fix: one more tick master clock frequency issue

f49ce93e · Fabien Le Mentec · 7ad46c48 · f49ce93e · f49ce93e
Commit f49ce93e authored Jan 05, 2016 by Fabien Le Mentec
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Showing with 7 additions and 8 deletions

user.tcl sim/isim/user.tcl +1 -0

absenc_master.vhd src/absenc_master.vhd +6 -8

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--- a/sim/isim/user.tcl
+++ b/sim/isim/user.tcl
@@ -16,3 +16,4 @@ source biss.tcl
 wave add /main/clk
 wave add /main/ma_clk
 wave add /main/ma_delayed_clk
+wave add /main/master/ma_half_match
\ No newline at end of file
--- a/src/absenc_master.vhd
+++ b/src/absenc_master.vhd
@@ -196,31 +196,29 @@ report "ma_fdiv'length too large" severity failure;
 -- generate edges using a counter from ma_fdiv/2 to 0

 ma_half_fdiv <= ma_fdiv srl 1;
+ma_half_match <= '1' when ma_half_count = 1 else '0';

 process
 begin
 wait until rising_edge(clk);

- ma_half_match <= '0';
-
- if ((rst or ma_clk_rst_en) = '1') then
-  ma_half_count <= ma_half_fdiv;
- elsif (ma_half_count = 0) then
+ if ((rst or ma_clk_rst_en or ma_half_match) = '1') then
  ma_half_count <= ma_half_fdiv;
-  ma_half_match <= '1';
 else
  ma_half_count <= ma_half_count - 1;
 end if;
+
 end process;

+
 process
 begin
 wait until rising_edge(clk);

 if ((rst or ma_clk_rst_en) = '1') then
  ma_clk_val <= ma_clk_rst_val;
- elsif (ma_half_match = '1') then
-  ma_clk_val <= not ma_clk_val;
+ else
+  ma_clk_val <= ma_clk_val xor ma_half_match;
 end if;

 end process;