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Absolute Encoder VHDL core
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Projects
Absolute Encoder VHDL core
Commits
38a1c55d
Commit
38a1c55d
authored
Nov 13, 2015
by
Fabien Le Mentec
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fix: use range instead of others for unconstrainted types allows vcom to compile
parent
ac9fe2e5
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7 changed files
with
9 additions
and
9 deletions
+9
-9
absenc_master_biss.vhd
src/absenc_master_biss.vhd
+1
-1
absenc_master_endat.vhd
src/absenc_master_endat.vhd
+1
-1
absenc_master_ssi.vhd
src/absenc_master_ssi.vhd
+1
-1
absenc_slave.vhd
src/absenc_slave.vhd
+2
-2
absenc_slave_biss.vhd
src/absenc_slave_biss.vhd
+1
-1
absenc_slave_endat.vhd
src/absenc_slave_endat.vhd
+1
-1
absenc_slave_ssi.vhd
src/absenc_slave_ssi.vhd
+2
-2
No files found.
src/absenc_master_biss.vhd
View file @
38a1c55d
...
...
@@ -162,7 +162,7 @@ begin
wait
until
rising_edge
(
clk
);
ma_clk_rst_en
<=
'0'
;
count_top
<=
(
others
=>
'0'
);
count_top
<=
(
count_top
'range
=>
'0'
);
count_rst
<=
'0'
;
sipo_latch
<=
'0'
;
...
...
src/absenc_master_endat.vhd
View file @
38a1c55d
...
...
@@ -203,7 +203,7 @@ begin
wait
until
rising_edge
(
clk
);
ma_clk_rst_en
<=
'0'
;
count_top
<=
(
others
=>
'0'
);
count_top
<=
(
count_top
'range
=>
'0'
);
count_rst
<=
'0'
;
sipo_latch
<=
'0'
;
gate
<=
'0'
;
...
...
src/absenc_master_ssi.vhd
View file @
38a1c55d
...
...
@@ -167,7 +167,7 @@ begin
wait
until
rising_edge
(
clk
);
ma_clk_rst_en
<=
'0'
;
count_top
<=
(
others
=>
'0'
);
count_top
<=
(
count_top
'range
=>
'0'
);
count_rst
<=
'0'
;
sipo_latch
<=
'0'
;
is_gray
<=
is_gray
;
...
...
src/absenc_slave.vhd
View file @
38a1c55d
...
...
@@ -408,8 +408,8 @@ begin
gate
<=
'0'
;
tm_top
<=
to_unsigned
(
DEFAULT_TM_TOP
,
tm_top
'length
);
count_rst
<=
'0'
;
count_top
<=
(
others
=>
'0'
);
piso_ini
<=
(
others
=>
'0'
);
count_top
<=
(
count_top
'range
=>
'0'
);
piso_ini
<=
(
piso_ini
'range
=>
'0'
);
piso_load
<=
'0'
;
for
i
in
0
to
ENC_MUX_COUNT
-
1
loop
...
...
src/absenc_slave_biss.vhd
View file @
38a1c55d
...
...
@@ -165,7 +165,7 @@ begin
wait
until
rising_edge
(
clk
);
miso
<=
'0'
;
count_top
<=
(
others
=>
'0'
);
count_top
<=
(
count_top
'range
=>
'0'
);
count_rst
<=
'0'
;
piso_load
<=
'0'
;
...
...
src/absenc_slave_endat.vhd
View file @
38a1c55d
...
...
@@ -228,7 +228,7 @@ begin
gate
<=
'0'
;
miso
<=
'0'
;
count_top
<=
(
others
=>
'0'
);
count_top
<=
(
count_top
'range
=>
'0'
);
count_rst
<=
'0'
;
piso_load
<=
'0'
;
...
...
src/absenc_slave_ssi.vhd
View file @
38a1c55d
...
...
@@ -161,10 +161,10 @@ begin
wait
until
rising_edge
(
clk
);
miso
<=
'0'
;
count_top
<=
(
others
=>
'0'
);
count_top
<=
(
count_top
'range
=>
'0'
);
count_rst
<=
'0'
;
piso_load
<=
'0'
;
piso_ini
<=
(
others
=>
'0'
);
piso_ini
<=
(
piso_ini
'range
=>
'0'
);
is_dot_bit
<=
is_dot_bit
;
case
curr_state
is
...
...
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