fix: EnDAT master sampling edge

28f238b2 · Fabien Le Mentec · f4e8ba75 · 28f238b2
Commit 28f238b2 authored Jul 29, 2016 by Fabien Le Mentec
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absenc_master.vhd src/absenc_master.vhd +1 -1

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--- a/src/absenc_master.vhd
+++ b/src/absenc_master.vhd
@@ -311,7 +311,7 @@ begin

 wait until rising_edge(clk);

- if (ma_clk_redge = '1') then
+ if (ma_clk_edge = '1') then
  sipo_val <= sipo_val(sipo_val'length - 2 downto 0) & miso;
 end if;