#!   /usr/bin/env	python
#    coding: utf8

import sys
import rr
import random
import time
import spi
import csr
import i2c
import gn4124
import fmc_adc
#import fmc_adc_test_suite
from pylab import *

if __name__ == '__main__':

    """
    Does successive burst writes to DDR3 controller. Requires hdl in 'misc' on ohwr for this project
    Functions remain in fmc_adc.py
    
    bug : ddr test contrroler hdl doesnt run on first attempt
    """


    GN4124_CSR = 0x0
    
    test_data = 1
    ddr3_calib_done = 0x3 <<2

    error_position =[]

    # Objects declaration
    spec = rr.Gennum() # bind to the SPEC board
    gn4124 = gn4124.CGN4124(spec, GN4124_CSR)
    fmc = fmc_adc.CFmcAdc100ks(spec)

    #PAGES
    write_size = int(raw_input("How many 16 bit writes ? : "))
    
    
    
    fmc.ram_write_config(1,1,0x1)
    fmc.ram_write_start()
    while fmc.ram_wr_finished()!=1:
    	time.sleep(.1)
    	print "clearing ram"
    
    raw_input("\nPress Enter for Ram Write")
        
    # Do a number of 16 byte writes
    for i in range(write_size):
    	start_write = i*8
    	end_write = (i*8)+7
    	fmc.ram_write_config(start_write,end_write,2)
    	fmc.ram_write_start()
    	while fmc.ram_wr_finished()!=1:
 		time.sleep(.025)
    
    print "Finished Ram Write"    
    print "Last address position = %d" %((write_size*8)-1)	    
      
    print '\nBye bye ...'
    sys.exit()
