#!   /usr/bin/env   python
#    coding: utf8

# Copyright CERN, 2012
# Author: Matthieu Cattin (CERN)
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
# Last modifications: 8/5/2012


# Control and status registers of the SPEC board
CARRIER_CSR=['Carrier control and status registers',{
        'CARRIER':[0x00, 'Carrier', {
                'PCB_REV':[0, 'PCB revision', 0xF],
                'RESERVED':[4, 'Reserved', 0xFFF],
                'TYPE':[16, 'Carrier type', 0xFFFF]}],
        'BITSTREAM_TYPE':[0x04, 'Bitstream type', {
                'BITSTREAM_TYPE':[0, 'Bitstream type', 0xFFFFFFFF]}],
        'BITSTREAM_DATE':[0x08, 'Bitstream date', {
                'BITSTREAM_DATE':[0, 'Bitstream date', 0xFFFFFFFF]}],
        'STAT':[0x0C, 'Status', {
                'FMC_PRES':[0, 'FMC presence (active low)', 0x1],
                'P2L_PLL_LCK':[1, 'P2L PLL locked', 0x1],
                'SYS_PLL_LCK':[2, 'System PLL locked', 0x1],
                'DDR3_CAL_DONE':[3, 'DDR3 calibration done', 0x1],
                'RESERVED':[4, 'Reserved', 0xFFFFFFF]}],
        'CTRL':[0x10, 'Control', {
                'LED_GREEN':[0, 'Green LED', 0x1],
                'LED_RED':[1, 'Red LED', 0x1],
                'DAC_CLR_N':[2, 'VCXO DAC clear (active low)', 0x1],
                'RESERVED':[3, 'Reserved', 0x1FFFFFFF]}]
        }]
