diff --git a/common/gn4124.py b/common/gn4124.py
index d92a5523ee0be75edb7c28536044c32c0c2a4498..9d86afe71e4d1854a0adc8b7f08c0a0c921b8f98 100644
--- a/common/gn4124.py
+++ b/common/gn4124.py
@@ -72,9 +72,11 @@ class CGN4124:
     PAGE_SIZE = 4096 # bytes
 
     def rd_reg(self, bar, addr):
+        #print("GN4124:READ: bar:0x%1X reg:0x%08X" % (bar,addr))
         return self.bus.iread(bar, addr, 4)
 
     def wr_reg(self, bar, addr, value):
+        #print("GN4124:WRITE: bar:0x%1X reg:0x%08X data:0x%08X" % (bar,addr,value))
         self.bus.iwrite(bar, addr, 4, value)
 
     def __init__(self, bus, csr):
@@ -176,6 +178,7 @@ class CGN4124:
     #    - Only supports 32-bit host address
     #    - Supports up to 128 items
     def add_dma_item(self, carrier_addr, host_addr, length, dma_dir, last_item):
+        #print("GN4124:ADD_DMA_ITEM: item cnt:%d"%self.dma_item_cnt)
         if(0 == self.dma_item_cnt):
             # write the first DMA item in the carrier
             self.dma_csr.wr_reg(self.R_DMA_CARRIER_START_ADDR, carrier_addr)
@@ -229,7 +232,7 @@ class CGN4124:
         #while(('Idle' == self.get_dma_status()) or
         #      ('Busy' == self.get_dma_status())):
         #    pass
-        self.dma_csr.wr_bit(self.R_DMA_CTL, self.DMA_CTL_START, 0)
+        #self.dma_csr.wr_bit(self.R_DMA_CTL, self.DMA_CTL_START, 0)
 
     # Abort DMA transfer
     def abort_dma(self):