1. 20 Aug, 2014 2 commits
  2. 18 Aug, 2014 2 commits
  3. 14 Aug, 2014 1 commit
  4. 08 Aug, 2014 1 commit
  5. 07 Aug, 2014 1 commit
  6. 06 Aug, 2014 1 commit
  7. 05 Aug, 2014 4 commits
  8. 04 Aug, 2014 1 commit
  9. 01 Aug, 2014 1 commit
    • Theodor-Adrian Stana's avatar
      Added package file and made adjustments to output enable logic · 6e1a5f9e
      Theodor-Adrian Stana authored
      The main logic changes are that the output enable lines are now set after
      the internal reset has been spent. This is to make sure that the lines are
      only controlled by the FPGA and no erroneous glitches are generated.
      
      Other changes include the addition of the RTM detection lines to the
      interface, which are now reflected in the CONV Status Reg, and connecting
      the reset from register line, which was previously unconnected.
      
      Then, component instantiations and the SDB declaration for conv_regs have
      been moved to the package file (conv_common_gw_pkg).
      6e1a5f9e
  10. 31 Jul, 2014 2 commits
  11. 30 Jul, 2014 1 commit
  12. 29 Jul, 2014 1 commit
    • Theodor-Adrian Stana's avatar
      Made interface simpler and added pulse inhibit on no fixed width pulse side as well · a04f0dc8
      Theodor-Adrian Stana authored
      The simpler interface is by means of providing only one pulse and pulse LED port
      per channel (both inputa and output). If there's an RTM involved, the splitting
      should be done outside the module.
      
      Then, the pulse inhibit is moved outside the g_with_fixed_pwidth block and provided
      in the generally synthesizable block, so it gets synthesized regardless of the value
      of the g_with_fixed_pwidth generic.
      a04f0dc8
  13. 25 Jul, 2014 1 commit
  14. 24 Jul, 2014 3 commits