- 06 Aug, 2014 1 commit
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Theodor-Adrian Stana authored
In addition, the base address of conv-regs has been changed to three hex digits
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- 05 Aug, 2014 4 commits
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Theodor-Adrian Stana authored
- BIDR default reset value - active values of several SR fields (SWITCHES, RTM, etc.) - formatting in some registers - also adapted .wb file to account for this
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Theodor-Adrian Stana authored
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Theodor-Adrian Stana authored
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Theodor-Adrian Stana authored
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- 04 Aug, 2014 1 commit
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Theodor-Adrian Stana authored
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- 01 Aug, 2014 1 commit
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Theodor-Adrian Stana authored
The main logic changes are that the output enable lines are now set after the internal reset has been spent. This is to make sure that the lines are only controlled by the FPGA and no erroneous glitches are generated. Other changes include the addition of the RTM detection lines to the interface, which are now reflected in the CONV Status Reg, and connecting the reset from register line, which was previously unconnected. Then, component instantiations and the SDB declaration for conv_regs have been moved to the package file (conv_common_gw_pkg).
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- 31 Jul, 2014 2 commits
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Theodor-Adrian Stana authored
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Theodor-Adrian Stana authored
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- 30 Jul, 2014 1 commit
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Theodor-Adrian Stana authored
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- 29 Jul, 2014 1 commit
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Theodor-Adrian Stana authored
The simpler interface is by means of providing only one pulse and pulse LED port per channel (both inputa and output). If there's an RTM involved, the splitting should be done outside the module. Then, the pulse inhibit is moved outside the g_with_fixed_pwidth block and provided in the generally synthesizable block, so it gets synthesized regardless of the value of the g_with_fixed_pwidth generic.
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- 25 Jul, 2014 1 commit
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Theodor-Adrian Stana authored
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- 24 Jul, 2014 3 commits
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Theodor-Adrian Stana authored
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Theodor-Adrian Stana authored
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Theodor-Adrian Stana authored
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