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conv-common-gw
Commit eb610e84 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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Implementation post-review. Main changes are to pull the falling and rising… 

Implementation post-review. Main changes are to pull the falling and rising edges of the asynch pulses directly from the conv_pulse_gen module as outputs and input those the burst controller. The top files have been modified accordingly. Also the pulse output now is correctly generated at the poutput port depending on PCB version and pulse width selection
parent 063828d3
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modules/conv_dyn_burst_ctrl.vhd
View file @ eb610e84
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modules/conv_pulse_gen.vhd
View file @ eb610e84
...@@ -60,6 +60,7 @@ ...@@ -60,6 +60,7 @@
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
use work.gencores_pkg.all;
entity conv_pulse_gen is entity conv_pulse_gen is
generic generic
...@@ -102,7 +103,10 @@ entity conv_pulse_gen is ...@@ -102,7 +103,10 @@ entity conv_pulse_gen is
-- latency: -- latency:
-- glitch filter disabled: none -- glitch filter disabled: none
-- glitch filter enabled: glitch filter length + 5 clk_i cycles -- glitch filter enabled: glitch filter length + 5 clk_i cycles
pulse_o : out std_logic pulse_o : out std_logic;
pulse_r_edge_p_o : out std_logic; --synced 1 cycle-long r edge output
pulse_f_edge_p_o : out std_logic
); );
end entity conv_pulse_gen; end entity conv_pulse_gen;
...@@ -165,16 +169,19 @@ architecture behav of conv_pulse_gen is ...@@ -165,16 +169,19 @@ architecture behav of conv_pulse_gen is
signal pulse_gf_off_d0 : std_logic; signal pulse_gf_off_d0 : std_logic;
signal pulse_gf_off_d1 : std_logic; signal pulse_gf_off_d1 : std_logic;
signal pulse_gf_off_d2 : std_logic; signal pulse_gf_off_d2 : std_logic;
signal gen_edge_gf_off_n : std_logic;
signal trig_gf_on : std_logic; signal trig_gf_on : std_logic;
signal trig_gf_on_d0 : std_logic; signal trig_gf_on_d0 : std_logic;
signal trig_gf_on_r_edge_p : std_logic; signal trig_gf_on_r_edge_p : std_logic;
signal trig_gf_on_f_edge_p : std_logic;
-- Pulse output signals -- Pulse output signals
signal pulse_gf_on : std_logic; signal pulse_gf_on : std_logic;
signal pulse_gf_off : std_logic; signal pulse_gf_off : std_logic;
signal pulse_gf_off_rst : std_logic; signal pulse_gf_off_rst : std_logic;
signal pulse_gf_off_r_edge_p : std_logic; signal pulse_gf_off_r_edge_p : std_logic;
signal pulse_gf_off_f_edge_p : std_logic;
-- Pulse length counter -- Pulse length counter
signal pulse_cnt : unsigned(f_log2_size(g_duty_cycle_div*g_pwidth)-1 downto 0); signal pulse_cnt : unsigned(f_log2_size(g_duty_cycle_div*g_pwidth)-1 downto 0);
...@@ -215,22 +222,38 @@ gen_with_fixed_pwidth : if (g_with_fixed_pwidth = true) generate ...@@ -215,22 +222,38 @@ gen_with_fixed_pwidth : if (g_with_fixed_pwidth = true) generate
end process p_pulse_gf_off; end process p_pulse_gf_off;
-- and synchronize the trigger in clk_i domain -- and synchronize the trigger in clk_i domain
p_sync_pulse_gf_off: process (clk_i) is -- p_sync_pulse_gf_off: process (clk_i) is
begin -- begin
if rising_edge(clk_i) then -- if rising_edge(clk_i) then
if (rst_n_i = '0') then -- if (rst_n_i = '0') then
pulse_gf_off_d0 <= '0'; -- pulse_gf_off_d0 <= '0';
pulse_gf_off_d1 <= '0'; -- pulse_gf_off_d1 <= '0';
pulse_gf_off_d2 <= '0'; -- pulse_gf_off_d2 <= '0';
pulse_gf_off_r_edge_p <= '0'; -- pulse_gf_off_r_edge_p <= '0';
elsif (en_i = '1') and (gf_en_n_i = '1') then -- elsif (en_i = '1') and (gf_en_n_i = '1') then
pulse_gf_off_d0 <= pulse_gf_off; -- pulse_gf_off_d0 <= pulse_gf_off;
pulse_gf_off_d1 <= pulse_gf_off_d0; -- pulse_gf_off_d1 <= pulse_gf_off_d0;
pulse_gf_off_d2 <= pulse_gf_off_d1; -- pulse_gf_off_d2 <= pulse_gf_off_d1;
pulse_gf_off_r_edge_p <= pulse_gf_off_d1 and (not pulse_gf_off_d2); -- pulse_gf_off_r_edge_p <= pulse_gf_off_d1 and (not pulse_gf_off_d2);
end if; -- end if;
end if; -- end if;
end process p_sync_pulse_gf_off; -- end process p_sync_pulse_gf_off;
gen_edge_gf_off_n <= rst_n_i or en_i or gf_en_n_i;
-- and synchronize the trigger in clk_i domain using sync_ffs general core
cmp_gc_sync_ffs : gc_sync_ffs
generic map
(
g_sync_edge => "positive"
)
port map(
clk_i => clk_i, -- clock from the destination clock domain
rst_n_i => gen_edge_gf_off_n, -- reset is acomibnation of rst_n_i,
-- en_i and gf_en_n_i
data_i => pulse_gf_off, -- async input
npulse_o => pulse_gf_off_f_edge_p,-- negative edge detect output
ppulse_o => pulse_gf_off_r_edge_p-- positive edge detect output
);
-- Trigger signal with glitch filter ON is input signal -- Trigger signal with glitch filter ON is input signal
trig_gf_on <= trig_a_i; trig_gf_on <= trig_a_i;
...@@ -245,10 +268,13 @@ gen_with_fixed_pwidth : if (g_with_fixed_pwidth = true) generate ...@@ -245,10 +268,13 @@ gen_with_fixed_pwidth : if (g_with_fixed_pwidth = true) generate
else else
trig_gf_on_d0 <= trig_gf_on; trig_gf_on_d0 <= trig_gf_on;
trig_gf_on_r_edge_p <= trig_gf_on and (not trig_gf_on_d0); trig_gf_on_r_edge_p <= trig_gf_on and (not trig_gf_on_d0);
trig_gf_on_f_edge_p <= (not trig_gf_on) and trig_gf_on_d0;
end if; end if;
end if; end if;
end process p_trig_gf_on; end process p_trig_gf_on;
pulse_r_edge_p_o <= pulse_gf_off_r_edge_p when gf_en_n_i = '1' else trig_gf_on_r_edge_p;
pulse_f_edge_p_o <= pulse_gf_off_f_edge_p when gf_en_n_i = '1' else trig_gf_on_f_edge_p;
--============================================================================ --============================================================================
-- Pulse width adjustment logic -- Pulse width adjustment logic
--============================================================================ --============================================================================
......
top/conv_common_gw.vhd
View file @ eb610e84
...@@ -43,10 +43,9 @@ ...@@ -43,10 +43,9 @@
-- 2014-07-24 Theodor Stana File created -- 2014-07-24 Theodor Stana File created
-- 2016-08-05 Denia Bouhired Moved inv ttl signals inside common gateware -- 2016-08-05 Denia Bouhired Moved inv ttl signals inside common gateware
-- and also added support for inv pulse LEDs -- and also added support for inv pulse LEDs
--Denia Bouhired Added support for one-wire thermometer register read out --Denia Bouhired Added support for one-wire thermometer register read out
-- 2016-12-20 Denia Bouhired Modified port list of conv_regs -- 2016-12-20 Denia Bouhired Modified port list of conv_regs
-- 2017-01-25 Denia Bouhired Added pulse_width_sel and burst_en_n_i (Disables hi-freq bursts for all board versions)
--============================================================================== --==============================================================================
-- TODO: - -- TODO: -
--============================================================================== --==============================================================================
...@@ -132,7 +131,7 @@ entity conv_common_gw is ...@@ -132,7 +131,7 @@ entity conv_common_gw is
gf_en_n_i : in std_logic; gf_en_n_i : in std_logic;
-- Burst mode enable signal. Mode disabled for all versions of board -- Burst mode enable signal. Mode disabled for all versions of board
burst_en_n_i : in std_logic; burst_en_n_i : in std_logic;
-- Pulse width selection, port low means 250ns, high means 1.2us. -- Pulse width selection, port low means 250ns, high means 1.2us.
pulse_width_sel_n_i : in std_logic; pulse_width_sel_n_i : in std_logic;
...@@ -320,8 +319,13 @@ architecture arch of conv_common_gw is ...@@ -320,8 +319,13 @@ architecture arch of conv_common_gw is
signal trig_chan_blo_redge_p : std_logic_vector(g_nr_chans-1 downto 0); signal trig_chan_blo_redge_p : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_man : std_logic_vector(g_nr_chans-1 downto 0); signal trig_man : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_pgen : std_logic_vector(g_nr_chans-1 downto 0); signal trig_pgen : std_logic_vector(g_nr_chans-1 downto 0);
signal burst_en_n : std_logic;
signal pulse_outp_cont : std_logic_vector(g_nr_chans-1 downto 0); signal pulse_outp_cont : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_sh_burst : std_logic_vector(g_nr_chans-1 downto 0); signal pulse_outp_sh_burst : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_r_edge_lg_p : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_f_edge_lg_p : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_r_edge_sh_p : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_f_edge_sh_p : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_sh : std_logic_vector(g_nr_chans-1 downto 0); signal pulse_outp_sh : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_lg_burst : std_logic_vector(g_nr_chans-1 downto 0); signal pulse_outp_lg_burst : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_lg : std_logic_vector(g_nr_chans-1 downto 0); signal pulse_outp_lg : std_logic_vector(g_nr_chans-1 downto 0);
...@@ -480,7 +484,7 @@ begin ...@@ -480,7 +484,7 @@ begin
generic map generic map
( (
-- Reset time: 50ns * 2 * (10**6) = 100 ms -- Reset time: 50ns * 2 * (10**6) = 100 ms
g_reset_time => 2*(10**6) g_reset_time => 2*(10**4)
) )
port map port map
( (
...@@ -520,12 +524,14 @@ begin ...@@ -520,12 +524,14 @@ begin
ttl_oen <= '0'; ttl_oen <= '0';
invttl_oen <= '0'; invttl_oen <= '0';
rear_oen <= '0'; rear_oen <= '0';
burst_en_n <= '0';
else else
global_oen <= '1'; global_oen <= '1';
if global_oen = '1' then if global_oen = '1' then
ttl_oen <= '1'; ttl_oen <= '1';
invttl_oen <= '1'; invttl_oen <= '1';
rear_oen <= '1'; rear_oen <= '1';
burst_en_n <= burst_en_n_i;
end if; end if;
end if; end if;
end if; end if;
...@@ -731,7 +737,9 @@ end generate gen_pulse_cnt; ...@@ -731,7 +737,9 @@ end generate gen_pulse_cnt;
pulse_err_p_o => pulse_outp_err_lg (i), pulse_err_p_o => pulse_outp_err_lg (i),
pulse_o => pulse_outp_lg(i) pulse_o => pulse_outp_lg(i),
pulse_r_edge_p_o => pulse_r_edge_lg_p(i),
pulse_f_edge_p_o => pulse_f_edge_lg_p(i)
); );
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
-- Instantiate burst control block for the channel -- Instantiate burst control block for the channel
...@@ -749,6 +757,8 @@ end generate gen_pulse_cnt; ...@@ -749,6 +757,8 @@ end generate gen_pulse_cnt;
rst_n_i => rst_20_n, rst_n_i => rst_20_n,
en_i => '1', en_i => '1',
pulse_burst_i => pulse_outp_lg(i), pulse_burst_i => pulse_outp_lg(i),
pulse_r_edge_p_i => pulse_r_edge_lg_p(i),
pulse_f_edge_p_i => pulse_f_edge_lg_p(i),
pulse_burst_o => pulse_outp_lg_burst(i), pulse_burst_o => pulse_outp_lg_burst(i),
burst_err_p_o => burst_outp_err_lg (i) burst_err_p_o => burst_outp_err_lg (i)
...@@ -780,7 +790,10 @@ end generate gen_pulse_cnt; ...@@ -780,7 +790,10 @@ end generate gen_pulse_cnt;
pulse_err_p_o => pulse_outp_err_sh (i), pulse_err_p_o => pulse_outp_err_sh (i),
pulse_o => pulse_outp_sh(i) pulse_o => pulse_outp_sh(i),
pulse_r_edge_p_o => pulse_r_edge_sh_p(i) ,
pulse_f_edge_p_o => pulse_f_edge_sh_p(i)
); );
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
-- Instantiate burst control block for the channel -- Instantiate burst control block for the channel
...@@ -798,6 +811,8 @@ end generate gen_pulse_cnt; ...@@ -798,6 +811,8 @@ end generate gen_pulse_cnt;
rst_n_i => rst_20_n, rst_n_i => rst_20_n,
en_i => '1', en_i => '1',
pulse_burst_i => pulse_outp_sh(i), pulse_burst_i => pulse_outp_sh(i),
pulse_r_edge_p_i => pulse_r_edge_sh_p(i),
pulse_f_edge_p_i => pulse_f_edge_sh_p(i),
pulse_burst_o => pulse_outp_sh_burst(i), pulse_burst_o => pulse_outp_sh_burst(i),
burst_err_p_o => burst_outp_err_sh (i) burst_err_p_o => burst_outp_err_sh (i)
); );
...@@ -805,29 +820,27 @@ end generate gen_pulse_cnt; ...@@ -805,29 +820,27 @@ end generate gen_pulse_cnt;
----------------------------------------------------------------------------------- -----------------------------------------------------------------------------------
--Select output depending on mode of operation. --Select output depending on mode of operation.
----------------------------------------------------------------------------------- -----------------------------------------------------------------------------------
p_output_sel : process (clk_20_i) is -- p_output_sel : process (burst_en_n, pulse_width_sel_n_i)
begin -- begin
if rising_edge(clk_20_i) then -- if burst_en_n = '1' then
--if (rst_20_n = '0') then -- pulse_outp(i) <= pulse_outp_cont(i);
-- pulse_outp(i) <= '0'; -- pmisse_p(i) <= pulse_outp_err_cont(i);
--else -- else
if burst_en_n_i = '1' then -- if pulse_width_sel_n_i='1' then
pulse_outp(i) <= pulse_outp_cont(i); -- pulse_outp(i) <= pulse_outp_lg_burst(i);
pmisse_p(i) <= pulse_outp_err_cont(i); -- pmisse_p(i) <= pulse_outp_err_lg(i) or burst_outp_err_lg(i);
elsif pulse_width_sel_n_i='1' then -- else
pulse_outp(i) <= pulse_outp_lg_burst(i); -- pulse_outp(i) <= pulse_outp_sh_burst(i);
pmisse_p(i) <= pulse_outp_err_lg(i) or burst_outp_err_lg(i); -- pmisse_p(i) <= pulse_outp_err_sh(i) or burst_outp_err_sh(i);
else -- end if;
pulse_outp(i) <= pulse_outp_sh_burst(i); -- end if;
pmisse_p(i) <= pulse_outp_err_sh(i) or burst_outp_err_sh(i); -- end process p_output_sel;
end if;
--end if;
end if;
end process p_output_sel;
pulse_outp(i) <= (pulse_outp_lg_burst(i) and pulse_width_sel_n_i) or
(pulse_outp_sh_burst(i) and not pulse_width_sel_n_i)
when burst_en_n = '0'
else pulse_outp_cont(i) ;
----------------------------------------------------------------------------------- -----------------------------------------------------------------------------------
-- Process to flash pulse LED when a pulse is output -- Process to flash pulse LED when a pulse is output
-- LED flash length: 26 ms -- LED flash length: 26 ms
......
top/conv_common_gw_pkg.vhd
View file @ eb610e84
...@@ -293,7 +293,9 @@ package conv_common_gw_pkg is ...@@ -293,7 +293,9 @@ package conv_common_gw_pkg is
-- latency: -- latency:
-- glitch filter disabled: none -- glitch filter disabled: none
-- glitch filter enabled: glitch filter length + 5 clk_i cycles -- glitch filter enabled: glitch filter length + 5 clk_i cycles
pulse_o : out std_logic pulse_o : out std_logic;
pulse_r_edge_p_o : out std_logic; --synced 1 cycle-long r edge output
pulse_f_edge_p_o : out std_logic
); );
end component conv_pulse_gen; end component conv_pulse_gen;
...@@ -324,6 +326,8 @@ package conv_common_gw_pkg is ...@@ -324,6 +326,8 @@ package conv_common_gw_pkg is
-- Enable input, pulse generation is enabled when '1' -- Enable input, pulse generation is enabled when '1'
en_i : in std_logic; en_i : in std_logic;
pulse_burst_i : in std_logic; pulse_burst_i : in std_logic;
pulse_r_edge_p_i : in std_logic;
pulse_f_edge_p_i : in std_logic;
pulse_burst_o : out std_logic; pulse_burst_o : out std_logic;
......
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