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conv-common-gw
Commit dca98fbc authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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Top file and package modified, so as to add burst support for wide pulses as well as the short ones

parent 3695b894
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Showing with 68 additions and 34 deletions
top/conv_common_gw.vhd
View file @ dca98fbc
......@@ -80,22 +80,25 @@ entity conv_common_gw is
-- Generate pulse repetition logic with fixed output pulse width
g_pgen_fixed_width : boolean := true ;
-- Pulse width at pulse generator output (valid with fixed output pulse width)
g_pgen_pwidth : natural range 2 to 40 := 24;
g_pgen_pwidth_lg : natural range 2 to 40 := 24;
g_pgen_pwidth_sh : natural range 2 to 40 := 5;
-- Duty cycle divider ratio for pulse generator
-- output pulse will be limited to 1/g_pgen_duty_cycle_div
g_pgen_duty_cycle_div : natural range 10 to 300 := 16;--changes maximum frequency to ~52k
g_pgen_duty_cycle_div_lg : natural range 10 to 300 := 16;--changes maximum frequency to ~52k
g_pgen_duty_cycle_div_sh : natural range 2 to 300 := 2;
-- Pulse generator glitch filter length in number of clk_20_i cycles
g_pgen_gf_len : integer := 4;
-- Burst-mode-specific generics:
-- Temperature rise resulting from 250ns pulse
g_burstctrl_1_pulse_temp_rise :in unsigned (19 downto 0) := x"2670"; -- Check every "g_eval_burst_len" pulses
g_temp_decre_step_lg : t_temp_decre_step :=(0,0,0,0,0,0,0,5750,100,79,13,12,4,5,13);
g_temp_decre_step_sh : t_temp_decre_step :=(0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0);
-- Single pulse temperature rise
g_burstctrl_1_pulse_temp_rise_lg :in unsigned (19 downto 0) := x"23040"; --For long 1.2us pulses
g_burstctrl_1_pulse_temp_rise_sh :in unsigned (19 downto 0) := x"01388"; --For short 250ns pulses
-- Maximum temperature allowed (scaled)
g_burstctrl_max_temp :in unsigned (39 downto 0) :=x"02540BE400";
g_burstctrl_max_temp_lg_sh :in unsigned (39 downto 0) :=x"02540BE400"; --For both long 1.2us pulses and short 250ns
-- Generate logic with pulse counters
g_with_pulse_cnt : boolean := false;
......@@ -286,7 +289,7 @@ architecture arch of conv_common_gw is
of unsigned(31 downto 0);
type t_ch_pcr is array(c_max_nr_chans-1 downto 0)
of std_logic_vector(31 downto 0);
-- Latest timestamp
type t_lts_tai is array(c_max_nr_chans-1 downto 0)
of std_logic_vector(39 downto 0);
......@@ -313,10 +316,11 @@ architecture arch of conv_common_gw is
signal trig_chan_blo_redge_p : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_man : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_pgen : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_sh : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_250ns : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_250ns : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_sh : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_1200ns : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_lg : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_d0 : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_redge_p : std_logic_vector(g_nr_chans-1 downto 0);
......@@ -324,9 +328,10 @@ architecture arch of conv_common_gw is
signal inv_pulse_outp_d0 : std_logic_vector(g_nr_inv_chans-1 downto 0);
signal inv_pulse_outp_fedge_p : std_logic_vector(g_nr_inv_chans-1 downto 0);
signal pmisse_p : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_err : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_err_lg : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_err_sh : std_logic_vector(g_nr_chans-1 downto 0);
signal burst_outp_err : std_logic_vector(g_nr_chans-1 downto 0);
signal burst_outp_err_lg : std_logic_vector(g_nr_chans-1 downto 0);
signal burst_outp_err_sh : std_logic_vector(g_nr_chans-1 downto 0);
-- Output enable signals
signal global_oen : std_logic;
......@@ -471,7 +476,7 @@ begin
generic map
(
-- Reset time: 50ns * 2 * (10**6) = 100 ms
g_reset_time => 2*(10**6)
g_reset_time => 2*(10**4)
)
port map
(
......@@ -667,12 +672,12 @@ end generate gen_pulse_cnt;
-- Instantiate pulse generator block for the channel for normal continuous mode
cmp_pulse_gen_1200ns : conv_pulse_gen
cmp_pulse_gen_lg : conv_pulse_gen
generic map
(
g_with_fixed_pwidth => g_pgen_fixed_width,
g_pwidth => g_pgen_pwidth,
g_duty_cycle_div => g_pgen_duty_cycle_div
g_pwidth => g_pgen_pwidth_lg,
g_duty_cycle_div => g_pgen_duty_cycle_div_lg
)
port map
(
......@@ -685,17 +690,37 @@ end generate gen_pulse_cnt;
trig_a_i => trig_pgen(i),
pulse_err_p_o => pulse_outp_err (i),
pulse_err_p_o => pulse_outp_err_lg (i),
pulse_o => pulse_outp_1200ns(i)
pulse_o => pulse_outp_lg(i)
);
----------------------------------------------------------------------------------
-- Instantiate burst control block for the channel
cmp_burst_ctrl_lg : conv_dyn_burst_ctrl
generic map
(
g_pwidth => g_pgen_pwidth_lg,
g_temp_decre_step => g_temp_decre_step_lg,
g_1_pulse_temp_rise => g_burstctrl_1_pulse_temp_rise_lg,
g_max_temp => g_burstctrl_max_temp_lg_sh
)
port map
(
clk_i => clk_20_i,
rst_n_i => rst_20_n,
en_i => '1',
pulse_burst_i => pulse_outp_lg(i),
pulse_burst_o => pulse_outp_1200ns(i),
burst_err_p_o => burst_outp_err_lg (i)
);
-------------------------------------------------------------------------------------
-- In burst mode, pulses are shorter, 250ns wide, and have a 50% duty cycle
-------------------------------------------------------------------------------------
--Instantiate pulse generator block for minimum pulse width and minimum allowed duty cycle
cmp_pulse_gen_250ns : conv_pulse_gen
cmp_pulse_gen_sh : conv_pulse_gen
generic map
(
g_with_fixed_pwidth => g_pgen_fixed_width,
......@@ -719,12 +744,13 @@ end generate gen_pulse_cnt;
);
----------------------------------------------------------------------------------
-- Instantiate burst control block for the channel
cmp_burst_ctrl : conv_dyn_burst_ctrl
cmp_burst_ctrl_sh : conv_dyn_burst_ctrl
generic map
(
g_pwidth => g_pgen_pwidth_sh,
g_1_pulse_temp_rise => g_burstctrl_1_pulse_temp_rise,
g_max_temp => g_burstctrl_max_temp
g_temp_decre_step => g_temp_decre_step_sh,
g_1_pulse_temp_rise => g_burstctrl_1_pulse_temp_rise_sh,
g_max_temp => g_burstctrl_max_temp_lg_sh
)
port map
(
......@@ -733,15 +759,14 @@ end generate gen_pulse_cnt;
en_i => '1',
pulse_burst_i => pulse_outp_sh(i),
pulse_burst_o => pulse_outp_250ns(i),
temp_rise_c => open,
burst_err_p_o => burst_outp_err (i)
burst_err_p_o => burst_outp_err_sh (i)
);
pulse_outp(i) <= pulse_outp_1200ns(i) when burst_en_n_i='1' else pulse_outp_250ns(i);
pmisse_p(i) <= pulse_outp_err (i) when burst_en_n_i='1' else pulse_outp_err_sh(i) or burst_outp_err(i);
pmisse_p(i) <= pulse_outp_err_lg(i) or burst_outp_err_lg(i) when burst_en_n_i='1' else pulse_outp_err_sh(i) or burst_outp_err_sh(i);
-----------------------------------------------------------------------------------
......
top/conv_common_gw_pkg.vhd
View file @ dca98fbc
......@@ -32,6 +32,7 @@
-- 2014-08-01 Theodor Stana File created
-- 2016-11 Denia Bouhired Added component for dynamic burst control module
-- 2016-12-20 Denia Bouhired Modified port list of conv_regs
-- 2017-01-23 Denia Bouhired Modified conv_common_gw, added array type for thermal model
--==============================================================================
-- TODO: -
--==============================================================================
......@@ -54,7 +55,12 @@ package conv_common_gw_pkg is
-- _incompatible_ with BLO and RS-485 pulse repeaters and you will need to
-- _reimplement_ the conv_regs module
constant c_max_nr_chans : natural := 6;
--============================================================================
--Type declarations
--============================================================================
--Array of constants for temperature model implemented for short pulse mode
type t_temp_decre_step is array (0 to 14) of integer;
--============================================================================
-- Component declarations
......@@ -77,21 +83,24 @@ package conv_common_gw_pkg is
-- Generate pulse repetition logic with fixed output pulse width
g_pgen_fixed_width : boolean;
-- Pulse width at pulse generator output (valid with fixed output pulse width)
g_pgen_pwidth : natural range 2 to 40 := 24; --**DB: was 20 to 40
g_pgen_pwidth_lg : natural range 2 to 40 := 24; --**DB: was 20 to 40
g_pgen_pwidth_sh : natural range 2 to 40 := 5;
-- Duty cycle divider ratio for pulse generator
-- output pulse will be limited to 1/g_pgen_duty_cycle_div
g_pgen_duty_cycle_div : natural := 200;
g_pgen_duty_cycle_div_lg : natural := 200;
g_pgen_duty_cycle_div_sh : natural range 2 to 300 := 2;
-- Pulse generator glitch filter length in number of clk_20_i cycles
g_pgen_gf_len : integer := 4;
-- Burst-mode-specific generics:
g_temp_decre_step_lg : t_temp_decre_step :=(0,0,0,0,0,0,0,5750,100,79,13,12,4,5,13);
g_temp_decre_step_sh : t_temp_decre_step :=(0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0);
-- Temperature rise resulting from 250ns pulse
g_burstctrl_1_pulse_temp_rise :in unsigned (19 downto 0); -- Check every "g_eval_burst_len" pulses
g_burstctrl_1_pulse_temp_rise_lg :in unsigned (19 downto 0) := x"23040"; -- Check every "g_eval_burst_len" pulses
g_burstctrl_1_pulse_temp_rise_sh :in unsigned (19 downto 0) := x"01388"; --For short 250ns pulses
-- Maximum temperature allowed (scaled)
g_burstctrl_max_temp :in unsigned (39 downto 0);
g_burstctrl_max_temp_lg_sh :in unsigned (39 downto 0);
-- Generate logic with pulse counters
g_with_pulse_cnt : boolean := false;
......@@ -295,8 +304,9 @@ package conv_common_gw_pkg is
(
-- Short pulse width, in number of clk_i cycles
-- Default short pulse width (20 MHz clock): 250 ns = 5 clk cycles
g_pwidth : natural range 2 to 40 := 5;
g_pwidth : natural range 2 to 40 := 5;
-- Thermal model constants, depend on mode selected short or long.
g_temp_decre_step : t_temp_decre_step;
-- Temperature rise resulting from with 250ns pulse
g_1_pulse_temp_rise :in unsigned (19 downto 0); -- Check every "g_eval_burst_len" pulses
......@@ -314,7 +324,6 @@ package conv_common_gw_pkg is
pulse_burst_i : in std_logic;
pulse_burst_o : out std_logic;
temp_rise_c : out unsigned (39 downto 0) ;
-- Burst error output, pulses high for one clock cycle when a pulse arrives
-- within a burst rejection phase
......
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