doc: Add info about fail-safe lines in LSR

dc4bfb25 · Theodor-Adrian Stana · 052a9c2c · dc4bfb25 · dc4bfb25
Commit dc4bfb25 authored Sep 26, 2014 by Theodor-Adrian Stana
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conv-common-gw.tex doc/conv-common-gw.tex +23 -4

conv-regs.tex doc/conv-regs.tex +18 -5

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--- a/doc/conv-common-gw.tex
+++ b/doc/conv-common-gw.tex
@@ -593,8 +593,8 @@ as part of \textit{conv\_regs} are intended to be active-high logic, so adaptati
 in logic external to the \textit{conv\_common\_gw} when an external connection is needed.

 The inputs that connect to bits in the status register are shown in Table~\ref{tbl:conv-regs-ext-inputs}.
-Should some of these inputs not be used, such as for example the failsafe lines in the case of CONV-TTL-BLO~\cite{conv-ttl-blo-ohwr},
-the corresponding lines should be connected to all-zeroes.
+Should some of these inputs not be used, such as for example the rear-panel failsafe lines in the case of
+CONV-TTL-BLO~\cite{conv-ttl-blo-ohwr}, the corresponding lines should be connected to all-zeroes.

 The \textit{g\_board\_id} and \textit{g\_gwvers} generics connect to registers in
 \textit{conv\_regs} as shown in Figure~\ref{fig:bidr-gwvers}.
@@ -613,7 +613,9 @@ The \textit{g\_board\_id} and \textit{g\_gwvers} generics connect to registers i
      line\_front\_i & LSR.FRONT & State of front-panel channel lines at FPGA input \\
      line\_inv\_i & LSR.FRONTINV & State of front-panel general-purpose inverter channels at FPGA input \\
      line\_rear\_i & LSR.REAR & State of rear-panel channel lines at FPGA input \\
-      line\_rear\_fs\_i & LSR.REARFS & State of fail-safe rear-panel inputs (whether a cable is plugged in or not) \\
+      line\_front\_fs\_i & LSR.FRONTFS & State of front-panel channel failsafe lines at FPGA input \\
+      line\_inv\_fs\_i & LSR.FRONTINVFS & State of front-panel general-purpose inverter failsafe lines at FPGA input \\
+      line\_rear\_fs\_i & LSR.REARFS & State of rear-panel input failsafe lines (whether a cable is plugged in or not) \\
      sw\_other\_i & OSWR & State of other on-board switches \\
      \hline
    \end{tabular}
@@ -631,10 +633,27 @@ bits or fields in \textit{conv\_regs} are set to a 'safe' value of '0'. Consult
 for details on how this is done and which are the fields concerned.

 Note that the logic allows less than 6 pulse repetition channels, but not more.
-If \textit{g\_nr\_chans < 6}, then the rest of the bits are automatically set to '0',
+If \textit{g\_nr\_chans $<$ 6}, then the rest of the bits are automatically set to '0',
 as in the case a \textit{g\_with\_*} generic is \textit{false}. If \textit{g\_nr\_chans $>$ 6}
 a synthesis error will be thrown.

+\subsubsection{Fail-safe lines in the line status register}
+
+The CONV-TTL-RS485~\cite{conv-ttl-rs485-ohwr} board has a an extra RS-485 transceiver per each
+channel input and output line, dedicated to detecting whether a line is in a fault state, or whether
+a cable is not plugged in.
+
+This in RS-485 parlance is called the fail-safe state and half the bits in the
+line status register (LSR -- see Appendix~\ref{app:conv-regs-lsr}) take their name after it. Designers of
+future converter boards would implement similar features for all the inputs might want to implement a 
+similar feature on future converter boards. For this, bits are provided in the LSR as shown in Table~\ref{tbl:conv-regs-ext-inputs}.
+If no such feature exists, or if the feature is only implemented for one of the two panels (front or rear),
+the non-used lines in Table~\ref{tbl:conv-regs-ext-inputs} can simply be connected to all-zeroes.
+
+Note that the register limits the user to six pulse repetition channels and four general-purpose inverter
+channels. Should more be needed, another \textit{conv\_common\_gw} module should be used, as shown in
+Appendix~\ref{app:more-than-six-chans}.
+
 %==============================================================================
 \subsection{MultiBoot}
 \label{subsec:multiboot}

--- a/doc/conv-regs.tex
+++ b/doc/conv-regs.tex
@@ -1522,11 +1522,11 @@ WRTAG
 \begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
 31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
 \hline
-\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
+\multicolumn{6}{|c|}{\cellcolor{gray!25}REARFS[5:0]} & \multicolumn{2}{|c|}{\cellcolor{gray!25}FRONTINVFS[3:2]}\\
 \hline
 23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
 \hline
-\multicolumn{1}{|c}{-} & - & \multicolumn{6}{|c|}{\cellcolor{gray!25}REARFS[5:0]}\\
+\multicolumn{2}{|c|}{\cellcolor{gray!25}FRONTINVFS[1:0]} & \multicolumn{6}{|c|}{\cellcolor{gray!25}FRONTFS[5:0]}\\
 \hline
 15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
 \hline
@@ -1563,10 +1563,24 @@ Line state at board input\\      Bit 0 -- channel 1\\      Bit 1 -- channel 2\\
 \end{small}
 \item \begin{small}
 {\bf 
+FRONTFS
+} [\emph{read-only}]: Front panel input failsafe state
+\\
+High if line is in failsafe mode (e.g., no cable plugged in)\\      Bit 0 -- channel 1\\      Bit 1 -- channel 2\\      etc.
+\end{small}
+\item \begin{small}
+{\bf 
+FRONTINVFS
+} [\emph{read-only}]: Front panel inverter input failsafe state
+\\
+High if line is in failsafe mode (e.g., no cable plugged in)\\      Bit 0 -- channel 1\\      Bit 1 -- channel 2\\      etc.
+\end{small}
+\item \begin{small}
+{\bf 
 REARFS
-} [\emph{read-only}]: Input failsafe state
+} [\emph{read-only}]: Rear panel input failsafe state
 \\
-High if line is in failsafe mode (no cable plugged in)\\      Bit 0 -- channel 1\\      Bit 1 -- channel 2\\      etc.
+High if line is in failsafe mode (e.g., no cable plugged in)\\      Bit 0 -- channel 1\\      Bit 1 -- channel 2\\      etc.
 \end{small}
 \item \begin{small}
 \textbf{Unimplemented bits}: write as '0', read undefined
@@ -1574,7 +1588,6 @@ High if line is in failsafe mode (no cable plugged in)\\      Bit 0 -- channel 1
 \end{itemize}
 \vspace{11pt}

-\pagebreak
 \subsubsection{OSWR -- Other Switches Register}
 \label{app:conv-regs-oswr}