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conv-common-gw
Commit d1913485 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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Modified top files to use more generic front names rather than signal types that… 

Modified top files to use more generic front names rather than signal types that are more specific to a particular board, Eg: ttl and blo for conv-ttl-blo. Now using front and rear instead. this can now be reused with conv-ttl-rs485
parent 9b832b6a
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top/conv_common_gw.vhd
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top/conv_common_gw_pkg.vhd
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...@@ -419,54 +419,54 @@ package conv_common_gw_pkg is ...@@ -419,54 +419,54 @@ package conv_common_gw_pkg is
-- Ports for PASS_THROUGH field: 'Manual Pulse Trigger' in reg: 'CR' -- Ports for PASS_THROUGH field: 'Manual Pulse Trigger' in reg: 'CR'
reg_cr_mpt_o : out std_logic_vector(7 downto 0); reg_cr_mpt_o : out std_logic_vector(7 downto 0);
reg_cr_mpt_wr_o : out std_logic; reg_cr_mpt_wr_o : out std_logic;
-- Port for std_logic_vector field: 'TTL pulse counter value' in reg: 'CH1TTLPCR' -- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH1FPPCR'
reg_ch1ttlpcr_o : out std_logic_vector(31 downto 0); reg_ch1fppcr_o : out std_logic_vector(31 downto 0);
reg_ch1ttlpcr_i : in std_logic_vector(31 downto 0); reg_ch1fppcr_i : in std_logic_vector(31 downto 0);
reg_ch1ttlpcr_load_o : out std_logic; reg_ch1fppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'TTL pulse counter value' in reg: 'CH2TTLPCR' -- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH2FPPCR'
reg_ch2ttlpcr_o : out std_logic_vector(31 downto 0); reg_ch2fppcr_o : out std_logic_vector(31 downto 0);
reg_ch2ttlpcr_i : in std_logic_vector(31 downto 0); reg_ch2fppcr_i : in std_logic_vector(31 downto 0);
reg_ch2ttlpcr_load_o : out std_logic; reg_ch2fppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'TTL pulse counter value' in reg: 'CH3TTLPCR' -- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH3FPPCR'
reg_ch3ttlpcr_o : out std_logic_vector(31 downto 0); reg_ch3fppcr_o : out std_logic_vector(31 downto 0);
reg_ch3ttlpcr_i : in std_logic_vector(31 downto 0); reg_ch3fppcr_i : in std_logic_vector(31 downto 0);
reg_ch3ttlpcr_load_o : out std_logic; reg_ch3fppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'TTL pulse counter value' in reg: 'CH4TTLPCR' -- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH4FPPCR'
reg_ch4ttlpcr_o : out std_logic_vector(31 downto 0); reg_ch4fppcr_o : out std_logic_vector(31 downto 0);
reg_ch4ttlpcr_i : in std_logic_vector(31 downto 0); reg_ch4fppcr_i : in std_logic_vector(31 downto 0);
reg_ch4ttlpcr_load_o : out std_logic; reg_ch4fppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'TTL pulse counter value' in reg: 'CH5TTLPCR' -- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH5FPPCR'
reg_ch5ttlpcr_o : out std_logic_vector(31 downto 0); reg_ch5fppcr_o : out std_logic_vector(31 downto 0);
reg_ch5ttlpcr_i : in std_logic_vector(31 downto 0); reg_ch5fppcr_i : in std_logic_vector(31 downto 0);
reg_ch5ttlpcr_load_o : out std_logic; reg_ch5fppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'TTL pulse counter value' in reg: 'CH6TTLPCR' -- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH6FPPCR'
reg_ch6ttlpcr_o : out std_logic_vector(31 downto 0); reg_ch6fppcr_o : out std_logic_vector(31 downto 0);
reg_ch6ttlpcr_i : in std_logic_vector(31 downto 0); reg_ch6fppcr_i : in std_logic_vector(31 downto 0);
reg_ch6ttlpcr_load_o : out std_logic; reg_ch6fppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'BLO pulse counter value' in reg: 'CH1BLOPCR' -- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH1RPPCR'
reg_ch1blopcr_o : out std_logic_vector(31 downto 0); reg_ch1rppcr_o : out std_logic_vector(31 downto 0);
reg_ch1blopcr_i : in std_logic_vector(31 downto 0); reg_ch1rppcr_i : in std_logic_vector(31 downto 0);
reg_ch1blopcr_load_o : out std_logic; reg_ch1rppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'BLO pulse counter value' in reg: 'CH2BLOPCR' -- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH2RPPCR'
reg_ch2blopcr_o : out std_logic_vector(31 downto 0); reg_ch2rppcr_o : out std_logic_vector(31 downto 0);
reg_ch2blopcr_i : in std_logic_vector(31 downto 0); reg_ch2rppcr_i : in std_logic_vector(31 downto 0);
reg_ch2blopcr_load_o : out std_logic; reg_ch2rppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'BLO pulse counter value' in reg: 'CH3BLOPCR' -- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH3RPPCR'
reg_ch3blopcr_o : out std_logic_vector(31 downto 0); reg_ch3rppcr_o : out std_logic_vector(31 downto 0);
reg_ch3blopcr_i : in std_logic_vector(31 downto 0); reg_ch3rppcr_i : in std_logic_vector(31 downto 0);
reg_ch3blopcr_load_o : out std_logic; reg_ch3rppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'BLO pulse counter value' in reg: 'CH4BLOPCR' -- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH4RPPCR'
reg_ch4blopcr_o : out std_logic_vector(31 downto 0); reg_ch4rppcr_o : out std_logic_vector(31 downto 0);
reg_ch4blopcr_i : in std_logic_vector(31 downto 0); reg_ch4rppcr_i : in std_logic_vector(31 downto 0);
reg_ch4blopcr_load_o : out std_logic; reg_ch4rppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'BLO pulse counter value' in reg: 'CH5BLOPCR' -- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH5RPPCR'
reg_ch5blopcr_o : out std_logic_vector(31 downto 0); reg_ch5rppcr_o : out std_logic_vector(31 downto 0);
reg_ch5blopcr_i : in std_logic_vector(31 downto 0); reg_ch5rppcr_i : in std_logic_vector(31 downto 0);
reg_ch5blopcr_load_o : out std_logic; reg_ch5rppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'BLO pulse counter value' in reg: 'CH6BLOPCR' -- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH6RPPCR'
reg_ch6blopcr_o : out std_logic_vector(31 downto 0); reg_ch6rppcr_o : out std_logic_vector(31 downto 0);
reg_ch6blopcr_i : in std_logic_vector(31 downto 0); reg_ch6rppcr_i : in std_logic_vector(31 downto 0);
reg_ch6blopcr_load_o : out std_logic; reg_ch6rppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'TAI seconds counter bits 31..0' in reg: 'TVLR' -- Port for std_logic_vector field: 'TAI seconds counter bits 31..0' in reg: 'TVLR'
reg_tvlr_o : out std_logic_vector(31 downto 0); reg_tvlr_o : out std_logic_vector(31 downto 0);
reg_tvlr_i : in std_logic_vector(31 downto 0); reg_tvlr_i : in std_logic_vector(31 downto 0);
......
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