Commit d1913485 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag

Modified top files to use more generic front names rather than signal types that…

Modified top files to use more generic front names rather than signal types that are more specific to a particular board, Eg: ttl and blo for conv-ttl-blo. Now using front and rear instead. this can now be reused with conv-ttl-rs485
parent 9b832b6a
......@@ -354,7 +354,7 @@ architecture arch of conv_common_gw is
-- Output enable signals
signal global_oen : std_logic;
signal ttl_oen, invttl_oen : std_logic;
signal front_oen, invttl_oen : std_logic;
signal rear_oen : std_logic;
-- I2C bridge signals
......@@ -386,19 +386,19 @@ architecture arch of conv_common_gw is
signal pmisse_bits_or : std_logic;
--signals for pulse counters
signal rst_ttl_cnt : std_logic_vector(c_max_nr_chans-1 downto 0);
signal rst_blo_cnt : std_logic_vector(c_max_nr_chans-1 downto 0);
signal rst_front_cnt : std_logic_vector(c_max_nr_chans-1 downto 0);
signal rst_rear_cnt : std_logic_vector(c_max_nr_chans-1 downto 0);
signal pulse_cnt : t_pulse_cnt;
signal ttl_pulse_cnt : t_pulse_cnt;
signal blo_pulse_cnt : t_pulse_cnt;
signal ttl_pulse_cnt_offset : t_pulse_cnt;
signal blo_pulse_cnt_offset : t_pulse_cnt;
signal ttl_pulse_c : t_pulse_cnt;
signal blo_pulse_c : t_pulse_cnt;
signal ch_ttl_pcr : t_ch_pcr;
signal ch_ttl_pcr_ld : std_logic_vector(c_max_nr_chans-1 downto 0);
signal ch_blo_pcr : t_ch_pcr;
signal ch_blo_pcr_ld : std_logic_vector(c_max_nr_chans-1 downto 0);
signal front_pulse_cnt : t_pulse_cnt;
signal rear_pulse_cnt : t_pulse_cnt;
signal front_pulse_cnt_offset : t_pulse_cnt;
signal rear_pulse_cnt_offset : t_pulse_cnt;
signal front_pulse_c : t_pulse_cnt;
signal rear_pulse_c : t_pulse_cnt;
signal ch_front_pcr : t_ch_pcr;
signal ch_front_pcr_ld : std_logic_vector(c_max_nr_chans-1 downto 0);
signal ch_rear_pcr : t_ch_pcr;
signal ch_rear_pcr_ld : std_logic_vector(c_max_nr_chans-1 downto 0);
signal mpt_ld : std_logic;
signal mpt : std_logic_vector( 7 downto 0);
signal tvlr : std_logic_vector(31 downto 0);
......@@ -519,7 +519,7 @@ begin
-- TRIG0_in(4) <= pulse_outp_err_lg_p(5);
-- TRIG0_in(5) <= burst_outp_err_lg_p(5);
-- TRIG0_in(6) <= pulse_outp_lg(5);
-- TRIG0_in(7) <= ch_ttl_pcr_ld(5);
-- TRIG0_in(7) <= ch_front_pcr_ld(5);
--============================================================================
......@@ -585,14 +585,14 @@ begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
global_oen <= '0';
ttl_oen <= '0';
front_oen <= '0';
invttl_oen <= '0';
rear_oen <= '0';
burst_en_n <= '0';
else
global_oen <= '1';
if global_oen = '1' then
ttl_oen <= '1';
front_oen <= '1';
invttl_oen <= '1';
rear_oen <= '1';
burst_en_n <= burst_en_n_i;
......@@ -603,7 +603,7 @@ begin
-- Assign OEN outputs
global_ch_oen_o <= global_oen;
pulse_front_oen_o <= ttl_oen;
pulse_front_oen_o <= front_oen;
inv_oen_o <= invttl_oen;
pulse_rear_oen_o <= rear_oen;
......@@ -711,25 +711,25 @@ gen_pulse_chan_logic : for i in 0 to g_nr_chans-1 generate
gen_pulse_cnt : if (g_with_pulse_cnt = true) generate
rst_ttl_cnt(i) <= rst_20 or ch_ttl_pcr_ld(i);
rst_blo_cnt(i) <= rst_20 or ch_blo_pcr_ld(i);
rst_front_cnt(i) <= rst_20 or ch_front_pcr_ld(i);
rst_rear_cnt(i) <= rst_20 or ch_rear_pcr_ld(i);
cmp_pulse_cnt_ttl: fastevent_counter
cmp_pulse_cnt_front: fastevent_counter
port map(
sysclk_i => clk_20_i,
rstcount_i => rst_ttl_cnt(i),
rstcount_i => rst_front_cnt(i),
en_i => '1',
trig_i => pulse_front_i(i),
count_int_o => ttl_pulse_c(i)
count_int_o => front_pulse_c(i)
);
cmp_pulse_cnt_blo: fastevent_counter
cmp_pulse_cnt_rear: fastevent_counter
port map(
sysclk_i => clk_20_i,
rstcount_i => rst_blo_cnt(i),
rstcount_i => rst_rear_cnt(i),
en_i => '1',
trig_i => pulse_rear_i(i),
count_int_o => blo_pulse_c(i)
count_int_o => rear_pulse_c(i)
);
-- First, the pulse counters for the used channels (up to g_nr_chans)
......@@ -739,17 +739,17 @@ cmp_pulse_cnt_blo: fastevent_counter
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
pulse_cnt(i) <= (others => '0');
ttl_pulse_cnt(i) <= (others => '0');
blo_pulse_cnt(i) <= (others => '0');
ttl_pulse_cnt_offset(i) <= (others => '0');
blo_pulse_cnt_offset(i) <= (others => '0');
elsif (ch_ttl_pcr_ld(i) = '1') then
ttl_pulse_cnt_offset(i) <= unsigned(ch_ttl_pcr(i));
elsif (ch_blo_pcr_ld(i) = '1') then
blo_pulse_cnt_offset(i) <= unsigned(ch_blo_pcr(i));
front_pulse_cnt(i) <= (others => '0');
rear_pulse_cnt(i) <= (others => '0');
front_pulse_cnt_offset(i) <= (others => '0');
rear_pulse_cnt_offset(i) <= (others => '0');
elsif (ch_front_pcr_ld(i) = '1') then
front_pulse_cnt_offset(i) <= unsigned(ch_front_pcr(i));
elsif (ch_rear_pcr_ld(i) = '1') then
rear_pulse_cnt_offset(i) <= unsigned(ch_rear_pcr(i));
else
ttl_pulse_cnt(i) <= ttl_pulse_cnt_offset(i)+ ttl_pulse_c(i);
blo_pulse_cnt(i) <= blo_pulse_cnt_offset(i)+ blo_pulse_c(i);
front_pulse_cnt(i) <= front_pulse_cnt_offset(i)+ front_pulse_c(i);
rear_pulse_cnt(i) <= rear_pulse_cnt_offset(i)+ rear_pulse_c(i);
end if;
end if;
end process p_pulse_cnt;
......@@ -759,8 +759,8 @@ cmp_pulse_cnt_blo: fastevent_counter
-- Connect pulse counter values for unused channels to all zeroes
gen_pulse_cnt_unused_chans : if (g_nr_chans < c_max_nr_chans) generate
pulse_cnt(c_max_nr_chans-1 downto g_nr_chans) <= (others => (others => '0'));
ttl_pulse_cnt(c_max_nr_chans-1 downto g_nr_chans) <= (others => (others => '0'));
blo_pulse_cnt(c_max_nr_chans-1 downto g_nr_chans) <= (others => (others => '0'));
front_pulse_cnt(c_max_nr_chans-1 downto g_nr_chans) <= (others => (others => '0'));
rear_pulse_cnt(c_max_nr_chans-1 downto g_nr_chans) <= (others => (others => '0'));
end generate gen_pulse_cnt_unused_chans;
--------------------------------------------------------------------------------
......@@ -1508,43 +1508,43 @@ end generate gen_latest_timestamp_unused_chans;
reg_cr_mpt_o => mpt,
reg_cr_mpt_wr_o => mpt_ld,
reg_ch1ttlpcr_o => ch_ttl_pcr(0),
reg_ch1ttlpcr_i => std_logic_vector(ttl_pulse_cnt(0)),
reg_ch1ttlpcr_load_o => ch_ttl_pcr_ld(0),
reg_ch2ttlpcr_o => ch_ttl_pcr(1),
reg_ch2ttlpcr_i => std_logic_vector(ttl_pulse_cnt(1)),
reg_ch2ttlpcr_load_o => ch_ttl_pcr_ld(1),
reg_ch3ttlpcr_o => ch_ttl_pcr(2),
reg_ch3ttlpcr_i => std_logic_vector(ttl_pulse_cnt(2)),
reg_ch3ttlpcr_load_o => ch_ttl_pcr_ld(2),
reg_ch4ttlpcr_o => ch_ttl_pcr(3),
reg_ch4ttlpcr_i => std_logic_vector(ttl_pulse_cnt(3)),
reg_ch4ttlpcr_load_o => ch_ttl_pcr_ld(3),
reg_ch5ttlpcr_o => ch_ttl_pcr(4),
reg_ch5ttlpcr_i => std_logic_vector(ttl_pulse_cnt(4)),
reg_ch5ttlpcr_load_o => ch_ttl_pcr_ld(4),
reg_ch6ttlpcr_o => ch_ttl_pcr(5),
reg_ch6ttlpcr_i => std_logic_vector(ttl_pulse_cnt(5)),
reg_ch6ttlpcr_load_o => ch_ttl_pcr_ld(5),
reg_ch1blopcr_o => ch_blo_pcr(0),
reg_ch1blopcr_i => std_logic_vector(blo_pulse_cnt(0)),
reg_ch1blopcr_load_o => ch_blo_pcr_ld(0),
reg_ch2blopcr_o => ch_blo_pcr(1),
reg_ch2blopcr_i => std_logic_vector(blo_pulse_cnt(1)),
reg_ch2blopcr_load_o => ch_blo_pcr_ld(1),
reg_ch3blopcr_o => ch_blo_pcr(2),
reg_ch3blopcr_i => std_logic_vector(blo_pulse_cnt(2)),
reg_ch3blopcr_load_o => ch_blo_pcr_ld(2),
reg_ch4blopcr_o => ch_blo_pcr(3),
reg_ch4blopcr_i => std_logic_vector(blo_pulse_cnt(3)),
reg_ch4blopcr_load_o => ch_blo_pcr_ld(3),
reg_ch5blopcr_o => ch_blo_pcr(4),
reg_ch5blopcr_i => std_logic_vector(blo_pulse_cnt(4)),
reg_ch5blopcr_load_o => ch_blo_pcr_ld(4),
reg_ch6blopcr_o => ch_blo_pcr(5),
reg_ch6blopcr_i => std_logic_vector(blo_pulse_cnt(5)),
reg_ch6blopcr_load_o => ch_blo_pcr_ld(5),
reg_ch1fppcr_o => ch_front_pcr(0),
reg_ch1fppcr_i => std_logic_vector(front_pulse_cnt(0)),
reg_ch1fppcr_load_o => ch_front_pcr_ld(0),
reg_ch2fppcr_o => ch_front_pcr(1),
reg_ch2fppcr_i => std_logic_vector(front_pulse_cnt(1)),
reg_ch2fppcr_load_o => ch_front_pcr_ld(1),
reg_ch3fppcr_o => ch_front_pcr(2),
reg_ch3fppcr_i => std_logic_vector(front_pulse_cnt(2)),
reg_ch3fppcr_load_o => ch_front_pcr_ld(2),
reg_ch4fppcr_o => ch_front_pcr(3),
reg_ch4fppcr_i => std_logic_vector(front_pulse_cnt(3)),
reg_ch4fppcr_load_o => ch_front_pcr_ld(3),
reg_ch5fppcr_o => ch_front_pcr(4),
reg_ch5fppcr_i => std_logic_vector(front_pulse_cnt(4)),
reg_ch5fppcr_load_o => ch_front_pcr_ld(4),
reg_ch6fppcr_o => ch_front_pcr(5),
reg_ch6fppcr_i => std_logic_vector(front_pulse_cnt(5)),
reg_ch6fppcr_load_o => ch_front_pcr_ld(5),
reg_ch1rppcr_o => ch_rear_pcr(0),
reg_ch1rppcr_i => std_logic_vector(rear_pulse_cnt(0)),
reg_ch1rppcr_load_o => ch_rear_pcr_ld(0),
reg_ch2rppcr_o => ch_rear_pcr(1),
reg_ch2rppcr_i => std_logic_vector(rear_pulse_cnt(1)),
reg_ch2rppcr_load_o => ch_rear_pcr_ld(1),
reg_ch3rppcr_o => ch_rear_pcr(2),
reg_ch3rppcr_i => std_logic_vector(rear_pulse_cnt(2)),
reg_ch3rppcr_load_o => ch_rear_pcr_ld(2),
reg_ch4rppcr_o => ch_rear_pcr(3),
reg_ch4rppcr_i => std_logic_vector(rear_pulse_cnt(3)),
reg_ch4rppcr_load_o => ch_rear_pcr_ld(3),
reg_ch5rppcr_o => ch_rear_pcr(4),
reg_ch5rppcr_i => std_logic_vector(rear_pulse_cnt(4)),
reg_ch5rppcr_load_o => ch_rear_pcr_ld(4),
reg_ch6rppcr_o => ch_rear_pcr(5),
reg_ch6rppcr_i => std_logic_vector(rear_pulse_cnt(5)),
reg_ch6rppcr_load_o => ch_rear_pcr_ld(5),
reg_tvlr_o => tvlr,
reg_tvlr_i => tm_tai(31 downto 0),
......@@ -1626,9 +1626,9 @@ end generate gen_latest_timestamp_unused_chans;
-- On-board DS18B20 Thermometer logic
--============================================================================
--------------------------------------------------------------------------------
gen_thermometer : if (g_with_thermometer = true) generate
-- The one-wire master component is used to control the on-board DS18B20
-- thermometer
gen_thermometer : if (g_with_thermometer = true) generate
--The one-wire interface component is used to read-out the on-board DS18B20
-- unique ID and temperature
cmp_onewire: gc_ds182x_interface
generic map (freq => 20)
......@@ -1642,9 +1642,9 @@ gen_thermometer : if (g_with_thermometer = true) generate
id_read_o => onewire_read_p,
id_ok_o => open
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- pps generator based on the 20 MHz clk
end generate gen_thermometer;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- pps generator based on the 20 MHz clk
cmp_pps_gen: wf_decr_counter
generic map(
g_counter_lgth => 25
......@@ -1659,7 +1659,7 @@ gen_thermometer : if (g_with_thermometer = true) generate
-- -- -- -- -- -- -- -- -- -- --
pps_load_p <= pps_is_zero; -- looping
rst_20 <= not rst_20_n;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- registering of the read values
reg_reading: process(clk_20_i)
begin
......@@ -1673,9 +1673,11 @@ gen_thermometer : if (g_with_thermometer = true) generate
end if;
end process;
--============================================================================
-- ============================================================================
-- Bicolor LED matrix logic
--============================================================================
-- ============================================================================
-- connect column, line & state signals outside
cmp_bicolor_led_ctrl : gc_bicolor_led_ctrl
generic map
......@@ -1699,9 +1701,9 @@ gen_thermometer : if (g_with_thermometer = true) generate
-- Set the system error signal for the ERR LED
led_syserr_o <= i2c_err_bit or i2c_wdto_bit or pmisse_bits_or;
--============================================================================
-- ============================================================================
-- Drive unused outputs with safe values
--============================================================================
-- ============================================================================
-- DAC outputs: enables to '1' (disable DAC comm interface) and SCK, DIN to '0'
dac20_sync_n_o <= '1';
dac20_din_o <= '0';
......@@ -1712,14 +1714,12 @@ gen_thermometer : if (g_with_thermometer = true) generate
-- SFP lines all open-drain, set to high-impedance
sfp_rate_select_o <= 'Z';
sfp_sda_b <= 'Z';
sfp_scl_i <= 'Z';
sfp_sda_b <= 'Z';
sfp_scl_i <= 'Z';
sfp_tx_disable_o <= 'Z';
end architecture arch;
--==============================================================================
-- architecture end
--==============================================================================
......@@ -419,54 +419,54 @@ package conv_common_gw_pkg is
-- Ports for PASS_THROUGH field: 'Manual Pulse Trigger' in reg: 'CR'
reg_cr_mpt_o : out std_logic_vector(7 downto 0);
reg_cr_mpt_wr_o : out std_logic;
-- Port for std_logic_vector field: 'TTL pulse counter value' in reg: 'CH1TTLPCR'
reg_ch1ttlpcr_o : out std_logic_vector(31 downto 0);
reg_ch1ttlpcr_i : in std_logic_vector(31 downto 0);
reg_ch1ttlpcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'TTL pulse counter value' in reg: 'CH2TTLPCR'
reg_ch2ttlpcr_o : out std_logic_vector(31 downto 0);
reg_ch2ttlpcr_i : in std_logic_vector(31 downto 0);
reg_ch2ttlpcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'TTL pulse counter value' in reg: 'CH3TTLPCR'
reg_ch3ttlpcr_o : out std_logic_vector(31 downto 0);
reg_ch3ttlpcr_i : in std_logic_vector(31 downto 0);
reg_ch3ttlpcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'TTL pulse counter value' in reg: 'CH4TTLPCR'
reg_ch4ttlpcr_o : out std_logic_vector(31 downto 0);
reg_ch4ttlpcr_i : in std_logic_vector(31 downto 0);
reg_ch4ttlpcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'TTL pulse counter value' in reg: 'CH5TTLPCR'
reg_ch5ttlpcr_o : out std_logic_vector(31 downto 0);
reg_ch5ttlpcr_i : in std_logic_vector(31 downto 0);
reg_ch5ttlpcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'TTL pulse counter value' in reg: 'CH6TTLPCR'
reg_ch6ttlpcr_o : out std_logic_vector(31 downto 0);
reg_ch6ttlpcr_i : in std_logic_vector(31 downto 0);
reg_ch6ttlpcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'BLO pulse counter value' in reg: 'CH1BLOPCR'
reg_ch1blopcr_o : out std_logic_vector(31 downto 0);
reg_ch1blopcr_i : in std_logic_vector(31 downto 0);
reg_ch1blopcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'BLO pulse counter value' in reg: 'CH2BLOPCR'
reg_ch2blopcr_o : out std_logic_vector(31 downto 0);
reg_ch2blopcr_i : in std_logic_vector(31 downto 0);
reg_ch2blopcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'BLO pulse counter value' in reg: 'CH3BLOPCR'
reg_ch3blopcr_o : out std_logic_vector(31 downto 0);
reg_ch3blopcr_i : in std_logic_vector(31 downto 0);
reg_ch3blopcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'BLO pulse counter value' in reg: 'CH4BLOPCR'
reg_ch4blopcr_o : out std_logic_vector(31 downto 0);
reg_ch4blopcr_i : in std_logic_vector(31 downto 0);
reg_ch4blopcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'BLO pulse counter value' in reg: 'CH5BLOPCR'
reg_ch5blopcr_o : out std_logic_vector(31 downto 0);
reg_ch5blopcr_i : in std_logic_vector(31 downto 0);
reg_ch5blopcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'BLO pulse counter value' in reg: 'CH6BLOPCR'
reg_ch6blopcr_o : out std_logic_vector(31 downto 0);
reg_ch6blopcr_i : in std_logic_vector(31 downto 0);
reg_ch6blopcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH1FPPCR'
reg_ch1fppcr_o : out std_logic_vector(31 downto 0);
reg_ch1fppcr_i : in std_logic_vector(31 downto 0);
reg_ch1fppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH2FPPCR'
reg_ch2fppcr_o : out std_logic_vector(31 downto 0);
reg_ch2fppcr_i : in std_logic_vector(31 downto 0);
reg_ch2fppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH3FPPCR'
reg_ch3fppcr_o : out std_logic_vector(31 downto 0);
reg_ch3fppcr_i : in std_logic_vector(31 downto 0);
reg_ch3fppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH4FPPCR'
reg_ch4fppcr_o : out std_logic_vector(31 downto 0);
reg_ch4fppcr_i : in std_logic_vector(31 downto 0);
reg_ch4fppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH5FPPCR'
reg_ch5fppcr_o : out std_logic_vector(31 downto 0);
reg_ch5fppcr_i : in std_logic_vector(31 downto 0);
reg_ch5fppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH6FPPCR'
reg_ch6fppcr_o : out std_logic_vector(31 downto 0);
reg_ch6fppcr_i : in std_logic_vector(31 downto 0);
reg_ch6fppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH1RPPCR'
reg_ch1rppcr_o : out std_logic_vector(31 downto 0);
reg_ch1rppcr_i : in std_logic_vector(31 downto 0);
reg_ch1rppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH2RPPCR'
reg_ch2rppcr_o : out std_logic_vector(31 downto 0);
reg_ch2rppcr_i : in std_logic_vector(31 downto 0);
reg_ch2rppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH3RPPCR'
reg_ch3rppcr_o : out std_logic_vector(31 downto 0);
reg_ch3rppcr_i : in std_logic_vector(31 downto 0);
reg_ch3rppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH4RPPCR'
reg_ch4rppcr_o : out std_logic_vector(31 downto 0);
reg_ch4rppcr_i : in std_logic_vector(31 downto 0);
reg_ch4rppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH5RPPCR'
reg_ch5rppcr_o : out std_logic_vector(31 downto 0);
reg_ch5rppcr_i : in std_logic_vector(31 downto 0);
reg_ch5rppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH6RPPCR'
reg_ch6rppcr_o : out std_logic_vector(31 downto 0);
reg_ch6rppcr_i : in std_logic_vector(31 downto 0);
reg_ch6rppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'TAI seconds counter bits 31..0' in reg: 'TVLR'
reg_tvlr_o : out std_logic_vector(31 downto 0);
reg_tvlr_i : in std_logic_vector(31 downto 0);
......
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