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conv-common-gw
Commit c2306023 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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Cleaned up code with very small modifications to reflect new memory map with… 

Cleaned up code with very small modifications to reflect new memory map with hardware revision number
parent 59dbc7a0
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Showing with 140 additions and 138 deletions
top/conv_common_gw.vhd
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top/conv_common_gw_pkg.vhd
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...@@ -60,7 +60,7 @@ package conv_common_gw_pkg is ...@@ -60,7 +60,7 @@ package conv_common_gw_pkg is
--============================================================================ --============================================================================
--Array of constants for temperature model implemented for short pulse mode --Array of constants for temperature model implemented for short pulse mode
type t_temp_decre_step is array (0 to 14) of integer; type t_temp_decre_step is array (0 to 15) of integer;
--============================================================================ --============================================================================
-- Component declarations -- Component declarations
...@@ -87,21 +87,21 @@ package conv_common_gw_pkg is ...@@ -87,21 +87,21 @@ package conv_common_gw_pkg is
g_pgen_pwidth_sh : natural range 2 to 40 := 5; g_pgen_pwidth_sh : natural range 2 to 40 := 5;
-- Duty cycle divider ratio for pulse generator -- Duty cycle divider ratio for pulse generator
-- output pulse will be limited to 1/g_pgen_duty_cycle_div -- output pulse will be limited to 1/g_pgen_duty_cycle_div
g_pgen_duty_cycle_div_cont : natural range 100 to 200 := 200; --For continuous mode operation max freq 4.12kHz g_pgen_duty_cycle_div_cont : natural range 2 to 200 := 200; --For continuous mode operation max freq 4.12kHz
g_pgen_duty_cycle_div_lg : natural range 8 to 300 := 16; --for LONG pulses changes maximum g_pgen_duty_cycle_div_lg : natural range 6 to 300 := 16; --for LONG pulses changes maximum
g_pgen_duty_cycle_div_sh : natural range 2 to 300 := 2; --for SHORT pulses changes maximum g_pgen_duty_cycle_div_sh : natural range 2 to 300 := 2; --for SHORT pulses changes maximum
-- Pulse generator glitch filter length in number of clk_20_i cycles -- Pulse generator glitch filter length in number of clk_20_i cycles
g_pgen_gf_len : integer := 4; g_pgen_gf_len : integer := 4;
-- Burst-mode-specific generics: -- Burst-mode-specific generics:
g_temp_decre_step_lg : t_temp_decre_step :=(0,0,0,0,0,0,0,5750,100,79,13,12,4,5,13); g_temp_decre_step_lg : t_temp_decre_step :=(0,0,0,0,0,0,0,0,5750,100,79,13,12,4,5,13);
g_temp_decre_step_sh : t_temp_decre_step :=(0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0); g_temp_decre_step_sh : t_temp_decre_step :=(0, 0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0);
-- Temperature rise resulting from 250ns pulse -- Temperature rise resulting from 250ns pulse
g_burstctrl_1_pulse_temp_rise_lg :in unsigned (19 downto 0) := x"23040"; -- Check every "g_eval_burst_len" pulses g_burstctrl_1_pulse_temp_rise_lg :in unsigned (19 downto 0) := x"17700"; -- Check every "g_eval_burst_len" pulses
g_burstctrl_1_pulse_temp_rise_sh :in unsigned (19 downto 0) := x"01388"; --For short 250ns pulses g_burstctrl_1_pulse_temp_rise_sh :in unsigned (19 downto 0) := x"01388"; --For short 250ns pulses
-- Maximum temperature allowed (scaled) -- Maximum temperature allowed (scaled)
g_burstctrl_max_temp_lg_sh :in unsigned (39 downto 0); g_burstctrl_max_temp_lg_sh :in unsigned (39 downto 0) := x"02540BE400";
-- Generate logic with pulse counters -- Generate logic with pulse counters
g_with_pulse_cnt : boolean := false; g_with_pulse_cnt : boolean := false;
...@@ -203,6 +203,9 @@ package conv_common_gw_pkg is ...@@ -203,6 +203,9 @@ package conv_common_gw_pkg is
sw_gp_i : in std_logic_vector(7 downto 0); sw_gp_i : in std_logic_vector(7 downto 0);
sw_other_i : in std_logic_vector(31 downto 0); sw_other_i : in std_logic_vector(31 downto 0);
-- PCB Version information
hwvers_i : in std_logic_vector (5 downto 0);
-- RTM lines -- RTM lines
rtmm_i : in std_logic_vector(2 downto 0); rtmm_i : in std_logic_vector(2 downto 0);
rtmp_i : in std_logic_vector(2 downto 0); rtmp_i : in std_logic_vector(2 downto 0);
...@@ -342,7 +345,7 @@ package conv_common_gw_pkg is ...@@ -342,7 +345,7 @@ package conv_common_gw_pkg is
-- Converter board control registers -- Converter board control registers
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
component conv_regs is component conv_regs is
port ( port (
rst_n_i : in std_logic; rst_n_i : in std_logic;
clk_sys_i : in std_logic; clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(5 downto 0); wb_adr_i : in std_logic_vector(5 downto 0);
...@@ -360,22 +363,28 @@ package conv_common_gw_pkg is ...@@ -360,22 +363,28 @@ package conv_common_gw_pkg is
reg_sr_gwvers_i : in std_logic_vector(7 downto 0); reg_sr_gwvers_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'Status of on-board general-purpose switches' in reg: 'SR' -- Port for std_logic_vector field: 'Status of on-board general-purpose switches' in reg: 'SR'
reg_sr_switches_i : in std_logic_vector(7 downto 0); reg_sr_switches_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM detection lines~\cite{rtm-det}' in reg: 'SR' -- Port for std_logic_vector field: 'RTM detection lines cite{rtm-det}' in reg: 'SR'
reg_sr_rtm_i : in std_logic_vector(5 downto 0); reg_sr_rtm_i : in std_logic_vector(5 downto 0);
-- Ports for BIT field: 'I2C communication watchdog timeout error' in reg: 'SR' -- Port for std_logic_vector field: 'Hardware version' in reg: 'SR'
reg_sr_i2c_wdto_o : out std_logic; reg_sr_hwvers_i : in std_logic_vector(5 downto 0);
reg_sr_i2c_wdto_i : in std_logic;
reg_sr_i2c_wdto_load_o : out std_logic;
-- Port for BIT field: 'White Rabbit present' in reg: 'SR' -- Port for BIT field: 'White Rabbit present' in reg: 'SR'
reg_sr_wrpres_i : in std_logic; reg_sr_wrpres_i : in std_logic;
-- Ports for BIT field: 'I2C communication error' in reg: 'SR' -- Ports for BIT field: 'I2C communication watchdog timeout error' in reg: 'ERR'
reg_sr_i2c_err_o : out std_logic; reg_err_i2c_wdto_o : out std_logic;
reg_sr_i2c_err_i : in std_logic; reg_err_i2c_wdto_i : in std_logic;
reg_sr_i2c_err_load_o : out std_logic; reg_err_i2c_wdto_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse missed error' in reg: 'SR' -- Ports for BIT field: 'I2C communication error' in reg: 'ERR'
reg_sr_pmisse_o : out std_logic_vector(5 downto 0); reg_err_i2c_err_o : out std_logic;
reg_sr_pmisse_i : in std_logic_vector(5 downto 0); reg_err_i2c_err_i : in std_logic;
reg_sr_pmisse_load_o : out std_logic; reg_err_i2c_err_load_o : out std_logic;
-- Port for std_logic_vector field: 'Frequency error' in reg: 'ERR'
reg_err_flim_pmisse_o : out std_logic_vector(5 downto 0);
reg_err_flim_pmisse_i : in std_logic_vector(5 downto 0);
reg_err_flim_pmisse_load_o : out std_logic;
-- Port for std_logic_vector field: 'Frequency watchdog error' in reg: 'ERR'
reg_err_fwdg_pmisse_o : out std_logic_vector(5 downto 0);
reg_err_fwdg_pmisse_i : in std_logic_vector(5 downto 0);
reg_err_fwdg_pmisse_load_o : out std_logic;
-- Ports for BIT field: 'Reset unlock bit' in reg: 'CR' -- Ports for BIT field: 'Reset unlock bit' in reg: 'CR'
reg_cr_rst_unlock_o : out std_logic; reg_cr_rst_unlock_o : out std_logic;
reg_cr_rst_unlock_i : in std_logic; reg_cr_rst_unlock_i : in std_logic;
...@@ -445,8 +454,7 @@ package conv_common_gw_pkg is ...@@ -445,8 +454,7 @@ package conv_common_gw_pkg is
reg_tvhr_load_o : out std_logic; reg_tvhr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Channel mask' in reg: 'TBMR' -- Port for std_logic_vector field: 'Channel mask' in reg: 'TBMR'
reg_tbmr_chan_i : in std_logic_vector(5 downto 0); reg_tbmr_chan_i : in std_logic_vector(5 downto 0);
reg_tb_rd_req_p_o : out std_logic;
-- Port for BIT field: 'White Rabbit present' in reg: 'TBMR' -- Port for BIT field: 'White Rabbit present' in reg: 'TBMR'
reg_tbmr_wrtag_i : in std_logic; reg_tbmr_wrtag_i : in std_logic;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'TBCYR' -- Port for std_logic_vector field: 'Cycles counter' in reg: 'TBCYR'
...@@ -527,8 +535,6 @@ package conv_common_gw_pkg is ...@@ -527,8 +535,6 @@ package conv_common_gw_pkg is
reg_lsr_rearfs_i : in std_logic_vector(5 downto 0); reg_lsr_rearfs_i : in std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Switch state' in reg: 'OSWR' -- Port for std_logic_vector field: 'Switch state' in reg: 'OSWR'
reg_oswr_switches_i : in std_logic_vector(31 downto 0); reg_oswr_switches_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'LS bits of 1-wire DS18B20U thermometer ID' in reg: 'UIDLR' -- Port for std_logic_vector field: 'LS bits of 1-wire DS18B20U thermometer ID' in reg: 'UIDLR'
reg_uidlr_i : in std_logic_vector(31 downto 0); reg_uidlr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'MS bits of 1-wire DS18B20U thermometer ID' in reg: 'UIDHR' -- Port for std_logic_vector field: 'MS bits of 1-wire DS18B20U thermometer ID' in reg: 'UIDHR'
...@@ -536,7 +542,7 @@ package conv_common_gw_pkg is ...@@ -536,7 +542,7 @@ package conv_common_gw_pkg is
-- Port for std_logic_vector field: 'TEMP' in reg: 'TEMPR' -- Port for std_logic_vector field: 'TEMP' in reg: 'TEMPR'
reg_tempr_i : in std_logic_vector(15 downto 0) reg_tempr_i : in std_logic_vector(15 downto 0)
); );
end component conv_regs; end component conv_regs;
-- Converter board registers SDB definition -- Converter board registers SDB definition
constant c_conv_regs_sdb : t_sdb_device := ( constant c_conv_regs_sdb : t_sdb_device := (
......
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