Commit c2306023 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag

Cleaned up code with very small modifications to reflect new memory map with…

Cleaned up code with very small modifications to reflect new memory map with hardware revision number
parent 59dbc7a0
......@@ -39,16 +39,7 @@
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2014-07-24 Theodor Stana File created
-- 2016-08-05 Denia Bouhired Moved inv ttl signals inside common gateware
-- and also added support for inv pulse LEDs
--Denia Bouhired Added support for one-wire thermometer register read out
-- 2016-12-20 Denia Bouhired Modified port list of conv_regs
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
......@@ -84,22 +75,30 @@ entity conv_common_gw is
g_pgen_pwidth_sh : natural range 2 to 40 := 5;
-- Duty cycle divider ratio for pulse generator
-- output pulse will be limited to 1/g_pgen_duty_cycle_div
g_pgen_duty_cycle_div_cont : natural range 100 to 200 := 200; --For continuous mode operation max freq 4.12kHz
g_pgen_duty_cycle_div_lg : natural range 8 to 300 := 16;--for LONG pulses changes maximum frequency to ~52k
g_pgen_duty_cycle_div_sh : natural range 2 to 300 := 2;--for SHORT pulses changes maximum frequency to ~52k
--For continuous mode operation max freq 4.16kHz
g_pgen_duty_cycle_div_cont : natural range 2 to 200 := 200;
--for LONG pulses changes maximum frequency to ~104kHz
g_pgen_duty_cycle_div_lg : natural range 6 to 300 := 8;
--for SHORT pulses changes maximum frequency to ~2MHz
g_pgen_duty_cycle_div_sh : natural range 2 to 300 := 2;
-- Pulse generator glitch filter length in number of clk_20_i cycles
g_pgen_gf_len : integer := 4;
-- Burst-mode-specific generics:
g_temp_decre_step_lg : t_temp_decre_step :=(0,0,0,0,0,0,0,5750,100,79,13,12,4,5,13);
g_temp_decre_step_sh : t_temp_decre_step :=(0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0);
g_temp_decre_step_lg : t_temp_decre_step :=
(0,0,0,0,0,0,0,0,5750,100,79,13,12,4,5,13);
g_temp_decre_step_sh : t_temp_decre_step :=
(0,0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0);
-- Single pulse temperature rise
g_burstctrl_1_pulse_temp_rise_lg :in unsigned (19 downto 0) := x"23040"; --For long 1.2us pulses
g_burstctrl_1_pulse_temp_rise_sh :in unsigned (19 downto 0) := x"01388"; --For short 250ns pulses
-- For long 1.2us pulses
g_burstctrl_1_pulse_temp_rise_lg :in unsigned (19 downto 0) := x"17700";
-- For short 250ns pulses
g_burstctrl_1_pulse_temp_rise_sh :in unsigned (19 downto 0) := x"01388";
-- Maximum temperature allowed (scaled)
g_burstctrl_max_temp_lg_sh :in unsigned (39 downto 0) :=x"02540BE400"; --For both long 1.2us pulses and short 250ns
g_burstctrl_max_temp_lg_sh :in unsigned (39 downto 0)
:=x"02540BE400"; --For both long 1.2us pulses and short 250ns
-- Generate logic with pulse counters
g_with_pulse_cnt : boolean := false;
......@@ -203,7 +202,9 @@ entity conv_common_gw is
-- Switch inputs (for readout from converter status register)
sw_gp_i : in std_logic_vector(7 downto 0);
sw_other_i : in std_logic_vector(31 downto 0);
-- PCB Version information
hwvers_i : in std_logic_vector (5 downto 0);
-- RTM lines
rtmm_i : in std_logic_vector(2 downto 0);
rtmp_i : in std_logic_vector(2 downto 0);
......@@ -321,13 +322,13 @@ architecture arch of conv_common_gw is
signal trig_pgen : std_logic_vector(g_nr_chans-1 downto 0);
signal burst_en_n : std_logic;
signal pulse_outp_cont : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_sh_burst : std_logic_vector(g_nr_chans-1 downto 0);
signal burst_outp_sh : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_r_edge_lg_p : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_f_edge_lg_p : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_r_edge_sh_p : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_f_edge_sh_p : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_sh : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_lg_burst : std_logic_vector(g_nr_chans-1 downto 0);
signal burst_outp_lg : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_lg : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp : std_logic_vector(g_nr_chans-1 downto 0);
......@@ -337,11 +338,13 @@ architecture arch of conv_common_gw is
signal inv_pulse_outp_d0 : std_logic_vector(g_nr_inv_chans-1 downto 0);
signal inv_pulse_outp_fedge_p : std_logic_vector(g_nr_inv_chans-1 downto 0);
signal pmisse_p : std_logic_vector(g_nr_chans-1 downto 0);
signal flim_pmisse_p : std_logic_vector(g_nr_chans-1 downto 0);
signal fwdg_pmisse_p : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_err_cont : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_err_lg : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_err_sh : std_logic_vector(g_nr_chans-1 downto 0);
signal burst_outp_err_lg : std_logic_vector(g_nr_chans-1 downto 0);
signal burst_outp_err_sh : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_err_lg_p : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_err_sh_p : std_logic_vector(g_nr_chans-1 downto 0);
signal burst_outp_err_lg_p : std_logic_vector(g_nr_chans-1 downto 0);
signal burst_outp_err_sh_p : std_logic_vector(g_nr_chans-1 downto 0);
-- Output enable signals
signal global_oen : std_logic;
......@@ -368,8 +371,12 @@ architecture arch of conv_common_gw is
signal i2c_wdto_bit_rst : std_logic;
signal i2c_wdto_bit_rst_ld : std_logic;
signal pmisse_bit : std_logic_vector(c_max_nr_chans-1 downto 0);
signal pmisse_bit_rst : std_logic_vector(c_max_nr_chans-1 downto 0);
signal pmisse_bit_rst_ld : std_logic;
signal flim_pmisse_bit : std_logic_vector(c_max_nr_chans-1 downto 0);
signal flim_pmisse_bit_rst : std_logic_vector(c_max_nr_chans-1 downto 0);
signal flim_pmisse_bit_rst_ld : std_logic;
signal fwdg_pmisse_bit : std_logic_vector(c_max_nr_chans-1 downto 0);
signal fwdg_pmisse_bit_rst : std_logic_vector(c_max_nr_chans-1 downto 0);
signal fwdg_pmisse_bit_rst_ld : std_logic;
signal pmisse_bits_or : std_logic;
signal pulse_cnt : t_pulse_cnt;
signal ttl_pulse_cnt : t_pulse_cnt;
......@@ -453,6 +460,8 @@ architecture arch of conv_common_gw is
signal id : std_logic_vector(63 downto 0);
signal temper : std_logic_vector(15 downto 0);
--==============================================================================
-- architecture begin
--==============================================================================
......@@ -484,7 +493,7 @@ begin
generic map
(
-- Reset time: 50ns * 2 * (10**6) = 100 ms
g_reset_time => 2*(10**4)
g_reset_time => 2*(10**6)
)
port map
(
......@@ -679,8 +688,6 @@ end generate gen_pulse_cnt;
-- The trigger to the pulse generator is either manual OR from the channel input
trig_pgen(i) <= trig_chan(i) or trig_man(i);
-------------------------------------------------------------------------------------------------
-- Instantiate pulse generator + burst controller block for the channel for LONG pulse operation
-------------------------------------------------------------------------------------------------
......@@ -735,7 +742,7 @@ end generate gen_pulse_cnt;
trig_a_i => trig_pgen(i),
pulse_err_p_o => pulse_outp_err_lg (i),
pulse_err_p_o => pulse_outp_err_lg_p (i),
pulse_o => pulse_outp_lg(i),
pulse_r_edge_p_o => pulse_r_edge_lg_p(i),
......@@ -759,8 +766,8 @@ end generate gen_pulse_cnt;
pulse_burst_i => pulse_outp_lg(i),
pulse_r_edge_p_i => pulse_r_edge_lg_p(i),
pulse_f_edge_p_i => pulse_f_edge_lg_p(i),
pulse_burst_o => pulse_outp_lg_burst(i),
burst_err_p_o => burst_outp_err_lg (i)
pulse_burst_o => burst_outp_lg(i),
burst_err_p_o => burst_outp_err_lg_p(i)
);
......@@ -770,7 +777,7 @@ end generate gen_pulse_cnt;
-- BURST MODE WITH SHORT PULSES
----------------------------------
--Instantiate pulse generator block for minimum pulse width and minimum allowed duty cycle
cmp_pulse_gen_sh : conv_pulse_gen
cmp_pulse_gen_sh : conv_pulse_gen
generic map
(
g_with_fixed_pwidth => g_pgen_fixed_width,
......@@ -788,7 +795,7 @@ end generate gen_pulse_cnt;
trig_a_i => trig_pgen(i),
pulse_err_p_o => pulse_outp_err_sh (i),
pulse_err_p_o => pulse_outp_err_sh_p (i),
pulse_o => pulse_outp_sh(i),
pulse_r_edge_p_o => pulse_r_edge_sh_p(i) ,
......@@ -813,35 +820,37 @@ end generate gen_pulse_cnt;
pulse_burst_i => pulse_outp_sh(i),
pulse_r_edge_p_i => pulse_r_edge_sh_p(i),
pulse_f_edge_p_i => pulse_f_edge_sh_p(i),
pulse_burst_o => pulse_outp_sh_burst(i),
burst_err_p_o => burst_outp_err_sh (i)
pulse_burst_o => burst_outp_sh(i),
burst_err_p_o => burst_outp_err_sh_p(i)
);
-----------------------------------------------------------------------------------
----------------------------------------------------------------------
--Select output depending on mode of operation.
-----------------------------------------------------------------------------------
-- p_output_sel : process (burst_en_n, pulse_width_sel_n_i)
-- begin
-- if burst_en_n = '1' then
-- pulse_outp(i) <= pulse_outp_cont(i);
-- pmisse_p(i) <= pulse_outp_err_cont(i);
-- else
-- if pulse_width_sel_n_i='1' then
-- pulse_outp(i) <= pulse_outp_lg_burst(i);
-- pmisse_p(i) <= pulse_outp_err_lg(i) or burst_outp_err_lg(i);
-- else
-- pulse_outp(i) <= pulse_outp_sh_burst(i);
-- pmisse_p(i) <= pulse_outp_err_sh(i) or burst_outp_err_sh(i);
-- end if;
-- end if;
-- end process p_output_sel;
----------------------------------------------------------------------
pulse_outp (i) <= (burst_outp_lg(i) and pulse_width_sel_n_i) or
(burst_outp_sh(i) and not pulse_width_sel_n_i)
when burst_en_n = '0'
else pulse_outp_cont(i);
----------------------------------------------------------------------
--Generate error pulses depending on mode of operation
----------------------------------------------------------------------
-- flim_pmisse_p gives out a pulse when a pulse is missed because its
-- frequency is above the set maximum frequency
flim_pmisse_p (i) <= (pulse_outp_err_lg_p(i) and pulse_width_sel_n_i) or
(pulse_outp_err_sh_p(i) and not pulse_width_sel_n_i)
when burst_en_n = '0'
else pulse_outp_err_cont(i) ;
pulse_outp(i) <= (pulse_outp_lg_burst(i) and pulse_width_sel_n_i) or
(pulse_outp_sh_burst(i) and not pulse_width_sel_n_i)
-- fwdg_pmisse_p gives out a pulse when a pulse is cutoff because the
-- frequency watchdog only supports a high frequency for a limited period
fwdg_pmisse_p (i) <= (burst_outp_err_lg_p(i) and pulse_width_sel_n_i) or
(burst_outp_err_sh_p(i) and not pulse_width_sel_n_i)
when burst_en_n = '0'
else pulse_outp_cont(i) ;
-----------------------------------------------------------------------------------
else '0' ;
pmisse_p (i) <= flim_pmisse_p (i) or fwdg_pmisse_p (i);
-----------------------------------------------------------------------
-- Process to flash pulse LED when a pulse is output
-- LED flash length: 26 ms
p_pulse_led : process (clk_20_i) is
......@@ -1217,23 +1226,37 @@ end generate gen_line_unused_chans;
end if;
end process p_rst_fr_reg;
-- Register for the PMISSE bits in the SR, set when a channel misses a pulse
-- Register for the PMISSE bits in the ERR, set when a channel misses a pulse
-- Each bit is cleared by writing a '1' to it
p_sr_pmisse_bit : process (clk_20_i)
p_err_pmisse_bit : process (clk_20_i)
begin
if rising_edge(clk_20_i) then
for i in 0 to g_nr_chans-1 loop
if (rst_20_n = '0') then
pmisse_bit(i) <= '0';
flim_pmisse_bit(i) <= '0';
fwdg_pmisse_bit (i)<= '0';
pmisse_bit(i) <= '0';
elsif (pmisse_p(i) = '1') then
pmisse_bit(i) <= '1';
elsif (pmisse_bit_rst_ld = '1') and (pmisse_bit_rst(i) = '1') then
pmisse_bit(i) <= '0';
if flim_pmisse_p (i) = '1' then
flim_pmisse_bit(i)<= '1';
end if;
if fwdg_pmisse_p (i) = '1' then
fwdg_pmisse_bit(i) <= '1';
end if;
else
if (flim_pmisse_bit_rst_ld = '1') and (flim_pmisse_bit_rst(i) = '1') then
flim_pmisse_bit(i) <= '0';
end if;
if (fwdg_pmisse_bit_rst_ld = '1') and (fwdg_pmisse_bit_rst(i) = '1') then
fwdg_pmisse_bit(i) <= '0';
end if;
end if;
pmisse_bit(i) <= flim_pmisse_bit(i) or fwdg_pmisse_bit(i);
end loop;
end if;
end process p_sr_pmisse_bit;
end process p_err_pmisse_bit;
-- Create an OR of all PMISSE bits
pmisse_bits_or <= '0' when (pmisse_bit = (pmisse_bit'range => '0')) else
'1';
......@@ -1372,16 +1395,21 @@ end generate gen_latest_timestamp_unused_chans;
reg_sr_gwvers_i => g_gwvers,
reg_sr_switches_i => sw_gp_i,
reg_sr_rtm_i => rtm_lines,
reg_sr_i2c_wdto_o => i2c_wdto_bit_rst,
reg_sr_i2c_wdto_i => i2c_wdto_bit,
reg_sr_i2c_wdto_load_o => i2c_wdto_bit_rst_ld,
reg_sr_wrpres_i => wrpres,
reg_sr_i2c_err_o => i2c_err_bit_rst,
reg_sr_i2c_err_i => i2c_err_bit,
reg_sr_i2c_err_load_o => i2c_err_bit_rst_ld,
reg_sr_pmisse_o => pmisse_bit_rst,
reg_sr_pmisse_i => pmisse_bit,
reg_sr_pmisse_load_o => pmisse_bit_rst_ld,
reg_sr_hwvers_i => hwvers_i,
reg_sr_wrpres_i => wrpres,
reg_err_i2c_wdto_o => i2c_wdto_bit_rst,
reg_err_i2c_wdto_i => i2c_wdto_bit,
reg_err_i2c_wdto_load_o => i2c_wdto_bit_rst_ld,
reg_err_i2c_err_o => i2c_err_bit_rst,
reg_err_i2c_err_i => i2c_err_bit,
reg_err_i2c_err_load_o => i2c_err_bit_rst_ld,
reg_err_flim_pmisse_o => flim_pmisse_bit_rst,
reg_err_flim_pmisse_i => flim_pmisse_bit,
reg_err_flim_pmisse_load_o => flim_pmisse_bit_rst_ld,
reg_err_fwdg_pmisse_o => fwdg_pmisse_bit_rst,
reg_err_fwdg_pmisse_i => fwdg_pmisse_bit,
reg_err_fwdg_pmisse_load_o => fwdg_pmisse_bit_rst_ld,
reg_cr_rst_unlock_o => rst_unlock_bit,
reg_cr_rst_unlock_i => rst_unlock,
......@@ -1439,7 +1467,7 @@ end generate gen_latest_timestamp_unused_chans;
reg_tbmr_chan_i => buf_dat_out( 5 downto 0),
reg_tbmr_wrtag_i => buf_dat_out( 6),
--reg_tb_rd_req_p_o => buf_rd_req_p,
reg_tb_rd_req_p_o => buf_rd_req_p,
reg_tbcyr_i => buf_dat_out(34 downto 7),
reg_tbtlr_i => buf_dat_out(66 downto 35),
reg_tbthr_i => buf_dat_out(74 downto 67),
......@@ -1556,41 +1584,6 @@ end generate gen_latest_timestamp_unused_chans;
end if;
end process;
-- cmp_onewire_master : wb_onewire_master
-- generic map
-- (
-- g_interface_mode => CLASSIC,
-- g_address_granularity => WORD,
-- g_num_ports => 1,
-- g_ow_btp_normal => "5.0",
-- g_ow_btp_overdrive => "1.0"
-- )
-- port map
-- (
-- clk_sys_i => clk_20_i,
-- rst_n_i => rst_20_n,
-- wb_cyc_i => xbar_master_out(c_slv_onewire_mst).cyc,
-- wb_sel_i => xbar_master_out(c_slv_onewire_mst).sel,
-- wb_stb_i => xbar_master_out(c_slv_onewire_mst).stb,
-- wb_we_i => xbar_master_out(c_slv_onewire_mst).we,
-- wb_adr_i => xbar_master_out(c_slv_onewire_mst).adr(4 downto 2),
-- wb_dat_i => xbar_master_out(c_slv_onewire_mst).dat,
-- wb_dat_o => xbar_master_in(c_slv_onewire_mst).dat,
-- wb_ack_o => xbar_master_in(c_slv_onewire_mst).ack,
-- wb_int_o => open,
-- wb_stall_o => xbar_master_in(c_slv_onewire_mst).stall,
-- owr_pwren_o => open,
-- owr_en_o => owr_en,
-- owr_i => owr_in
-- );
--Generate tri-state buffer for thermometer
-- thermometer_b <= '0' when (owr_en(0) = '1') else
-- 'Z';
-- owr_in(0) <= thermometer_b;
--============================================================================
-- Bicolor LED matrix logic
......@@ -1635,6 +1628,9 @@ end generate gen_latest_timestamp_unused_chans;
sfp_mod_def2_b <= 'Z';
sfp_tx_disable_o <= 'Z';
end architecture arch;
--==============================================================================
-- architecture end
......
......@@ -60,7 +60,7 @@ package conv_common_gw_pkg is
--============================================================================
--Array of constants for temperature model implemented for short pulse mode
type t_temp_decre_step is array (0 to 14) of integer;
type t_temp_decre_step is array (0 to 15) of integer;
--============================================================================
-- Component declarations
......@@ -87,21 +87,21 @@ package conv_common_gw_pkg is
g_pgen_pwidth_sh : natural range 2 to 40 := 5;
-- Duty cycle divider ratio for pulse generator
-- output pulse will be limited to 1/g_pgen_duty_cycle_div
g_pgen_duty_cycle_div_cont : natural range 100 to 200 := 200; --For continuous mode operation max freq 4.12kHz
g_pgen_duty_cycle_div_lg : natural range 8 to 300 := 16; --for LONG pulses changes maximum
g_pgen_duty_cycle_div_cont : natural range 2 to 200 := 200; --For continuous mode operation max freq 4.12kHz
g_pgen_duty_cycle_div_lg : natural range 6 to 300 := 16; --for LONG pulses changes maximum
g_pgen_duty_cycle_div_sh : natural range 2 to 300 := 2; --for SHORT pulses changes maximum
-- Pulse generator glitch filter length in number of clk_20_i cycles
g_pgen_gf_len : integer := 4;
-- Burst-mode-specific generics:
g_temp_decre_step_lg : t_temp_decre_step :=(0,0,0,0,0,0,0,5750,100,79,13,12,4,5,13);
g_temp_decre_step_sh : t_temp_decre_step :=(0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0);
g_temp_decre_step_lg : t_temp_decre_step :=(0,0,0,0,0,0,0,0,5750,100,79,13,12,4,5,13);
g_temp_decre_step_sh : t_temp_decre_step :=(0, 0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0);
-- Temperature rise resulting from 250ns pulse
g_burstctrl_1_pulse_temp_rise_lg :in unsigned (19 downto 0) := x"23040"; -- Check every "g_eval_burst_len" pulses
g_burstctrl_1_pulse_temp_rise_lg :in unsigned (19 downto 0) := x"17700"; -- Check every "g_eval_burst_len" pulses
g_burstctrl_1_pulse_temp_rise_sh :in unsigned (19 downto 0) := x"01388"; --For short 250ns pulses
-- Maximum temperature allowed (scaled)
g_burstctrl_max_temp_lg_sh :in unsigned (39 downto 0);
g_burstctrl_max_temp_lg_sh :in unsigned (39 downto 0) := x"02540BE400";
-- Generate logic with pulse counters
g_with_pulse_cnt : boolean := false;
......@@ -203,6 +203,9 @@ package conv_common_gw_pkg is
sw_gp_i : in std_logic_vector(7 downto 0);
sw_other_i : in std_logic_vector(31 downto 0);
-- PCB Version information
hwvers_i : in std_logic_vector (5 downto 0);
-- RTM lines
rtmm_i : in std_logic_vector(2 downto 0);
rtmp_i : in std_logic_vector(2 downto 0);
......@@ -342,7 +345,7 @@ package conv_common_gw_pkg is
-- Converter board control registers
------------------------------------------------------------------------------
component conv_regs is
port (
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(5 downto 0);
......@@ -360,22 +363,28 @@ package conv_common_gw_pkg is
reg_sr_gwvers_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'Status of on-board general-purpose switches' in reg: 'SR'
reg_sr_switches_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM detection lines~\cite{rtm-det}' in reg: 'SR'
-- Port for std_logic_vector field: 'RTM detection lines cite{rtm-det}' in reg: 'SR'
reg_sr_rtm_i : in std_logic_vector(5 downto 0);
-- Ports for BIT field: 'I2C communication watchdog timeout error' in reg: 'SR'
reg_sr_i2c_wdto_o : out std_logic;
reg_sr_i2c_wdto_i : in std_logic;
reg_sr_i2c_wdto_load_o : out std_logic;
-- Port for std_logic_vector field: 'Hardware version' in reg: 'SR'
reg_sr_hwvers_i : in std_logic_vector(5 downto 0);
-- Port for BIT field: 'White Rabbit present' in reg: 'SR'
reg_sr_wrpres_i : in std_logic;
-- Ports for BIT field: 'I2C communication error' in reg: 'SR'
reg_sr_i2c_err_o : out std_logic;
reg_sr_i2c_err_i : in std_logic;
reg_sr_i2c_err_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse missed error' in reg: 'SR'
reg_sr_pmisse_o : out std_logic_vector(5 downto 0);
reg_sr_pmisse_i : in std_logic_vector(5 downto 0);
reg_sr_pmisse_load_o : out std_logic;
-- Ports for BIT field: 'I2C communication watchdog timeout error' in reg: 'ERR'
reg_err_i2c_wdto_o : out std_logic;
reg_err_i2c_wdto_i : in std_logic;
reg_err_i2c_wdto_load_o : out std_logic;
-- Ports for BIT field: 'I2C communication error' in reg: 'ERR'
reg_err_i2c_err_o : out std_logic;
reg_err_i2c_err_i : in std_logic;
reg_err_i2c_err_load_o : out std_logic;
-- Port for std_logic_vector field: 'Frequency error' in reg: 'ERR'
reg_err_flim_pmisse_o : out std_logic_vector(5 downto 0);
reg_err_flim_pmisse_i : in std_logic_vector(5 downto 0);
reg_err_flim_pmisse_load_o : out std_logic;
-- Port for std_logic_vector field: 'Frequency watchdog error' in reg: 'ERR'
reg_err_fwdg_pmisse_o : out std_logic_vector(5 downto 0);
reg_err_fwdg_pmisse_i : in std_logic_vector(5 downto 0);
reg_err_fwdg_pmisse_load_o : out std_logic;
-- Ports for BIT field: 'Reset unlock bit' in reg: 'CR'
reg_cr_rst_unlock_o : out std_logic;
reg_cr_rst_unlock_i : in std_logic;
......@@ -445,8 +454,7 @@ package conv_common_gw_pkg is
reg_tvhr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Channel mask' in reg: 'TBMR'
reg_tbmr_chan_i : in std_logic_vector(5 downto 0);
reg_tb_rd_req_p_o : out std_logic;
-- Port for BIT field: 'White Rabbit present' in reg: 'TBMR'
reg_tbmr_wrtag_i : in std_logic;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'TBCYR'
......@@ -527,8 +535,6 @@ package conv_common_gw_pkg is
reg_lsr_rearfs_i : in std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Switch state' in reg: 'OSWR'
reg_oswr_switches_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'LS bits of 1-wire DS18B20U thermometer ID' in reg: 'UIDLR'
reg_uidlr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'MS bits of 1-wire DS18B20U thermometer ID' in reg: 'UIDHR'
......@@ -536,7 +542,7 @@ package conv_common_gw_pkg is
-- Port for std_logic_vector field: 'TEMP' in reg: 'TEMPR'
reg_tempr_i : in std_logic_vector(15 downto 0)
);
end component conv_regs;
end component conv_regs;
-- Converter board registers SDB definition
constant c_conv_regs_sdb : t_sdb_device := (
......
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