Commit c1d3f39b authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

Add time-tag logic with latest time-tag in dedicated registers

parent 02b0e7c2
......@@ -58,7 +58,7 @@ entity conv_pulse_timetag is
rst_n_i : in std_logic;
-- Asynchronous pulse input
pulse_a_i : in std_logic_vector(g_nr_chan downto 1);
pulse_a_i : in std_logic_vector(g_nr_chan-1 downto 0);
-- Time inputs from White Rabbit
wr_tm_cycles_i : in std_logic_vector(27 downto 0);
......@@ -75,7 +75,7 @@ entity conv_pulse_timetag is
tm_cycles_o : out std_logic_vector(27 downto 0);
tm_tai_o : out std_logic_vector(39 downto 0);
tm_wrpres_o : out std_logic;
chan_o : out std_logic_vector(g_nr_chan downto 1);
chan_p_o : out std_logic_vector(g_nr_chan-1 downto 0);
-- Ring buffer I/O
buf_wr_req_p_o : out std_logic
......@@ -95,8 +95,8 @@ architecture behav of conv_pulse_timetag is
signal tai_l_ld : std_logic;
signal tai_h_ld : std_logic;
signal pulse_redge_p : std_logic_vector(g_nr_chan downto 1);
signal pulse_redge_p_d0 : std_logic_vector(g_nr_chan downto 1);
signal pulse_redge_p : std_logic_vector(g_nr_chan-1 downto 0);
signal pulse_redge_p_d0 : std_logic_vector(g_nr_chan-1 downto 0);
--==============================================================================
-- architecture begin
......@@ -169,7 +169,7 @@ begin
-- Control logic for the FIFO
--============================================================================
-- First, synchronize the pulse inputs in the clk_i domain
gen_sync_chains : for i in 1 to g_nr_chan generate
gen_sync_chains : for i in 0 to g_nr_chan-1 generate
cmp_pulse_sync : gc_sync_ffs
generic map
(
......@@ -222,7 +222,7 @@ begin
tm_tai_o <= wr_tm_tai_i when wr_tm_valid_i = '1' else
std_logic_vector(tai_cnt);
tm_wrpres_o <= wr_tm_valid_i;
chan_o <= pulse_redge_p_d0;
chan_p_o <= pulse_redge_p_d0;
end architecture behav;
--==============================================================================
......
This diff is collapsed.
......@@ -425,8 +425,8 @@ peripheral {
description = "Value of the 8-ns cycles counter when time tag was taken.";
type = SLV;
size = 28;
access_bus = WRITE_ONLY;
access_dev = READ_ONLY;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
......@@ -478,8 +478,8 @@ peripheral {
description = "Value of the 8-ns cycles counter when time tag was taken.";
type = SLV;
size = 28;
access_bus = WRITE_ONLY;
access_dev = READ_ONLY;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
......@@ -531,8 +531,8 @@ peripheral {
description = "Value of the 8-ns cycles counter when time tag was taken.";
type = SLV;
size = 28;
access_bus = WRITE_ONLY;
access_dev = READ_ONLY;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
......@@ -585,8 +585,8 @@ peripheral {
prefix = "tai";
type = SLV;
size = 28;
access_bus = WRITE_ONLY;
access_dev = READ_ONLY;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
......@@ -638,8 +638,8 @@ peripheral {
description = "Value of the 8-ns cycles counter when time tag was taken.";
type = SLV;
size = 28;
access_bus = WRITE_ONLY;
access_dev = READ_ONLY;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
......@@ -691,8 +691,8 @@ peripheral {
description = "Value of the 8-ns cycles counter when time tag was taken.";
type = SLV;
size = 28;
access_bus = WRITE_ONLY;
access_dev = READ_ONLY;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
......
This diff is collapsed.
......@@ -342,52 +342,64 @@ package conv_common_gw_pkg is
reg_tbcsr_clr_o : out std_logic;
reg_tbcsr_clr_i : in std_logic;
reg_tbcsr_clr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH1LTSCYR'
reg_ch1ltscyr_i : in std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH1LTSTLR'
reg_ch1ltstlr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH1LTSTHR'
reg_ch1ltsthr_tai_i : in std_logic_vector(7 downto 0);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH1LTSTHR'
reg_ch1ltsthr_wrtag_i : in std_logic;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH2LTSCYR'
reg_ch2ltscyr_i : in std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH2LTSTLR'
reg_ch2ltstlr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH2LTSTHR'
reg_ch2ltsthr_tai_i : in std_logic_vector(7 downto 0);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH2LTSTHR'
reg_ch2ltsthr_wrtag_i : in std_logic;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH3LTSCYR'
reg_ch3ltscyr_i : in std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH3LTSTLR'
reg_ch3ltstlr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH3LTSTHR'
reg_ch3ltsthr_tai_i : in std_logic_vector(7 downto 0);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH3LTSTHR'
reg_ch3ltsthr_wrtag_i : in std_logic;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH4LTSCYR'
reg_ch4ltscyr_i : in std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH4LTSTLR'
reg_ch4ltstlr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH4LTSTHR'
reg_ch4ltsthr_tai_i : in std_logic_vector(7 downto 0);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH4LTSTHR'
reg_ch4ltsthr_wrtag_i : in std_logic;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH5LTSCYR'
reg_ch5ltscyr_i : in std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH5LTSTLR'
reg_ch5ltstlr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH5LTSTHR'
reg_ch5ltsthr_tai_i : in std_logic_vector(7 downto 0);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH5LTSTHR'
reg_ch5ltsthr_wrtag_i : in std_logic;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH6LTSCYR'
reg_ch6ltscyr_i : in std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH6LTSTLR'
reg_ch6ltstlr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH6LTSTHR'
reg_ch6ltsthr_tai_i : in std_logic_vector(7 downto 0);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH6LTSTHR'
reg_ch6ltsthr_wrtag_i : in std_logic;
-- Port for std_logic_vector field: 'Front panel TTL input state' in reg: 'LSR'
reg_lsr_front_ttl_i : in std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Front panel TTL-BAR input state' in reg: 'LSR'
reg_lsr_front_invttl_i : in std_logic_vector(3 downto 0);
-- Port for std_logic_vector field: 'Front panel channel input state' in reg: 'LSR'
reg_lsr_front_i : in std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Front panel INV-TTL input state' in reg: 'LSR'
reg_lsr_frontinv_i : in std_logic_vector(3 downto 0);
-- Port for std_logic_vector field: 'Rear panel input state' in reg: 'LSR'
reg_lsr_rear_i : in std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Input failsafe state' in reg: 'LSR'
reg_lsr_fs_i : in std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'State of MultiCast switches' in reg: 'MSWR'
reg_mswr_bit_i : in std_logic_vector(3 downto 0)
reg_lsr_rearfs_i : in std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Multicast address (from switch)' in reg: 'MSWR'
reg_mswr_switches_i : in std_logic_vector(3 downto 0)
);
end component conv_regs;
......@@ -427,7 +439,7 @@ package conv_common_gw_pkg is
rst_n_i : in std_logic;
-- Asynchronous pulse input
pulse_a_i : in std_logic_vector(g_nr_chan downto 1);
pulse_a_i : in std_logic_vector(g_nr_chan-1 downto 0);
-- Time inputs from White Rabbit
wr_tm_cycles_i : in std_logic_vector(27 downto 0);
......@@ -444,7 +456,7 @@ package conv_common_gw_pkg is
tm_cycles_o : out std_logic_vector(27 downto 0);
tm_tai_o : out std_logic_vector(39 downto 0);
tm_wrpres_o : out std_logic;
chan_o : out std_logic_vector(g_nr_chan downto 1);
chan_p_o : out std_logic_vector(g_nr_chan-1 downto 0);
-- Ring buffer I/O
buf_wr_req_p_o : out std_logic
......
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