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level-conversion
conv-common-gw
Commits
c1d3f39b
Commit
c1d3f39b
authored
Aug 18, 2014
by
Theodor-Adrian Stana
Browse files
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Browse Files
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Plain Diff
Add time-tag logic with latest time-tag in dedicated registers
parent
02b0e7c2
Hide whitespace changes
Inline
Side-by-side
Showing
5 changed files
with
232 additions
and
315 deletions
+232
-315
conv_pulse_timetag.vhd
modules/conv_pulse_timetag.vhd
+6
-6
conv_regs.vhd
modules/conv_regs.vhd
+44
-188
conv_regs.wb
modules/conv_regs.wb
+12
-12
conv_common_gw.vhd
top/conv_common_gw.vhd
+148
-99
conv_common_gw_pkg.vhd
top/conv_common_gw_pkg.vhd
+22
-10
No files found.
modules/conv_pulse_timetag.vhd
View file @
c1d3f39b
...
...
@@ -58,7 +58,7 @@ entity conv_pulse_timetag is
rst_n_i
:
in
std_logic
;
-- Asynchronous pulse input
pulse_a_i
:
in
std_logic_vector
(
g_nr_chan
downto
1
);
pulse_a_i
:
in
std_logic_vector
(
g_nr_chan
-1
downto
0
);
-- Time inputs from White Rabbit
wr_tm_cycles_i
:
in
std_logic_vector
(
27
downto
0
);
...
...
@@ -75,7 +75,7 @@ entity conv_pulse_timetag is
tm_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
tm_tai_o
:
out
std_logic_vector
(
39
downto
0
);
tm_wrpres_o
:
out
std_logic
;
chan_
o
:
out
std_logic_vector
(
g_nr_chan
downto
1
);
chan_
p_o
:
out
std_logic_vector
(
g_nr_chan
-1
downto
0
);
-- Ring buffer I/O
buf_wr_req_p_o
:
out
std_logic
...
...
@@ -95,8 +95,8 @@ architecture behav of conv_pulse_timetag is
signal
tai_l_ld
:
std_logic
;
signal
tai_h_ld
:
std_logic
;
signal
pulse_redge_p
:
std_logic_vector
(
g_nr_chan
downto
1
);
signal
pulse_redge_p_d0
:
std_logic_vector
(
g_nr_chan
downto
1
);
signal
pulse_redge_p
:
std_logic_vector
(
g_nr_chan
-1
downto
0
);
signal
pulse_redge_p_d0
:
std_logic_vector
(
g_nr_chan
-1
downto
0
);
--==============================================================================
-- architecture begin
...
...
@@ -169,7 +169,7 @@ begin
-- Control logic for the FIFO
--============================================================================
-- First, synchronize the pulse inputs in the clk_i domain
gen_sync_chains
:
for
i
in
1
to
g_nr_chan
generate
gen_sync_chains
:
for
i
in
0
to
g_nr_chan
-1
generate
cmp_pulse_sync
:
gc_sync_ffs
generic
map
(
...
...
@@ -222,7 +222,7 @@ begin
tm_tai_o
<=
wr_tm_tai_i
when
wr_tm_valid_i
=
'1'
else
std_logic_vector
(
tai_cnt
);
tm_wrpres_o
<=
wr_tm_valid_i
;
chan_
o
<=
pulse_redge_p_d0
;
chan_
p_o
<=
pulse_redge_p_d0
;
end
architecture
behav
;
--==============================================================================
...
...
modules/conv_regs.vhd
View file @
c1d3f39b
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : conv_regs.vhd
-- Author : auto-generated by wbgen2 from conv_regs.wb
-- Created :
Thu Jul 31 15:16:45
2014
-- Created :
Mon Aug 18 15:56:43
2014
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb
...
...
@@ -31,7 +31,7 @@ entity conv_regs is
reg_bidr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Gateware version' in reg: 'SR'
reg_sr_gwvers_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for std_logic_vector field: 'Status of on-board switches' in reg: 'SR'
-- Port for std_logic_vector field: 'Status of on-board
general-purpose
switches' in reg: 'SR'
reg_sr_switches_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for std_logic_vector field: 'RTM detection lines~\cite{rtm-det}' in reg: 'SR'
reg_sr_rtm_i
:
in
std_logic_vector
(
5
downto
0
);
...
...
@@ -45,7 +45,7 @@ entity conv_regs is
reg_sr_i2c_err_o
:
out
std_logic
;
reg_sr_i2c_err_i
:
in
std_logic
;
reg_sr_i2c_err_load_o
:
out
std_logic
;
-- Port
s for BIT
field: 'Pulse missed error' in reg: 'SR'
-- Port
for std_logic_vector
field: 'Pulse missed error' in reg: 'SR'
reg_sr_pmisse_o
:
out
std_logic_vector
(
5
downto
0
);
reg_sr_pmisse_i
:
in
std_logic_vector
(
5
downto
0
);
reg_sr_pmisse_load_o
:
out
std_logic
;
...
...
@@ -96,8 +96,6 @@ entity conv_regs is
reg_tbmr_chan_i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for BIT field: 'White Rabbit present' in reg: 'TBMR'
reg_tbmr_wrtag_i
:
in
std_logic
;
-- Tag buffer read request, asserted when reading from TBMR
reg_tb_rd_req_p_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'TBCYR'
reg_tbcyr_i
:
in
std_logic_vector
(
27
downto
0
);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'TBTLR'
...
...
@@ -114,52 +112,66 @@ entity conv_regs is
reg_tbcsr_clr_o
:
out
std_logic
;
reg_tbcsr_clr_i
:
in
std_logic
;
reg_tbcsr_clr_load_o
:
out
std_logic
;
-- Tag buffer read request, asserted when reading from TBMR
reg_tb_rd_req_p_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH1LTSCYR'
reg_ch1ltscyr_i
:
in
std_logic_vector
(
27
downto
0
);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH1LTSTLR'
reg_ch1ltstlr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH1LTSTHR'
reg_ch1ltsthr_tai_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH1LTSTHR'
reg_ch1ltsthr_wrtag_i
:
in
std_logic
;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH2LTSCYR'
reg_ch2ltscyr_i
:
in
std_logic_vector
(
27
downto
0
);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH2LTSTLR'
reg_ch2ltstlr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH2LTSTHR'
reg_ch2ltsthr_tai_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH2LTSTHR'
reg_ch2ltsthr_wrtag_i
:
in
std_logic
;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH3LTSCYR'
reg_ch3ltscyr_i
:
in
std_logic_vector
(
27
downto
0
);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH3LTSTLR'
reg_ch3ltstlr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH3LTSTHR'
reg_ch3ltsthr_tai_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH3LTSTHR'
reg_ch3ltsthr_wrtag_i
:
in
std_logic
;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH4LTSCYR'
reg_ch4ltscyr_i
:
in
std_logic_vector
(
27
downto
0
);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH4LTSTLR'
reg_ch4ltstlr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH4LTSTHR'
reg_ch4ltsthr_tai_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH4LTSTHR'
reg_ch4ltsthr_wrtag_i
:
in
std_logic
;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH5LTSCYR'
reg_ch5ltscyr_i
:
in
std_logic_vector
(
27
downto
0
);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH5LTSTLR'
reg_ch5ltstlr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH5LTSTHR'
reg_ch5ltsthr_tai_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH5LTSTHR'
reg_ch5ltsthr_wrtag_i
:
in
std_logic
;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH6LTSCYR'
reg_ch6ltscyr_i
:
in
std_logic_vector
(
27
downto
0
);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH6LTSTLR'
reg_ch6ltstlr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH6LTSTHR'
reg_ch6ltsthr_tai_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH6LTSTHR'
reg_ch6ltsthr_wrtag_i
:
in
std_logic
;
-- Port for std_logic_vector field: 'Front panel
TTL
input state' in reg: 'LSR'
reg_lsr_front_
ttl_i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for std_logic_vector field: 'Front panel
TTL-BAR
input state' in reg: 'LSR'
reg_lsr_front
_invttl_i
:
in
std_logic_vector
(
3
downto
0
);
-- Port for std_logic_vector field: 'Front panel
channel
input state' in reg: 'LSR'
reg_lsr_front_
i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for std_logic_vector field: 'Front panel
INV-TTL
input state' in reg: 'LSR'
reg_lsr_front
inv_i
:
in
std_logic_vector
(
3
downto
0
);
-- Port for std_logic_vector field: 'Rear panel input state' in reg: 'LSR'
reg_lsr_rear_i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for std_logic_vector field: 'Input failsafe state' in reg: 'LSR'
reg_lsr_
fs_i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for std_logic_vector field: '
State of MultiCast switches
' in reg: 'MSWR'
reg_mswr_
bit_i
:
in
std_logic_vector
(
3
downto
0
)
reg_lsr_
rearfs_i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for std_logic_vector field: '
Multicast address (from switch)
' in reg: 'MSWR'
reg_mswr_
switches_i
:
in
std_logic_vector
(
3
downto
0
)
);
end
conv_regs
;
...
...
@@ -508,34 +520,7 @@ begin
when
"010000"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
27
downto
0
)
<=
reg_ch1ltscyr_i
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
...
...
@@ -581,34 +566,7 @@ begin
when
"010011"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
27
downto
0
)
<=
reg_ch2ltscyr_i
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
...
...
@@ -654,34 +612,7 @@ begin
when
"010110"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
27
downto
0
)
<=
reg_ch3ltscyr_i
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
...
...
@@ -727,34 +658,7 @@ begin
when
"011001"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
27
downto
0
)
<=
reg_ch4ltscyr_i
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
...
...
@@ -800,34 +704,7 @@ begin
when
"011100"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
27
downto
0
)
<=
reg_ch5ltscyr_i
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
...
...
@@ -873,34 +750,7 @@ begin
when
"011111"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
0
)
<=
'X'
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
27
downto
0
)
<=
reg_ch6ltscyr_i
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
...
...
@@ -946,10 +796,10 @@ begin
when
"100010"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
5
downto
0
)
<=
reg_lsr_front_
ttl_
i
;
rddata_reg
(
9
downto
6
)
<=
reg_lsr_front
_invttl
_i
;
rddata_reg
(
5
downto
0
)
<=
reg_lsr_front_i
;
rddata_reg
(
9
downto
6
)
<=
reg_lsr_front
inv
_i
;
rddata_reg
(
15
downto
10
)
<=
reg_lsr_rear_i
;
rddata_reg
(
21
downto
16
)
<=
reg_lsr_fs_i
;
rddata_reg
(
21
downto
16
)
<=
reg_lsr_
rear
fs_i
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
...
...
@@ -965,7 +815,7 @@ begin
when
"100011"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
3
downto
0
)
<=
reg_mswr_
bit
_i
;
rddata_reg
(
3
downto
0
)
<=
reg_mswr_
switches
_i
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
...
...
@@ -1011,7 +861,7 @@ begin
wb_dat_o
<=
rddata_reg
;
-- ID register bits
-- Gateware version
-- Status of on-board switches
-- Status of on-board
general-purpose
switches
-- RTM detection lines~\cite{rtm-det}
-- I2C communication watchdog timeout error
reg_sr_i2c_wdto_o
<=
wrdata_reg
(
22
);
...
...
@@ -1053,29 +903,35 @@ begin
-- Buffer empty
-- Clear tag buffer
reg_tbcsr_clr_o
<=
wrdata_reg
(
18
);
-- Cycles counter
-- Lower part of TAI seconds counter
-- Upper part of TAI seconds counter
-- White Rabbit present
-- Cycles counter
-- Lower part of TAI seconds counter
-- Upper part of TAI seconds counter
-- White Rabbit present
-- Cycles counter
-- Lower part of TAI seconds counter
-- Upper part of TAI seconds counter
-- White Rabbit present
-- Cycles counter
-- Lower part of TAI seconds counter
-- Upper part of TAI seconds counter
-- White Rabbit present
-- Cycles counter
-- Lower part of TAI seconds counter
-- Upper part of TAI seconds counter
-- White Rabbit present
-- Cycles counter
-- Lower part of TAI seconds counter
-- Upper part of TAI seconds counter
-- White Rabbit present
-- Front panel
TTL
input state
-- Front panel
TTL-BAR
input state
-- Front panel
channel
input state
-- Front panel
INV-TTL
input state
-- Rear panel input state
-- Input failsafe state
--
State of MultiCast switches
--
Multicast address (from switch)
rwaddr_reg
<=
wb_adr_i
;
wb_stall_o
<=
(
not
ack_sreg
(
0
))
and
(
wb_stb_i
and
wb_cyc_i
);
-- ACK signal generation. Just pass the LSB of ACK counter.
...
...
modules/conv_regs.wb
View file @
c1d3f39b
...
...
@@ -425,8 +425,8 @@ peripheral {
description = "Value of the 8-ns cycles counter when time tag was taken.";
type = SLV;
size = 28;
access_
bus
= WRITE_ONLY;
access_
dev
= READ_ONLY;
access_
dev
= WRITE_ONLY;
access_
bus
= READ_ONLY;
};
};
...
...
@@ -478,8 +478,8 @@ peripheral {
description = "Value of the 8-ns cycles counter when time tag was taken.";
type = SLV;
size = 28;
access_
bus
= WRITE_ONLY;
access_
dev
= READ_ONLY;
access_
dev
= WRITE_ONLY;
access_
bus
= READ_ONLY;
};
};
...
...
@@ -531,8 +531,8 @@ peripheral {
description = "Value of the 8-ns cycles counter when time tag was taken.";
type = SLV;
size = 28;
access_
bus
= WRITE_ONLY;
access_
dev
= READ_ONLY;
access_
dev
= WRITE_ONLY;
access_
bus
= READ_ONLY;
};
};
...
...
@@ -585,8 +585,8 @@ peripheral {
prefix = "tai";
type = SLV;
size = 28;
access_
bus
= WRITE_ONLY;
access_
dev
= READ_ONLY;
access_
dev
= WRITE_ONLY;
access_
bus
= READ_ONLY;
};
};
...
...
@@ -638,8 +638,8 @@ peripheral {
description = "Value of the 8-ns cycles counter when time tag was taken.";
type = SLV;
size = 28;
access_
bus
= WRITE_ONLY;
access_
dev
= READ_ONLY;
access_
dev
= WRITE_ONLY;
access_
bus
= READ_ONLY;
};
};
...
...
@@ -691,8 +691,8 @@ peripheral {
description = "Value of the 8-ns cycles counter when time tag was taken.";
type = SLV;
size = 28;
access_
bus
= WRITE_ONLY;
access_
dev
= READ_ONLY;
access_
dev
= WRITE_ONLY;
access_
bus
= READ_ONLY;
};
};
...
...
top/conv_common_gw.vhd
View file @
c1d3f39b
...
...
@@ -194,6 +194,9 @@ architecture arch of conv_common_gw is
type
t_pulse_cnt
is
array
(
5
downto
0
)
of
unsigned
(
31
downto
0
);
type
t_ch_pcr
is
array
(
5
downto
0
)
of
std_logic_vector
(
31
downto
0
);
type
t_latest_timestamp_tai
is
array
(
5
downto
0
)
of
std_logic_vector
(
39
downto
0
);
type
t_latest_timestamp_cycles
is
array
(
5
downto
0
)
of
std_logic_vector
(
27
downto
0
);
--============================================================================
-- Constant declarations
--============================================================================
...
...
@@ -222,8 +225,8 @@ architecture arch of conv_common_gw is
-- Tag bufferdata width: 40 -- TAI
-- 28 -- cycles
-- 1 -- WRPRES bit
--
xx -- channel mask
constant
c_tagbuff_data_width
:
positive
:
=
40
+
28
+
1
+
g_nr_chans
;
--
6 -- channel mask for max. nr. channels
constant
c_tagbuff_data_width
:
positive
:
=
40
+
28
+
1
+
6
;
--============================================================================
-- Signal declarations
...
...
@@ -321,6 +324,12 @@ architecture arch of conv_common_gw is
signal
buf_dat_in
:
std_logic_vector
(
c_tagbuff_data_width
-1
downto
0
);
signal
buf_dat_out
:
std_logic_vector
(
c_tagbuff_data_width
-1
downto
0
);
-- Latest timestamp signals
signal
latest_timestamp_ld
:
std_logic_vector
(
5
downto
0
);
signal
latest_timestamp_tai
:
t_latest_timestamp_tai
;
signal
latest_timestamp_cycles
:
t_latest_timestamp_cycles
;
signal
latest_timestamp_wrtag
:
std_logic_vector
(
5
downto
0
);
--==============================================================================
-- architecture begin
--==============================================================================
...
...
@@ -413,79 +422,6 @@ begin
--============================================================================
trig_a
<=
pulse_i
;
gen_pulse_timetag
:
if
(
g_with_pulse_timetag
=
true
)
generate
cmp_pulse_timetag
:
conv_pulse_timetag
generic
map
(
-- Frequency in Hz of the clk_i signal
g_clk_rate
=>
125000000
,
-- Number of repetition channels
g_nr_chan
=>
g_nr_chans
)
port
map
(
-- Clock and active-low reset
clk_i
=>
clk_125
,
rst_n_i
=>
rst_125_n
,
-- Asynchronous pulse input
pulse_a_i
=>
trig_chan
,
-- Time inputs from White Rabbit
wr_tm_cycles_i
=>
(
others
=>
'0'
),
wr_tm_tai_i
=>
(
others
=>
'0'
),
wr_tm_valid_i
=>
'0'
,
-- Timing inputs from Wishbone-mapped registers
wb_tm_tai_l_i
=>
tvlr
,
wb_tm_tai_l_ld_i
=>
tvlr_ld
,
wb_tm_tai_h_i
=>
tvhr
,
wb_tm_tai_h_ld_i
=>
tvhr_ld
,
-- Timing outputs
tm_cycles_o
=>
tm_cycles
,
tm_tai_o
=>
tm_tai
,
tm_wrpres_o
=>
buf_wrtag
,
chan_o
=>
buf_chan
,
-- Ring buffer I/O
buf_wr_req_p_o
=>
buf_wr_req_p
);
-- Assign ring buffer component inputs
buf_dat_in
(
5
downto
0
)
<=
buf_chan
;
buf_dat_in
(
6
)
<=
buf_wrtag
;
buf_dat_in
(
34
downto
7
)
<=
tm_cycles
;
buf_dat_in
(
74
downto
35
)
<=
tm_tai
;
-- Instantiate the ring buffer
cmp_ring_buf
:
conv_ring_buf
generic
map
(
g_data_width
=>
c_tagbuff_data_width
,
g_size
=>
128
)
port
map
(
-- Clocks and reset
clk_rd_i
=>
clk_20_i
,
clk_wr_i
=>
clk_125
,
rst_n_a_i
=>
rst_20_n
,
-- Buffer inputs
buf_dat_i
=>
buf_dat_in
,
buf_rd_req_i
=>
buf_rd_req_p
,
buf_wr_req_i
=>
buf_wr_req_p
,
buf_clr_i
=>
buf_clr_p
,
-- Buffer outputs
buf_dat_o
=>
buf_dat_out
,
buf_full_o
=>
buf_full
,
buf_empty_o
=>
buf_empty
,
buf_count_o
=>
buf_count
);
end
generate
gen_pulse_timetag
;
gen_pulse_chan_logic
:
for
i
in
0
to
g_nr_chans
-1
generate
-- Synchronize the asynchronous trigger input into the 20 MHz clock
...
...
@@ -627,6 +563,87 @@ end generate gen_pulse_cnt;
end
generate
gen_pulse_chan_logic
;
gen_pulse_timetag
:
if
(
g_with_pulse_timetag
=
true
)
generate
cmp_pulse_timetag
:
conv_pulse_timetag
generic
map
(
-- Frequency in Hz of the clk_i signal
g_clk_rate
=>
125000000
,
-- Number of repetition channels
g_nr_chan
=>
g_nr_chans
)
port
map
(
-- Clock and active-low reset
clk_i
=>
clk_125
,
rst_n_i
=>
rst_125_n
,
-- Asynchronous pulse input
pulse_a_i
=>
trig_chan
,
-- Time inputs from White Rabbit
wr_tm_cycles_i
=>
(
others
=>
'0'
),
wr_tm_tai_i
=>
(
others
=>
'0'
),
wr_tm_valid_i
=>
'0'
,
-- Timing inputs from Wishbone-mapped registers
wb_tm_tai_l_i
=>
tvlr
,
wb_tm_tai_l_ld_i
=>
tvlr_ld
,
wb_tm_tai_h_i
=>
tvhr
,
wb_tm_tai_h_ld_i
=>
tvhr_ld
,
-- Timing outputs
tm_cycles_o
=>
tm_cycles
,
tm_tai_o
=>
tm_tai
,
tm_wrpres_o
=>
buf_wrtag
,
chan_p_o
=>
buf_chan
,
-- Ring buffer I/O
buf_wr_req_p_o
=>
buf_wr_req_p
);
-- Assign ring buffer component inputs
gen_buf_chan
:
if
(
g_nr_chans
=
6
)
generate
buf_dat_in
(
5
downto
0
)
<=
buf_chan
;
end
generate
gen_buf_chan
;
gen_buf_chan_unused_chans
:
if
(
g_nr_chans
<
6
)
generate
buf_dat_in
(
g_nr_chans
-1
downto
0
)
<=
buf_chan
;
buf_dat_in
(
5
downto
g_nr_chans
)
<=
(
others
=>
'0'
);
end
generate
gen_buf_chan_unused_chans
;
buf_dat_in
(
6
)
<=
buf_wrtag
;
buf_dat_in
(
34
downto
7
)
<=
tm_cycles
;
buf_dat_in
(
74
downto
35
)
<=
tm_tai
;
-- Instantiate the ring buffer
cmp_ring_buf
:
conv_ring_buf
generic
map
(
g_data_width
=>
c_tagbuff_data_width
,
g_size
=>
128
)
port
map
(
-- Clocks and reset
clk_rd_i
=>
clk_20_i
,
clk_wr_i
=>
clk_125
,
rst_n_a_i
=>
rst_20_n
,
-- Buffer inputs
buf_dat_i
=>
buf_dat_in
,
buf_rd_req_i
=>
buf_rd_req_p
,
buf_wr_req_i
=>
buf_wr_req_p
,
buf_clr_i
=>
buf_clr_p
,
-- Buffer outputs
buf_dat_o
=>
buf_dat_out
,
buf_full_o
=>
buf_full
,
buf_empty_o
=>
buf_empty
,
buf_count_o
=>
buf_count
);
end
generate
gen_pulse_timetag
;
-- Channel output assignments
pulse_o
<=
pulse_outp
;
led_pulse_o
<=
led_pulse
;
...
...
@@ -888,6 +905,32 @@ end generate;
end
if
;
end
process
p_tbcsr_clr
;
-- Implement the latest timestamp registers
-- NOTE: Updated in the 125 MHz clock domain
p_latest_timestamp
:
process
(
clk_125
)
begin
if
rising_edge
(
clk_125
)
then
for
i
in
0
to
g_nr_chans
-1
loop
if
(
rst_125_n
=
'0'
)
then
latest_timestamp_cycles
(
i
)
<=
(
others
=>
'0'
);
latest_timestamp_tai
(
i
)
<=
(
others
=>
'0'
);
latest_timestamp_wrtag
(
i
)
<=
'0'
;
elsif
(
buf_chan
(
i
)
=
'1'
)
then
latest_timestamp_cycles
(
i
)
<=
tm_cycles
;
latest_timestamp_tai
(
i
)
<=
tm_tai
;
latest_timestamp_wrtag
(
i
)
<=
buf_wrtag
;
end
if
;
end
loop
;
end
if
;
end
process
p_latest_timestamp
;
-- Connect unused timestamps to all zeroes
gen_latest_timestamp_unused_chans
:
if
(
g_nr_chans
<
6
)
generate
latest_timestamp_cycles
(
5
downto
g_nr_chans
)
<=
(
others
=>
(
others
=>
'0'
));
latest_timestamp_tai
(
5
downto
g_nr_chans
)
<=
(
others
=>
(
others
=>
'0'
));
latest_timestamp_tai
(
5
downto
g_nr_chans
)
<=
(
others
=>
(
others
=>
'0'
));
end
generate
gen_latest_timestamp_unused_chans
;
-- Then, instantiate the component
cmp_conv_regs
:
conv_regs
port
map
(
...
...
@@ -912,7 +955,7 @@ end generate;
reg_sr_i2c_wdto_o
=>
i2c_wdto_bit_rst
,
reg_sr_i2c_wdto_i
=>
i2c_wdto_bit
,
reg_sr_i2c_wdto_load_o
=>
i2c_wdto_bit_rst_ld
,
reg_sr_wrpres_i
=>
'0'
,
reg_sr_wrpres_i
=>
wrpres
,
reg_sr_i2c_err_o
=>
i2c_err_bit_rst
,
reg_sr_i2c_err_i
=>
i2c_err_bit
,
reg_sr_i2c_err_load_o
=>
i2c_err_bit_rst_ld
,
...
...
@@ -968,31 +1011,37 @@ end generate;
reg_tbcsr_full_i
=>
buf_full
,
reg_tbcsr_empty_i
=>
buf_empty
,
reg_ch1ltstlr_i
=>
(
others
=>
'0'
),
reg_ch1ltsthr_tai_i
=>
(
others
=>
'0'
),
reg_ch1ltsthr_wrtag_i
=>
'0'
,
reg_ch2ltstlr_i
=>
(
others
=>
'0'
),
reg_ch2ltsthr_tai_i
=>
(
others
=>
'0'
),
reg_ch2ltsthr_wrtag_i
=>
'0'
,
reg_ch3ltstlr_i
=>
(
others
=>
'0'
),
reg_ch3ltsthr_tai_i
=>
(
others
=>
'0'
),
reg_ch3ltsthr_wrtag_i
=>
'0'
,
reg_ch4ltstlr_i
=>
(
others
=>
'0'
),
reg_ch4ltsthr_tai_i
=>
(
others
=>
'0'
),
reg_ch4ltsthr_wrtag_i
=>
'0'
,
reg_ch5ltstlr_i
=>
(
others
=>
'0'
),
reg_ch5ltsthr_tai_i
=>
(
others
=>
'0'
),
reg_ch5ltsthr_wrtag_i
=>
'0'
,
reg_ch6ltstlr_i
=>
(
others
=>
'0'
),
reg_ch6ltsthr_tai_i
=>
(
others
=>
'0'
),
reg_ch6ltsthr_wrtag_i
=>
'0'
,
reg_lsr_front_ttl_i
=>
line_front
,
reg_lsr_front_invttl_i
=>
line_inv_i
,
reg_ch1ltscyr_i
=>
latest_timestamp_cycles
(
0
),
reg_ch1ltstlr_i
=>
latest_timestamp_tai
(
0
)(
31
downto
0
),
reg_ch1ltsthr_tai_i
=>
latest_timestamp_tai
(
0
)(
39
downto
32
),
reg_ch1ltsthr_wrtag_i
=>
latest_timestamp_wrtag
(
0
),
reg_ch2ltscyr_i
=>
latest_timestamp_cycles
(
1
),
reg_ch2ltstlr_i
=>
latest_timestamp_tai
(
1
)(
31
downto
0
),
reg_ch2ltsthr_tai_i
=>
latest_timestamp_tai
(
1
)(
39
downto
32
),
reg_ch2ltsthr_wrtag_i
=>
latest_timestamp_wrtag
(
1
),
reg_ch3ltscyr_i
=>
latest_timestamp_cycles
(
2
),
reg_ch3ltstlr_i
=>
latest_timestamp_tai
(
2
)(
31
downto
0
),
reg_ch3ltsthr_tai_i
=>
latest_timestamp_tai
(
2
)(
39
downto
32
),
reg_ch3ltsthr_wrtag_i
=>
latest_timestamp_wrtag
(
2
),
reg_ch4ltscyr_i
=>
latest_timestamp_cycles
(
3
),
reg_ch4ltstlr_i
=>
latest_timestamp_tai
(
3
)(
31
downto
0
),
reg_ch4ltsthr_tai_i
=>
latest_timestamp_tai
(
3
)(
39
downto
32
),
reg_ch4ltsthr_wrtag_i
=>
latest_timestamp_wrtag
(
3
),
reg_ch5ltscyr_i
=>
latest_timestamp_cycles
(
4
),
reg_ch5ltstlr_i
=>
latest_timestamp_tai
(
4
)(
31
downto
0
),
reg_ch5ltsthr_tai_i
=>
latest_timestamp_tai
(
4
)(
39
downto
32
),
reg_ch5ltsthr_wrtag_i
=>
latest_timestamp_wrtag
(
4
),
reg_ch6ltscyr_i
=>
latest_timestamp_cycles
(
5
),
reg_ch6ltstlr_i
=>
latest_timestamp_tai
(
5
)(
31
downto
0
),
reg_ch6ltsthr_tai_i
=>
latest_timestamp_tai
(
5
)(
39
downto
32
),
reg_ch6ltsthr_wrtag_i
=>
latest_timestamp_wrtag
(
5
),
reg_lsr_front_i
=>
line_front
,
reg_lsr_frontinv_i
=>
line_inv_i
,
reg_lsr_rear_i
=>
line_rear
,
reg_lsr_
fs_i
=>
line_rear_fs
,
reg_lsr_
rearfs_i
=>
line_rear_fs
,
reg_mswr_
bit_i
=>
sw_multicast_i
reg_mswr_
switches_i
=>
sw_multicast_i
);
--============================================================================
...
...
top/conv_common_gw_pkg.vhd
View file @
c1d3f39b
...
...
@@ -342,52 +342,64 @@ package conv_common_gw_pkg is
reg_tbcsr_clr_o
:
out
std_logic
;
reg_tbcsr_clr_i
:
in
std_logic
;
reg_tbcsr_clr_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH1LTSCYR'
reg_ch1ltscyr_i
:
in
std_logic_vector
(
27
downto
0
);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH1LTSTLR'
reg_ch1ltstlr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH1LTSTHR'
reg_ch1ltsthr_tai_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH1LTSTHR'
reg_ch1ltsthr_wrtag_i
:
in
std_logic
;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH2LTSCYR'
reg_ch2ltscyr_i
:
in
std_logic_vector
(
27
downto
0
);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH2LTSTLR'
reg_ch2ltstlr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH2LTSTHR'
reg_ch2ltsthr_tai_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH2LTSTHR'
reg_ch2ltsthr_wrtag_i
:
in
std_logic
;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH3LTSCYR'
reg_ch3ltscyr_i
:
in
std_logic_vector
(
27
downto
0
);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH3LTSTLR'
reg_ch3ltstlr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH3LTSTHR'
reg_ch3ltsthr_tai_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH3LTSTHR'
reg_ch3ltsthr_wrtag_i
:
in
std_logic
;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH4LTSCYR'
reg_ch4ltscyr_i
:
in
std_logic_vector
(
27
downto
0
);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH4LTSTLR'
reg_ch4ltstlr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH4LTSTHR'
reg_ch4ltsthr_tai_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH4LTSTHR'
reg_ch4ltsthr_wrtag_i
:
in
std_logic
;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH5LTSCYR'
reg_ch5ltscyr_i
:
in
std_logic_vector
(
27
downto
0
);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH5LTSTLR'
reg_ch5ltstlr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH5LTSTHR'
reg_ch5ltsthr_tai_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH5LTSTHR'
reg_ch5ltsthr_wrtag_i
:
in
std_logic
;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH6LTSCYR'
reg_ch6ltscyr_i
:
in
std_logic_vector
(
27
downto
0
);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH6LTSTLR'
reg_ch6ltstlr_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH6LTSTHR'
reg_ch6ltsthr_tai_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH6LTSTHR'
reg_ch6ltsthr_wrtag_i
:
in
std_logic
;
-- Port for std_logic_vector field: 'Front panel
TTL
input state' in reg: 'LSR'
reg_lsr_front_
ttl_i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for std_logic_vector field: 'Front panel
TTL-BAR
input state' in reg: 'LSR'
reg_lsr_front
_invttl_i
:
in
std_logic_vector
(
3
downto
0
);
-- Port for std_logic_vector field: 'Front panel
channel
input state' in reg: 'LSR'
reg_lsr_front_
i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for std_logic_vector field: 'Front panel
INV-TTL
input state' in reg: 'LSR'
reg_lsr_front
inv_i
:
in
std_logic_vector
(
3
downto
0
);
-- Port for std_logic_vector field: 'Rear panel input state' in reg: 'LSR'
reg_lsr_rear_i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for std_logic_vector field: 'Input failsafe state' in reg: 'LSR'
reg_lsr_
fs_i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for std_logic_vector field: '
State of MultiCast switches
' in reg: 'MSWR'
reg_mswr_
bit_i
:
in
std_logic_vector
(
3
downto
0
)
reg_lsr_
rearfs_i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for std_logic_vector field: '
Multicast address (from switch)
' in reg: 'MSWR'
reg_mswr_
switches_i
:
in
std_logic_vector
(
3
downto
0
)
);
end
component
conv_regs
;
...
...
@@ -427,7 +439,7 @@ package conv_common_gw_pkg is
rst_n_i
:
in
std_logic
;
-- Asynchronous pulse input
pulse_a_i
:
in
std_logic_vector
(
g_nr_chan
downto
1
);
pulse_a_i
:
in
std_logic_vector
(
g_nr_chan
-1
downto
0
);
-- Time inputs from White Rabbit
wr_tm_cycles_i
:
in
std_logic_vector
(
27
downto
0
);
...
...
@@ -444,10 +456,10 @@ package conv_common_gw_pkg is
tm_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
tm_tai_o
:
out
std_logic_vector
(
39
downto
0
);
tm_wrpres_o
:
out
std_logic
;
chan_
o
:
out
std_logic_vector
(
g_nr_chan
downto
1
);
chan_
p_o
:
out
std_logic_vector
(
g_nr_chan
-1
downto
0
);
-- Ring buffer I/O
buf_wr_req_p_o
:
out
std_logic
buf_wr_req_p_o
:
out
std_logic
);
end
component
conv_pulse_timetag
;
...
...
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