Commit 8e4921b9 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

doc: Update memory map and add appendix

The memory map has been updated to include the thermometer SDB
descriptor.

Appendix B was added, containing guidelines on how to implement
a pulse repeater with more than six channels.
parent 3a692ef1
......@@ -63,3 +63,9 @@
howpublished = {\url{http://www.xilinx.com/support/documentation/user_guides/ug380.pdf}}
}
@misc{onewire-core,
author = {Iztok Jeras},
title = {{sockit\_owm, 1-wire (onewire) master}},
year = 2011,
note = {\url{http://opencores.org/websvn,filedetails?repname=sockit_owm&path=%2Fsockit_owm%2Ftrunk%2Fdoc%2Fsockit_owr.pdf}}
}
......@@ -9,8 +9,8 @@
% Hyperrefs
\usepackage[
colorlinks = true,
linkcolor = Mahogany,
citecolor = Mahogany,
linkcolor = black,
citecolor = black,
urlcolor = blue,
]{hyperref}
......@@ -415,10 +415,8 @@ for signaling communication.
%==============================================================================
The \textit{conv\_regs} module contains various Wishbone-addressable registers that contain status information,
as well as select control functionality.
It is the module which constrains \textit{conv\_common\_gw} to a maximum of six
pulse repetition channels, due to need of compatibility with previously-released
as well as select control functionality. It is the module which constrains \textit{conv\_common\_gw}
to a maximum of six pulse repetition channels, due to need of compatibility with previously-released
implementations of the \textit{conv\_regs} memory map.
Some of the bits in the converter board registers are set from inside the \textit{conv\_common\_gw}
......@@ -430,7 +428,7 @@ The inputs that connect to bits in the status register are shown in Table~\ref{t
Should some of these inputs not be used, such as for example the failsafe lines in the case of CONV-TTL-BLO~\cite{conv-ttl-blo-ohwr},
the corresponding lines should be connected to all-zeroes.
Finally, the \textit{g\_board\_id} and \textit{g\_gwvers} generics connect to registers in
The \textit{g\_board\_id} and \textit{g\_gwvers} generics connect to registers in
\textit{conv\_regs} as shown in Figure~\ref{fig:bidr-gwvers}.
\begin{table}[h]
......@@ -459,6 +457,16 @@ Finally, the \textit{g\_board\_id} and \textit{g\_gwvers} generics connect to re
\caption{\label{fig:bidr-gwvers} BIDR and SR.GWVERS connections}
\end{figure}
Some bits or fields inside \textit{conv\_regs} are generated based on the settings of
\textit{g\_with\_*} generics. Should such a generic set to \textit{false}, the corresponding
bits or fields in \textit{conv\_regs} are set to a 'safe' value of '0'. Consult the code
for details on how this is done and which are the fields concerned.
Note that the logic allows less than 6 pulse repetition channels, but not more.
If \textit{g\_nr\_chans < 6}, then the rest of the bits are automatically set to '0',
as in the case a \textit{g\_with\_*} generic is \textit{false}. If \textit{g\_nr\_chans > 6}
a synthesis error will be thrown.
%==============================================================================
\subsection{MultiBoot}
\label{subsec:multiboot}
......@@ -500,21 +508,97 @@ The following sections list the memory map of each peripheral.
\hline
Board registers & 0x000 & 0x0ff & Coverter board registers \\
MultiBoot & 0x100 & 0x110 & MultiBoot module \\
One-wire master & 0x200 & 0x2ff & One-wire master for DS18B20 thermometer module \\
SDB descriptor & 0xf00 & 0xfff & SDB descriptor (see~\cite{sdb}) \\
\hline
\end{tabular}
}
\end{table}
%%------------------------------------------------------------------------------
%% SUBSEC: conv_regs
%% SUBSEC: conv-regs
%%------------------------------------------------------------------------------
\include{conv-regs}
%\include{tmp}
%------------------------------------------------------------------------------
% SUBSEC: MultiBoot
%------------------------------------------------------------------------------
\include{multiboot-regs}
%------------------------------------------------------------------------------
% SUBSEC: Thermo
%------------------------------------------------------------------------------
\subsection{Thermometer module}
\label{app:memmap-thermo}
\indent Base address: 0x080
\vspace*{11pt}
\centerline
{
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l l l p{.5\textwidth}}
\hline
\textbf{Offset} & \textbf{Default} & \textbf{Name} & \textbf{Description} \\
\hline
0x00 & 0x00000000 & OWCSR & One-Wire Control and Status Register \\
0x04 & 0x00000004 & OWCDR & One-Wire Clock Divider Registers \\
\hline
\end{tabular}
}
\vspace*{11pt}
For details on the bits of the thermometer module access registers, see the
OneWire Master module's documentation~\cite{onewire-core}.
Note that the OWCDR should be set accordingly for proper functioning of the
one-wire timings. The value for the current version of the gateware is
\verb-OWCDR = 0x00130063-.
%==============================================================================
% APP: Changing the code for more than six pulse repetition channels
%==============================================================================
\pagebreak
\section{Gateware for pulse converters with more than six conversion channels}
\label{app:more-than-six-chans}
This appendix offers guidelines on how to use or change \textit{conv\_common\_gw}
should a pulse repeater with more than six channels be eventually implemented.
Note that none of the guidelines here have been tested, since no board exists
with more than six channels at the time of writing of this document.
The first option is obviously instantiating more than one \textit{conv\_common\_gw}
component, each with its appropriate \textit{g\_nr\_chans} and making the appropriate connections
to the FPGA outputs. Note that each \textit{conv\_common\_gw} will
come with its own \textit{conv\_regs}, MultiBoot and one-wire master peripherals.
In this case, since it is expected that there is only one flash and thermometer
chip on-board, connect only the outputs of one of the \textit{conv\_common\_gw} modules
to the top-level module outputs, as shown in Figure~\ref{fig:more-than-six-chans}.
The synthesis tool should be smart enough to optimize away the unused modules.
\begin{figure}[h]
\centerline{\includegraphics[width=1.1\textwidth]{fig/more-than-six-chans}}
\caption{\label{fig:more-than-six-chans} Connect the outputs of only one \textit{conv\_common\_gw} module at the top-level}
\end{figure}
\pagebreak
The second, non-encouraged option, is to change the \textit{conv\_common\_gw} code.
Note that this will:
\begin{enumerate}
\item Involve changing the memory map and \textit{conv\_regs} component,
which will
\item Make the \textit{conv\_common\_gw} module incompatible with the
version described in this document
\end{enumerate}
If this option is chosen, the reader should start by changing the
\textit{c\_max\_nr\_chans} generic in the package file (\textit{conv\_common\_gw\_pkg.vhd}).
Then, a new memory map should be chosen and the \textit{conv\_regs} component
adapted as appropriate.
%==============================================================================
\end{appendices}
......
......@@ -32,7 +32,7 @@ Base address: 0x000
0x30 & 0x00000000 & TBCYR & Tag Buffer Cycles Register\\
0x34 & 0x00000000 & TBTLR & Tag Buffer TAI Low Register\\
0x38 & 0x00000000 & TBTHR & Tag Buffer TAI High Register\\
0x3c & 0x00000000 & TBCSR & Tag Buffer Control and Status Register\\
0x3c & 0x00020000 & TBCSR & Tag Buffer Control and Status Register\\
0x40 & 0x00000000 & CH1LTSCYR & Channel 1 Latest Timestamp Cycles Register\\
0x44 & 0x00000000 & CH1LTSTLR & Channel 1 Latest Timestamp TAI Low Register\\
0x48 & 0x00000000 & CH1LTSTHR & Channel 1 Latest Timestamp TAI High Register\\
......@@ -111,7 +111,7 @@ Reset value: \textit{g\_board\_id}
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}PMISSE} & \multicolumn{1}{|c|}{\cellcolor{gray!25}I2C\_ERR}\\
\multicolumn{1}{|c}{-} & \multicolumn{6}{|c|}{\cellcolor{gray!25}PMISSE[5:0]} & \multicolumn{1}{|c|}{\cellcolor{gray!25}I2C\_ERR}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
......@@ -176,7 +176,7 @@ I2C\_ERR
PMISSE
} [\emph{read/write}]: Pulse missed error
\\
1 -- pulse arrived during pulse rejection phase \\ 0 -- idle \\ This bit can be cleared by writing a '1' to it
1 -- pulse arrived during pulse rejection phase \\ 0 -- idle \\ Bit 0 -- channel 1 \\ Bit 1 -- channel 2 \\ etc. \\ Each bit can be cleared by writing a '1' to it
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
......
This diff is collapsed.
......@@ -131,8 +131,8 @@ peripheral {
name = "Pulse missed error";
description = "1 -- pulse arrived during pulse rejection phase \
0 -- idle \
Bit 0 -- CH1 \
Bit 1 -- CH2 \
Bit 0 -- channel 1 \
Bit 1 -- channel 2 \
etc. \
Each bit can be cleared by writing a '1' to it";
prefix = "pmisse";
......
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