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conv-common-gw
Commit 686c0b2c authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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doc: Add VME_SYSRESET_N pin as reset source (Reset section)

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doc/conv-common-gw.tex
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...@@ -254,15 +254,17 @@ An internal reset generator (\textit{conv\_reset\_gen}) is used to supply a rese ...@@ -254,15 +254,17 @@ An internal reset generator (\textit{conv\_reset\_gen}) is used to supply a rese
modules of the \textit{conv\_common\_gw}, so that they start up in a known state. modules of the \textit{conv\_common\_gw}, so that they start up in a known state.
This reset pulse occurs either when the FPGA finishes configuration and goes into user mode, or when This reset pulse occurs either when the FPGA finishes configuration and goes into user mode, or when
an external reset is received via the control register (CR) in the converter board registers component. an external reset is received. The external reset can come from one of two sources:
To be able to issue an external reset, the reset bit in the CR must be unlocked via the reset \begin{itemize}
unlock bit. \item the VME system reset pin
\item a write to the CR.RST bit, after having been previously unlocked by a write to the
CR.RST\_UNLOCK bit (see Appendix~\ref{app:conv-regs-cr})
\end{itemize}
The \textit{conv\_reset\_gen} component is clocked from \textit{clk\_20\_i}, so the reset The \textit{conv\_reset\_gen} component is clocked from \textit{clk\_20\_i}, so the reset
it generates is in the 20~MHz clock domain. This is also the reset that is present at the it generates is in the 20~MHz clock domain. This is also the reset that is present at the
\textit{rst\_n\_o} pin. \textit{rst\_n\_o} pin. A reset synchronized to the 125~MHz clock domain is generated
%A reset synchronized to the 125~MHz clock domain is generated inside \textit{conv\_common\_gw}, but this is not provided at the output.
%inside \textit{conv\_common\_gw}, but this is not provided at the output.
Note that the VHDL of this module is Xilinx and XST-specific and porting to a different Note that the VHDL of this module is Xilinx and XST-specific and porting to a different
FPGA architecture or synthesis tool is not guaranteed to provide the same results. FPGA architecture or synthesis tool is not guaranteed to provide the same results.
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