Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
C
conv-common-gw
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Commits
Open sidebar
level-conversion
conv-common-gw
Commits
686c0b2c
Commit
686c0b2c
authored
Aug 29, 2014
by
Theodor-Adrian Stana
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
doc: Add VME_SYSRESET_N pin as reset source (Reset section)
parent
1ededea0
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
8 additions
and
6 deletions
+8
-6
conv-common-gw.tex
doc/conv-common-gw.tex
+8
-6
No files found.
doc/conv-common-gw.tex
View file @
686c0b2c
...
...
@@ -254,15 +254,17 @@ An internal reset generator (\textit{conv\_reset\_gen}) is used to supply a rese
modules of the
\textit
{
conv
\_
common
\_
gw
}
, so that they start up in a known state.
This reset pulse occurs either when the FPGA finishes configuration and goes into user mode, or when
an external reset is received via the control register (CR) in the converter board registers component.
To be able to issue an external reset, the reset bit in the CR must be unlocked via the reset
unlock bit.
an external reset is received. The external reset can come from one of two sources:
\begin{itemize}
\item
the VME system reset pin
\item
a write to the CR.RST bit, after having been previously unlocked by a write to the
CR.RST
\_
UNLOCK bit (see Appendix~
\ref
{
app:conv-regs-cr
}
)
\end{itemize}
The
\textit
{
conv
\_
reset
\_
gen
}
component is clocked from
\textit
{
clk
\_
20
\_
i
}
, so the reset
it generates is in the 20~MHz clock domain. This is also the reset that is present at the
\textit
{
rst
\_
n
\_
o
}
pin.
%A reset synchronized to the 125~MHz clock domain is generated
%inside \textit{conv\_common\_gw}, but this is not provided at the output.
\textit
{
rst
\_
n
\_
o
}
pin. A reset synchronized to the 125~MHz clock domain is generated
inside
\textit
{
conv
\_
common
\_
gw
}
, but this is not provided at the output.
Note that the VHDL of this module is Xilinx and XST-specific and porting to a different
FPGA architecture or synthesis tool is not guaranteed to provide the same results.
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment