Commit 59dbc7a0 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag

Added two more bits to the hwversion register to represent revision number, eg: v4.2 =>v4 rev2

parent 467bc957
......@@ -2,17 +2,17 @@
Register definitions for slave core: Converter board registers
* File : conv_regs.h
* Author : auto-generated by wbgen2 from .\conv_regs.wb
* Created : 02/01/17 15:43:01
* Author : auto-generated by wbgen2 from conv_regs.wb
* Created : 02/06/17 15:05:15
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE .\conv_regs.wb
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS__\CONV_REGS_WB
#define __WBGEN2_REGDEFS__\CONV_REGS_WB
#ifndef __WBGEN2_REGDEFS_CONV_REGS_WB
#define __WBGEN2_REGDEFS_CONV_REGS_WB
#include <inttypes.h>
......@@ -47,20 +47,20 @@
#define REG_SR_SWITCHES_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define REG_SR_SWITCHES_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
/* definitions for field: RTM detection lines~\cite{rtm-det} in reg: SR */
/* definitions for field: RTM detection lines cite{rtm-det} in reg: SR */
#define REG_SR_RTM_MASK WBGEN2_GEN_MASK(16, 6)
#define REG_SR_RTM_SHIFT 16
#define REG_SR_RTM_W(value) WBGEN2_GEN_WRITE(value, 16, 6)
#define REG_SR_RTM_R(reg) WBGEN2_GEN_READ(reg, 16, 6)
/* definitions for field: Hardware version in reg: SR */
#define REG_SR_HWVERS_MASK WBGEN2_GEN_MASK(22, 4)
#define REG_SR_HWVERS_MASK WBGEN2_GEN_MASK(22, 6)
#define REG_SR_HWVERS_SHIFT 22
#define REG_SR_HWVERS_W(value) WBGEN2_GEN_WRITE(value, 22, 4)
#define REG_SR_HWVERS_R(reg) WBGEN2_GEN_READ(reg, 22, 4)
#define REG_SR_HWVERS_W(value) WBGEN2_GEN_WRITE(value, 22, 6)
#define REG_SR_HWVERS_R(reg) WBGEN2_GEN_READ(reg, 22, 6)
/* definitions for field: White Rabbit present in reg: SR */
#define REG_SR_WRPRES WBGEN2_GEN_MASK(26, 1)
#define REG_SR_WRPRES WBGEN2_GEN_MASK(28, 1)
/* definitions for register: ERR */
......
......@@ -1015,7 +1015,7 @@ wb_stb_i
</td>
<td class="td_pblock_right">
reg_sr_hwvers_i[3:0]
reg_sr_hwvers_i[5:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -4709,17 +4709,17 @@ Status Register
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
WRPRES
</td>
<td style="border: solid 1px black;" colspan=2 class="td_field">
HWVERS[3:2]
<td style="border: solid 1px black;" colspan=4 class="td_field">
HWVERS[5:2]
</td>
<td >
</td>
<td >
</td>
<td >
......@@ -4896,15 +4896,15 @@ GWVERS
<li><b>
SWITCHES
</b>[<i>read-only</i>]: Status of on-board general-purpose switches
<br>1 -- switch is ON <br> 0 -- switch is OFF
<br>Eg: SW1.1-- SR.SWITCHES[0] <br> SW1.2-- SR.SWITCHES[1] <br> SW2.1-- SR.SWITCHES[4] <br> SW2.4-- SR.SWITCHES[7] <br> 1 -- switch is ON <br> 0 -- switch is OFF
<li><b>
RTM
</b>[<i>read-only</i>]: RTM detection lines~\cite{rtm-det}
<br>1 -- line active <br> 0 -- line inactive
</b>[<i>read-only</i>]: RTM detection lines cite{rtm-det}
<br>1 bit per RTM output channel <br> 1 -- line active <br> 0 -- line inactive
<li><b>
HWVERS
</b>[<i>read-only</i>]: Hardware version
<br>PCB version - Hardwired on the board <br> Only meaningful for HW v4 and over <br> Earlier versions show 0 <br> e.g. <br> 0x04 -- hw v4 <br> 0x05 -- hw v5 <br> 0x00 -- hw v3 and earlier
<br>PCB version - Hardwired on the board <br> Only meaningful for HW v4.0 and over <br> Earlier versions show 0. The register <br> uses 4 bits for the version number and<br> 2 bits for the execution.<br> e.g. <br> 0x010001 -- hw v4.1 <br> 0x010111 -- hw v5.3 <br> 0x00-- hw v3 and earlier
<li><b>
WRPRES
</b>[<i>read-only</i>]: White Rabbit present
......
This diff is collapsed.
......@@ -2,11 +2,11 @@
-- Title : Wishbone slave core for Converter board registers
---------------------------------------------------------------------------------------
-- File : .\conv_regs.vhd
-- Author : auto-generated by wbgen2 from .\conv_regs.wb
-- Created : 02/01/17 15:43:00
-- Author : auto-generated by wbgen2 from conv_regs.wb
-- Created : 02/06/17 15:05:15
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE .\conv_regs.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
......@@ -33,10 +33,10 @@ entity conv_regs is
reg_sr_gwvers_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'Status of on-board general-purpose switches' in reg: 'SR'
reg_sr_switches_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM detection lines~\cite{rtm-det}' in reg: 'SR'
-- Port for std_logic_vector field: 'RTM detection lines cite{rtm-det}' in reg: 'SR'
reg_sr_rtm_i : in std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Hardware version' in reg: 'SR'
reg_sr_hwvers_i : in std_logic_vector(3 downto 0);
reg_sr_hwvers_i : in std_logic_vector(5 downto 0);
-- Port for BIT field: 'White Rabbit present' in reg: 'SR'
reg_sr_wrpres_i : in std_logic;
-- Ports for BIT field: 'I2C communication watchdog timeout error' in reg: 'ERR'
......@@ -335,10 +335,8 @@ begin
rddata_reg(7 downto 0) <= reg_sr_gwvers_i;
rddata_reg(15 downto 8) <= reg_sr_switches_i;
rddata_reg(21 downto 16) <= reg_sr_rtm_i;
rddata_reg(25 downto 22) <= reg_sr_hwvers_i;
rddata_reg(26) <= reg_sr_wrpres_i;
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(27 downto 22) <= reg_sr_hwvers_i;
rddata_reg(28) <= reg_sr_wrpres_i;
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
......@@ -991,7 +989,7 @@ begin
-- ID register bits
-- Gateware version
-- Status of on-board general-purpose switches
-- RTM detection lines~\cite{rtm-det}
-- RTM detection lines cite{rtm-det}
-- Hardware version
-- White Rabbit present
-- I2C communication watchdog timeout error
......
......@@ -82,8 +82,12 @@ peripheral {
};
field {
name = "Status of on-board general-purpose switches";
description = "1 -- switch is ON \
0 -- switch is OFF";
description = "Eg: SW1.1-- SR.SWITCHES[0] \
SW1.2-- SR.SWITCHES[1] \
SW2.1-- SR.SWITCHES[4] \
SW2.4-- SR.SWITCHES[7] \
1 -- switch is ON \
0 -- switch is OFF";
prefix = "switches";
type = SLV;
size = 8;
......@@ -91,8 +95,9 @@ peripheral {
access_bus = READ_ONLY;
};
field {
name = "RTM detection lines~\\cite{rtm-det}";
description = "1 -- line active \
name = "RTM detection lines \cite{rtm-det}";
description = "1 bit per RTM output channel \
1 -- line active \
0 -- line inactive";
prefix = "rtm";
type = SLV;
......@@ -103,15 +108,17 @@ peripheral {
field {
name = "Hardware version";
description = "PCB version - Hardwired on the board \
Only meaningful for HW v4 and over \
Earlier versions show 0 \
Only meaningful for HW v4.0 and over \
Earlier versions show 0. The register \
uses 4 bits for the version number and\
2 bits for the execution.\
e.g. \
0x04 -- hw v4 \
0x05 -- hw v5 \
0x00 -- hw v3 and earlier";
0x010001 -- hw v4.1 \
0x010111 -- hw v5.3 \
0x00-- hw v3 and earlier";
prefix = "hwvers";
type = SLV;
size = 4;
size = 6;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
......
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