Commit 4f5893c4 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag

Doc: Modified pulse-gen and pulse-cnt sections according to redesign.

parent 84b412d7
......@@ -286,9 +286,9 @@ By default, the reset time is set to 100~ms.
\label{sec:chan-logic}
The channel logic is presented in Figure~\ref{fig:chan-logic}. The central part
thereof is a pulse generator which can be configured for pass-through mode, or
thereof is a pulse generator followed by a burst mode controller. The former can be configured for pass-through mode, or
fixed-width pulse generation with subsequent pulse rejection after a pulse has
been generated. The generator can be triggered in two ways:
been generated. The latter (the burst controller) allows high frequency bursts to be repeated for a limited period of time, as defined by some internal parameters, see Section~\ref{subsec:burst-ctrl}. The generator itself can be triggered in two ways:
\begin{itemize}
\item by the pulse input, which can be fed directly to the generator's input,
......@@ -355,7 +355,9 @@ For information on the module's implementation, consult its documentation in the
Figure~\ref{fig:pulse-cnt} presents the implementation of the pulse counters.
When a pulse arrives on either the TTL or blocking side, it is resynchronized
in the 20~MHz clock domain and passed to a \textit{fast counter} module. Indeed, at high frequencies it was found that internal counters need to be able to cope with high frequency triggers howvwer short. A \textit{Flancter} based counter is therefore used~\cite{bib:doulos-counter}. When
in the 20~MHz clock domain and passed to a \textit{fast counter} module. Indeed, at high frequencies it was found that internal counters need to be able to cope with high frequency triggers however short.
A so-callod \textit{Flancter}-based counter is therefore used~\cite{bib:doulos-counter}. When
a rising edge occurs on the pulse, the result of the counter is stored
to the channel pulse counter register. On v4 release of the gateware\footnotemark\footnotetext{On preceding releases, there was a single counter per channel, aggregating both types of pulses.}, there are two counters implemented separately for TTL
and BLO outputs of each channel (CHxTTLPCR and CHxBLOPCR -- see Appendix~\ref{app:conv-regs}).
......@@ -364,7 +366,7 @@ Figure~\ref{fig:pulse-cnt} presents the implementation for the TTL case only, th
blocking counter.
The pulse counter register can be written via the \textit{conv\_regs} component as a
result of an I$^2$C write access to the register's address.
result of an I$^2$C write access to the register's address. At this point, the fastcounter module needs to be reset by the external load command, otherwise, it will keep its old value.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/pulse-cnt}}
......@@ -526,7 +528,7 @@ When an output stage is sensitive to the pulse duty cycle, such as in the TTL to
blocking converter (CONV-TTL-BLO~\cite{conv-ttl-blo-ohwr}), the \textit{g\_pgen\_fixed\_width}
generic can be set to \textit{true} and this will synthesize a pulse generator
which outputs a pulse with a fixed width (\textit{g\_pgen\_pwidth}) and fixed
duty cycle (1/\textit{g\_pgen\_duty\_cycle\_div}).
period (\textit{g\_pgen\_pperiod}).
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/pulse-gen}}
......@@ -535,15 +537,10 @@ duty cycle (1/\textit{g\_pgen\_duty\_cycle\_div}).
In this latter case, a finite-state machine (FSM) handles pulse generation and rejection.
Its general operation is shown in Figure~\ref{fig:pulse-gen-operation}.
The operation of the pulse generator depends on whether the glitch filter is enabled.
If this is enabled, then the pulse is synchronized externally to the \textit{conv\_pulse\_gen}
block and it triggers the FSM directly. Alternatively, if the glitch filter is disabled, the
trigger
input starts the pulse (to avoid glitches on the leading edge) and then the pulse is synchronized
and the
FSM triggered to generate the fixed-width pulse. After the pulse width has been reached, the FSM
resets
the input flip-flop and goes into the rejection state.
The operation of the pulse generator is agnostic of whether the signal is de-glitched or not\footnotemark\footnotetext{This module has seen a complete redesign in comparison with the one used in release v3.0. This is because it had different signal paths for the asynchronous external trigger and the de-glitched version. This has made for a more complex logic, which the new module tries to simplify by using the same logic whether the signal is glitch-filtered or not} and
so is independent of whether it is synchronous (de-glitched) or asynchronous to the system clock.
After the pulse width has been reached, the FSM
resets the input flip-flop and goes into the rejection state.
If any pulses arrive either during the generation state, or the rejection state, the error output
is set high for one clock cycle. This type of error is identified as a \textit{flim\_err\_p}. It is the result of the maximum allowed frequency being reached.
......
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