Commit 467bc957 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag

Code further modified after review as was not behaving coorectly for very high…

Code further modified after review as was not behaving coorectly for very high frequencies with very small duty cycle
parent ccaffebc
......@@ -145,7 +145,7 @@ architecture behav of conv_pulse_gen is
-- duty cycle,
-- since the FSM needs to go through IDLE to accept a pulse
constant c_max_gen_gf_off : natural := g_pwidth-5;
constant c_max_rej_gf_off : natural := g_duty_cycle_div*g_pwidth - 5;
constant c_max_rej_gf_off : natural := g_duty_cycle_div*g_pwidth - 6;
constant c_max_gen_gf_on : natural := g_pwidth-1;
constant c_max_rej_gf_on : natural := g_duty_cycle_div*g_pwidth - 2;
......@@ -256,13 +256,14 @@ gen_with_fixed_pwidth : if (g_with_fixed_pwidth = true) generate
);
-- Trigger signal with glitch filter ON is input signal
trig_gf_on <= trig_a_i;
trig_gf_on <= '0' when rst_n_i = '0' else trig_a_i ;
-- Rising edge detector for the trigger signal when glitch filter is ON
p_trig_gf_on : process (clk_i) is
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
trig_gf_on_d0 <= '0';
trig_gf_on_r_edge_p <= '0';
else
......@@ -288,6 +289,7 @@ pulse_f_edge_p_o <= pulse_gf_off_f_edge_p when gf_en_n_i = '1' else trig_gf_on_f
pulse_gf_on <= '0';
pulse_cnt <= (others => '0');
pulse_err_p_o <= '0';
--first_p <= '1';
elsif (en_i = '1') then
-- State machine logic
case state is
......@@ -300,7 +302,7 @@ pulse_f_edge_p_o <= pulse_gf_off_f_edge_p when gf_en_n_i = '1' else trig_gf_on_f
when IDLE =>
pulse_cnt <= (others => '0');
pulse_gf_off_rst <= '0';
pulse_err_p_o <= '0';
pulse_err_p_o <= '0';
if (gf_en_n_i = '1') then
if (pulse_gf_off_r_edge_p = '1') then
state <= GEN_GF_OFF;
......@@ -310,10 +312,17 @@ pulse_f_edge_p_o <= pulse_gf_off_f_edge_p when gf_en_n_i = '1' else trig_gf_on_f
state <= GEN_GF_ON;
end if;
end if;
-- Pulse error assignment
-- This has been added for special cases whre rising edge occurs
-- on state transition
if (trig_gf_on_f_edge_p = '1' ) then
pulse_err_p_o <= '1';
end if;
---------------------------------------------------------------------
-- GEN_GF_OFFc
---------------------------------------------------------------------
-- GEN_GF_OFF
--------------------------c-------------------------------------------
-- Extend the generated pulse to the required pulse width.
---------------------------------------------------------------------
when GEN_GF_OFF =>
......@@ -325,14 +334,15 @@ pulse_f_edge_p_o <= pulse_gf_off_f_edge_p when gf_en_n_i = '1' else trig_gf_on_f
if c_max_gen_gf_off = 0 then
state <= REJ_GF_OFF;
state <= REJ_GF_OFF;
pulse_gf_off_rst <= '1';
end if;
-- Pulse error assignment
pulse_err_p_o <= '0';
if (trig_gf_on_r_edge_p = '1') then
if (trig_gf_on_r_edge_p = '1') then
pulse_err_p_o <= '1';
end if;
......@@ -343,19 +353,19 @@ pulse_f_edge_p_o <= pulse_gf_off_f_edge_p when gf_en_n_i = '1' else trig_gf_on_f
---------------------------------------------------------------------
when REJ_GF_OFF =>
-- Pulse logic and state change
pulse_gf_off_rst <= '1';
pulse_cnt <= pulse_cnt + 1;
if (pulse_cnt = c_max_rej_gf_off or c_max_rej_gf_off = 5) then -- second condition in
--the OR added to allow very short pulses of 250ns through
if pulse_cnt = c_max_rej_gf_off then
state <= IDLE;
end if;
pulse_gf_off_rst <= '0';
else
pulse_gf_off_rst <= '1';
end if;
-- Pulse error assignment
pulse_err_p_o <= '0';
if (trig_gf_on_r_edge_p = '1') then
pulse_err_p_o <= '1';
end if;
pulse_err_p_o <= '0';
if (trig_gf_on_r_edge_p = '1') then
pulse_err_p_o <= '1';
end if;
---------------------------------------------------------------------
-- GEN_GF_ON
---------------------------------------------------------------------
......
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