modified conv common so that the rest time is set from the top module or from the testbench

3c81af0f · Denia Bouhired-Ferrag · e65f9b5f · 3c81af0f · 3c81af0f
Commit 3c81af0f authored Mar 12, 2018 by Denia Bouhired-Ferrag
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Showing with 12 additions and 2 deletions

conv_common_gw.vhd top/conv_common_gw.vhd +8 -2

conv_common_gw_pkg.vhd top/conv_common_gw_pkg.vhd +4 -0

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--- a/top/conv_common_gw.vhd
+++ b/top/conv_common_gw.vhd
@@ -57,6 +57,10 @@ use work.conv_common_gw_pkg.all;
 entity conv_common_gw is
  generic
  (
+    -- Reduces some timeouts to speed up simulations
+    g_simul                : boolean := false;
+	-- Reset time: 50ns * 2 * (10**6) = 100 ms
+	g_rst_time			   : positive := 2*(10**6);		 
    -- Number of repeater channels
    g_nr_chans             : integer := 6;
    -- Number of inverter channels
@@ -314,6 +318,7 @@ architecture arch of conv_common_gw is
  signal rst_20_n            	: std_logic;
  signal rst_20            		: std_logic;
  signal rst_ext             	: std_logic;
+  signal rst_time               : positive := 10;
  -- Pulse logic signals
  signal trig_a              	: std_logic_vector(g_nr_chans-1 downto 0);
@@ -543,12 +548,13 @@ begin
  -- External reset input to reset generator
  rst_ext <= rst_fr_reg or (not vme_sysreset_n_i);
  -- Configure reset generator for 100ms reset
  cmp_reset_gen : conv_reset_gen
    generic map
    (
-  -- Reset time: 50ns * 2 * (10**6) = 100 ms
+      g_reset_time => g_rst_time 
-      g_reset_time => 2*(10**6) 
    )
    port map
    (

--- a/top/conv_common_gw_pkg.vhd
+++ b/top/conv_common_gw_pkg.vhd
@@ -71,6 +71,10 @@ package conv_common_gw_pkg is
  component conv_common_gw is
    generic
    (
+      -- Reduces some timeouts to speed up simulations
+      g_simul               : boolean := false;
+	  -- reset time
+	  g_rst_time			   : positive := 2*(10**6);	
      -- Number of repeater channels
      g_nr_chans            : integer := 6;
 	  g_nr_inv_chans        : integer := 4;