diff --git a/modules/conv_dyn_burst_ctrl.vhd b/modules/conv_dyn_burst_ctrl.vhd
index 122e1cb3e24bd2583dcafce822ff8a4b57098387..0758c0121b99e989d15a08247d519f5410ac3a58 100644
--- a/modules/conv_dyn_burst_ctrl.vhd
+++ b/modules/conv_dyn_burst_ctrl.vhd
@@ -93,6 +93,8 @@ entity conv_dyn_burst_ctrl is
 		pulse_r_edge_p_i	: in std_logic;
 		pulse_f_edge_p_i	: in std_logic;
 	
+	-- Temp_rise is output for external probing
+		temp_rise_o			: out unsigned (39 downto 0) ;
 	-- Dynamic temperature-controlled ouput pulse train.
 		pulse_burst_o		: out std_logic;
 	
@@ -133,7 +135,7 @@ entity conv_dyn_burst_ctrl is
 	-- Output from module depends on burst_ctrl_rst and en_i
 	---------------------------------------------------------
 		pulse_burst_o <= '0' when burst_ctrl_rst = '1' else pulse_burst_i and en_i;
-
+		temp_rise_o <= temp_rise;
 -----------------------------------------------------------------------------
 -- Finite State Machine FSM
 -----------------------------------------------------------------------------
@@ -168,7 +170,7 @@ entity conv_dyn_burst_ctrl is
 		when IDLE =>
 			if en_i = '1' and pulse_r_edge_p_i = '1' then
 					nxt_state 	<= PULSE_REPEAT;
-			 else
+			else
 					nxt_state 	<= IDLE; 
 			end if;
 		
@@ -191,7 +193,8 @@ entity conv_dyn_burst_ctrl is
 	-- i.e. temp_rise >= g_max_temp.
 	------------------------------------------------------------------------
 		when PULSE_REJECT =>
-			if pulse_f_edge_p_i = '1' and temp_rise <= g_max_temp then
+			if (pulse_f_edge_p_i = '1' and temp_rise <= g_max_temp) OR 
+				temp_rise = 0 then
 				nxt_state <= PULSE_REPEAT;
 			else
 				nxt_state <= PULSE_REJECT;
@@ -265,10 +268,10 @@ entity conv_dyn_burst_ctrl is
 		else
 			-- Reset counters in the event of a new pulse only 
 			-- when pulse rejection is not active
-			if (pulse_r_edge_p_i = '1') and burst_ctrl_rst = '0' then	
+			if (pulse_r_edge_p_i = '1' and burst_ctrl_rst = '0') then --OR
+			 --(pulse_f_edge_p_i = '1' and n_cycle_cnt /= 1) then
 				single_cycle_cnt <= 1;
 				n_cycle_cnt   <= 1;
-
 			else
 				--count clk cycles 
 				single_cycle_cnt <= single_cycle_cnt + 1;
@@ -305,7 +308,11 @@ entity conv_dyn_burst_ctrl is
 					end if;
 				end if;
 			elsif s_pulse_reject = '1' and temp_rise > 0 then
-				temp_rise <= temp_rise - to_unsigned(g_temp_decre_step(n_cycle_cnt-1), 40);
+				if temp_rise >= g_temp_decre_step(n_cycle_cnt-1) then
+					temp_rise <= temp_rise - to_unsigned(g_temp_decre_step(n_cycle_cnt-1), 40);
+				else
+					temp_rise <= (others => '0');
+				end if;
 			end if;
 		end if;
 	end if;