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Commit 2ff811dd authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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doc: Changed 'multicast switches' to 'other switches' 

This makes the doc and module more generic. The modification will be made in
the code as well.
parent 87d7325f
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doc/conv-common-gw.tex
View file @ 2ff811dd
...@@ -155,11 +155,54 @@ is accessible through an I$^2$C interface, and an I$^2$C to Wishbone bridge perf ...@@ -155,11 +155,54 @@ is accessible through an I$^2$C interface, and an I$^2$C to Wishbone bridge perf
the conversion between the two interfaces. the conversion between the two interfaces.
\begin{figure}[h] \begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/block-diagram}} \centerline{\includegraphics[width=1.1\textwidth]{fig/block-diagram}}
\caption{\label{fig:block-diagram} Block diagram of common gateware} \caption{\label{fig:block-diagram} Block diagram of common gateware}
\end{figure} \end{figure}
\textcolor{red}{\textbf{SWITCHES CONVENTION}} %------------------------------------------------------------------------------
% SUBSEC: Switches
%------------------------------------------------------------------------------
\subsection{Switches on converter boards}
Various converter boards may use various switches, so a convention should be made
about switch names and locations.
The CONV-TTL-BLO~\cite{conv-ttl-blo-ohwr}, which is the first converter project using
an FPGA, had eight switches which we called \textit{general-purpose switches}. These
appear on the CONV-TTL-RS485~\cite{conv-ttl-rs485-ohwr} as well. It is recommended to add
general-purpose switches on all converter boards in a similar manner to the two projects
mentioned above.
Additionally, the RS-485 pulse repeater adds four other switches, which are called MultiCast switches
and despite their seemingly dedicated name, they are also general-purpose switches at the
time of writing of this document. Therefore, they are considered as \textit{other switches},
due to the fact they do not appear on the CONV-TTL-BLO.
The state of the general-purpose switches can be read from the status register
(SR -- see Appendix~\ref{app:conv-regs-sr}), and the state of the MultiCast
switches can be read from the other switches register (OSWR -- see Appendix~\ref{app:conv-regs-oswr}).
A total of 32 dedicated switches can be implemented on converter boards and mapped to the OSWR, should
they be required. This number-of-32 constraint is imposed by the number of bits in the OSWR.
Table~\ref{tbl:switches} summarizes the switches on converter boards.
\begin{table}[h]
\caption{\label{tbl:switches} Switches on converter boards}
\rowcolors{2}{white}{gray!25}
\centerline {
\begin{tabular}{l p{.7\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Name}} & \multicolumn{1}{c}{\textbf{Comments}} \\
\hline
General-purpose & Eight switches that \textit{should} be implemented on all converter boards.
Read their state from the SR.SWITCHES field (see Appendix~\ref{app:conv-regs-sr}) \\
Other & Dedicated switches for specific converter boards.
Read their state from the OSWR register \newline
(see Appendix~\ref{app:conv-regs-oswr}) \\
\hline
\end{tabular}
}
\end{table}
%============================================================================== %==============================================================================
% SEC: Clocking % SEC: Clocking
...@@ -194,7 +237,7 @@ Table~\ref{tbl:clocks} lists the clock domains used in the gateware. ...@@ -194,7 +237,7 @@ Table~\ref{tbl:clocks} lists the clock domains used in the gateware.
\textbf{Clock domain} & \textbf{Frequency} & \multicolumn{1}{c}{\textbf{Comments}} \\ \textbf{Clock domain} & \textbf{Frequency} & \multicolumn{1}{c}{\textbf{Comments}} \\
\hline \hline
\textit{clk\_20\_i} & 20~MHz & Clock input to most of the sequential logic \\ \textit{clk\_20\_i} & 20~MHz & Clock input to most of the sequential logic \\
% \textit{clk\_125} & 125~MHz & Time-tagging logic and WR reference clock \\ \textit{clk\_125} & 125~MHz & Time-tagging logic and WR reference clock \\
\hline \hline
\end{tabular} \end{tabular}
} }
...@@ -399,18 +442,18 @@ Finally, the \textit{g\_board\_id} and \textit{g\_gwvers} generics connect to re ...@@ -399,18 +442,18 @@ Finally, the \textit{g\_board\_id} and \textit{g\_gwvers} generics connect to re
\caption{\label{tbl:conv-regs-ext-inputs} Active-high inputs to converter board registers from external logic} \caption{\label{tbl:conv-regs-ext-inputs} Active-high inputs to converter board registers from external logic}
\rowcolors{2}{white}{gray!25} \rowcolors{2}{white}{gray!25}
\centerline { \centerline {
\begin{tabular}{l l p{.45\textwidth}} \begin{tabular}{l l p{.5\textwidth}}
\hline \hline
\multicolumn{1}{c}{\textbf{Input port}} & \multicolumn{1}{c}{\textbf{Register}} & \multicolumn{1}{c}{\textbf{Description}} \\ \multicolumn{1}{c}{\textbf{Input port}} & \multicolumn{1}{c}{\textbf{Register}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline \hline
sw\_gp\_i & SR.SWITCHES & General-purpose switch status \\ sw\_gp\_i & SR.SWITCHES & General-purpose switch state \\
rtmm\_i & SR.RTM[2:0] & RTM Motherboard detection lines \\ rtmm\_i & SR.RTM[2:0] & RTM Motherboard detection lines \\
rtmp\_i & SR.RTM[5:3] & RTM Piggyback detection lines \\ rtmp\_i & SR.RTM[5:3] & RTM Piggyback detection lines \\
line\_front\_i & LSR.FRONT & State of front-panel channel lines at FPGA input \\ line\_front\_i & LSR.FRONT & State of front-panel channel lines at FPGA input \\
line\_inv\_i & LSR.FRONTINV & State of front-panel general-purpose inverter channels at FPGA input \\ line\_inv\_i & LSR.FRONTINV & State of front-panel general-purpose inverter channels at FPGA input \\
line\_rear\_i & LSR.REAR & State of rear-panel channel lines at FPGA input \\ line\_rear\_i & LSR.REAR & State of rear-panel channel lines at FPGA input \\
line\_rear\_fs\_i & LSR.REARFS & State of fail-safe rear-panel inputs (whether a cable is plugged in or not) \\ line\_rear\_fs\_i & LSR.REARFS & State of fail-safe rear-panel inputs (whether a cable is plugged in or not) \\
sw\_multicast\_i & MSWR & Multicast switches, connected to Multicast Switch Register \\ sw\_other\_i & OSWR & State of other on-board switches \\
\hline \hline
\end{tabular} \end{tabular}
} }
......
doc/conv-regs.tex
View file @ 2ff811dd
...@@ -52,7 +52,7 @@ Base address: 0x000 ...@@ -52,7 +52,7 @@ Base address: 0x000
0x80 & 0x00000000 & CH6LTSTLR & Channel 6 Latest Timestamp TAI Low Register\\ 0x80 & 0x00000000 & CH6LTSTLR & Channel 6 Latest Timestamp TAI Low Register\\
0x84 & 0x00000000 & CH6LTSTHR & Channel 6 Latest Timestamp TAI High Register\\ 0x84 & 0x00000000 & CH6LTSTHR & Channel 6 Latest Timestamp TAI High Register\\
0x88 & (2) & LSR & Line Status Register\\ 0x88 & (2) & LSR & Line Status Register\\
0x8c & 0x00000000 & MSWR & Multicast Switch Register\\ 0x8c & 0x00000000 & OSWR & Other Switches Register\\
\end{longtable} \end{longtable}
} }
...@@ -1575,8 +1575,8 @@ High if line is in failsafe mode (no cable plugged in)\\ Bit 0 -- channel 1 ...@@ -1575,8 +1575,8 @@ High if line is in failsafe mode (no cable plugged in)\\ Bit 0 -- channel 1
\vspace{11pt} \vspace{11pt}
\pagebreak \pagebreak
\subsubsection{MSWR -- Multicast Switch Register} \subsubsection{OSWR -- Other Switches Register}
\label{app:conv-regs-mswr} \label{app:conv-regs-oswr}
\vspace{11pt} \vspace{11pt}
\noindent \noindent
...@@ -1584,19 +1584,19 @@ High if line is in failsafe mode (no cable plugged in)\\ Bit 0 -- channel 1 ...@@ -1584,19 +1584,19 @@ High if line is in failsafe mode (no cable plugged in)\\ Bit 0 -- channel 1
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} } \begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\ 31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline \hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\ \multicolumn{8}{|c|}{\cellcolor{gray!25}SWITCHES[31:24]}\\
\hline \hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\ 23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline \hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\ \multicolumn{8}{|c|}{\cellcolor{gray!25}SWITCHES[23:16]}\\
\hline \hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\ 15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline \hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\ \multicolumn{8}{|c|}{\cellcolor{gray!25}SWITCHES[15:8]}\\
\hline \hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\ 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline \hline
\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}SWITCHES[3:0]}\\ \multicolumn{8}{|c|}{\cellcolor{gray!25}SWITCHES[7:0]}\\
\hline \hline
\end{tabular} \end{tabular}
} }
...@@ -1605,7 +1605,7 @@ High if line is in failsafe mode (no cable plugged in)\\ Bit 0 -- channel 1 ...@@ -1605,7 +1605,7 @@ High if line is in failsafe mode (no cable plugged in)\\ Bit 0 -- channel 1
\item \begin{small} \item \begin{small}
{\bf {\bf
SWITCHES SWITCHES
} [\emph{read-only}]: Multicast address (from switch) } [\emph{read-only}]: Switch state
\\ \\
1 -- switch is ON \\ 0 -- switch is OFF 1 -- switch is ON \\ 0 -- switch is OFF
\end{small} \end{small}
......
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