Commit 223396a3 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

Added module documentation

parent aa091233
FILE=conv-common-gw
all:
$(MAKE) -C fig
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
bibtex $(FILE).aux
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
evince $(FILE).pdf &
clean:
$(MAKE) -C fig clean
rm -rf *.aux *.dvi *.log $(FILE).pdf *.lof *.lot *.out *.toc *.bbl *.blg *.gz
Type 'make' to create your .pdf documentation file.
You need Inkscape to make the documentation files:
sudo apt-get install inkscape
\ No newline at end of file
\begin{titlepage}
\vspace*{3cm}
%---------------------------------------------------------------
% name
%---------------------------------------------------------------
\noindent{\LARGE \textbf{Converter board common gateware}}
\noindent \rule{\textwidth}{.1cm}
\hfill August 5, 2014
\vspace*{3cm}
\begin{figure}[h]
\includegraphics[height=3cm]{fig/cern-logo}
\hfill
\includegraphics[height=3cm]{fig/ohwr-logo}
\end{figure}
\vfill
%---------------------------------------------------------------
% name
%---------------------------------------------------------------
\noindent {\Large \textbf{Theodor-Adrian Stana (CERN/BE-CO-HT)}}
\noindent \rule{\textwidth}{.05cm}
\end{titlepage}
@misc{coding-guidelines,
author = "Patrick Loschmidt and Nata{\v s}a Simani\'c and C\'esar Prados and Pablo Alvarez and Javier Serrano",
title = {{Guidelines for VHDL Coding}},
month = 04,
year = 2011,
note = {\url{http://www.ohwr.org/documents/24}}
}
@misc{level-conversion,
title = {{Level Conversion Circuits}},
note = {\url{http://www.ohwr.org/projects/level-conversion/wiki}}
}
@misc{conv-common-gw-git,
title = {{Repository for converter board common gateware}},
note = {\url{http://www.ohwr.org/projects/conv-common-gw/repository}}
}
@misc{board-id,
title = {{Board IDs for level conversion circuits}},
note = {\url{http://www.ohwr.org/projects/conv-common-gw/wiki/Board-id}}
}
@misc{conv-ttl-blo-ohwr,
title = {{Conv TTL Blocking Project Page on OHWR}},
howpublished = {\url{http://www.ohwr.org/projects/conv-ttl-blo}}
}
@misc{conv-ttl-rs485-ohwr,
title = {{Conv TTL Blocking Project Page on OHWR}},
howpublished = {\url{http://www.ohwr.org/projects/conv-ttl-rs485}}
}
@misc{sdb,
title = {{SDB specification v1.1}},
howpublished = {\url{http://www.ohwr.org/documents/256}}
}
@misc{gencores-ohwr,
title = {{Platform-independent Core Collection webage on Open Hardware Repository}},
howpublished = {\url{http://www.ohwr.org/projects/general-cores/wiki}}
}
%==============================================================================
% Document header
%==============================================================================
\documentclass[a4paper,11pt]{article}
% Color package
\usepackage[usenames,dvipsnames,table]{xcolor}
% Hyperrefs
\usepackage[
colorlinks = true,
linkcolor = Mahogany,
citecolor = Mahogany,
urlcolor = blue,
]{hyperref}
% Longtable
\usepackage{longtable}
% Graphics, multirow
\usepackage{graphicx}
\usepackage{multirow}
% Appendix package
\usepackage[toc,page]{appendix}
\usepackage{fancyhdr}
\setlength{\headheight}{15.2pt}
\pagestyle{fancy}
\fancyhead[L]{\nouppercase{\leftmark}}
\fancyhead[R]{}
\renewcommand{\footrulewidth}{0.4pt}
% Row number command
\newcounter{rownr}
\newcommand{\rownumber}{\stepcounter{rownr}\arabic{rownr}}
%==============================================================================
% Start of document
%==============================================================================
\begin{document}
%------------------------------------------------------------------------------
% Title
%------------------------------------------------------------------------------
\include{cern-title}
%------------------------------------------------------------------------------
% Revision history
%------------------------------------------------------------------------------
\thispagestyle{empty}
\section*{Revision history}
\centerline
{
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l c p{.6\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Date}} & \multicolumn{1}{c}{\textbf{Version}} & \multicolumn{1}{c}{\textbf{Change}} \\
\hline
05-08-2014 & 0.1 & First draft \\
\hline
\end{tabular}
}
\pagebreak
\pagenumbering{roman}
\setcounter{page}{1}
\tableofcontents
%------------------------------------------------------------------------------
% List of figs, tables
%------------------------------------------------------------------------------
\listoffigures
\listoftables
%------------------------------------------------------------------------------
% List of abbreviations
%------------------------------------------------------------------------------
\pagebreak
\section*{List of Abbreviations}
\begin{tabular}{l l}
CR & Control Register \\
FPGA & Field-Programmable Gate Array \\
LSR & Line Status Register \\
MSWR & Multicast Switch Register \\
SR & Status Register \\
\end{tabular}
\pagebreak
\pagenumbering{arabic}
\setcounter{page}{1}
%==============================================================================
% SEC: Intro
%==============================================================================
\section{Introduction}
\label{sec:intro}
This document presents the common gateware for converter board projects~\cite{level-conversion}.
This gateware, mainly written in VHDL, is a grouping of modules common to all converter board projects.
A synthesized version thereof is intended to be downloaded to the FPGA on the converter board.
No specific FPGA is assumed for the converter boards, therefore the VHDL code is as generic as possible.
However, some details about the way that the boars are designed in the Hardware \& Timing section at CERN
are assumed, and these details are described throughout the document.
The document will start with a summary of the VHDL entity's ports, continue with presenting
a top-level diagram of the gateware, followed by a high-level description of each module in the gateware.
More involved details can be obtained by consulting the code itself, which can be freely obtained (including
the \textit{general-cores}) submodule from the \textit{git} repository~\cite{conv-common-gw-git} using the
following commands:
\begin{small}
\begin{verbatim}
git clone git://ohwr.org/level-conversion/conv-common-gw.git
git submodule init
git submodule update
\end{verbatim}
\end{small}
%==============================================================================
% SEC: Instantiation
%==============================================================================
\pagebreak
\section{Instantiation}
\label{sec:instantiation}
To use the common gateware, the designer should instantiate the module \textit{conv\_common\_gw},
which is part of the repository and contains all sub-modules required to implement
the pulse repetition functionality.
A corresponding VHDL component declaration can be found in the associated package file
(\textit{conv\_common\_gw\_pkg.vhd}), which needs to be imported into the file of the
instantiating module.
Port names follow the OHWR coding style guide~\cite{coding-guidelines}. Except for few cases,
the module uses active-high ports, any adaptations to active-low logic must be made in external logic.
Since there are a lot of ports in the component, listing them all here would be a waste of space.
The reader is referred to the package file or the source file directly, where each port declaration
is commented. Projects where this gateware is already used (e.g., CONV-TTL-RS485~\cite{conv-ttl-rs485-ohwr}) can also be a
good source of reference.
The module's generics are listed here for quick reference (Table~\ref{tbl:generics}).
\begin{table}[h]
\caption{\label{tbl:generics} Generics of \textit{conv\_common\_gw}}
\rowcolors{2}{white}{gray!25}
\centerline{
\begin{tabular}{p{.3\textwidth} p{.7\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Name}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
g\_nr\_chans & Number of pulse repetition channels \newline
Max. 6 channels allowed \\
g\_board\_id & Board ID, per the converter board ID page~\cite{board-id} \newline
Connects to BID register \\
g\_gwvers & Current gateware version \newline
Connects to GWVERS field in SR \\
g\_pgen\_fixed\_width & Pulse generator with fixed width at output \newline
\textit{true} -- fixed-width output pulse and pulse rejection after pulse is generated \newline
\textit{false} -- pulse generator is simple pass-through \\
g\_pgen\_pwidth & Pulse width at generator output \newline
Value in number of \textit{clk\_20\_i} cycles \newline
Constrained between 20 and 40 \textit{clk\_20\_i} cycles \newline
No effect if \textit{g\_pgen\_fixed\_width} is \textit{false} \\
g\_pgen\_duty\_cycle\_div & Divider ratio of pulse rejection mechanism \newline
Output max. freq. 1/g\_pgen\_duty\_cycle\_div \newline
No effect if \textit{g\_pgen\_fixed\_width} is \textit{false} \\
g\_pgen\_gf\_len & Pulse generation mechanism glitch filter length in number of \textit{clk\_20\_i} cycles \\
g\_bicolor\_led\_columns & Number of columns for bicolor LED controller \\
g\_bicolor\_led\_lines & Number of lines for bicolor LED controller \\
\hline
\end{tabular}
}
\end{table}
%==============================================================================
% SEC: Top-level diagram
%==============================================================================
\pagebreak
\section{Overview}
\label{sec:overview}
The common gateware comprises various modules, as shown in Figure~\ref{fig:block-diagram}.
The channel logic, presented in Section~\ref{sec:chan-logic}, is multiplied \textit{g\_nr\_chans} times.
Its status and select functionality can be controlled via the controller board
registers (Section~\ref{subsec:conv-regs}), which are part of a Wishbone memory-mapped
peripheral. This peripheral, along with the rest of the memory-mapped peripherals on converter boards,
is accessible through an I$^2$C interface, and an I$^2$C to Wishbone bridge performs
the conversion between the two interfaces.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/block-diagram}}
\caption{\label{fig:block-diagram} Block diagram of common gateware}
\end{figure}
%==============================================================================
% SEC: Clocking
%==============================================================================
\pagebreak
\section{Clocks}
\label{sec:clocks}
There are two clock signals input to the FPGA (Figure~\ref{fig:clocks}).
The first is a 20~MHz signal from a VCXO. The second clock signal with a frequency
of 125~MHz is generated on-board via a Texas Instruments PLL IC from a 25~MHz VCXO.
Two DACs are provided on-board for controlling the two VCXOs. The DACs can be
controlled via SPI, and if White Rabbit is available, the White Rabbit PTP Core (WRPC)
can control these DACs to discipline these clocks.
Table~\ref{tbl:clocks} lists the clock domains used in the gateware.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/clocks}}
\caption{FPGA clock inputs}
\label{fig:clocks}
\end{figure}
\begin{table}[h]
\caption{\label{tbl:clocks} Clock domains}
\rowcolors{2}{white}{gray!25}
\centerline
{
\begin{tabular}{c c p{.6\textwidth}}
\hline
\textbf{Clock domain} & \textbf{Frequency} & \multicolumn{1}{c}{\textbf{Comments}} \\
\hline
\textit{clk\_20\_i} & 20~MHz & Clock input to most of the sequential logic \\
% \textit{clk\_125} & 125~MHz & Time-tagging logic and WR reference clock \\
\hline
\end{tabular}
}
\end{table}
%==============================================================================
% SEC: Reset
%==============================================================================
\pagebreak
\section{Reset}
\label{sec:reset}
An internal reset generator (\textit{conv\_reset\_gen}) is used to supply a reset pulse to the sequential
modules of the \textit{conv\_common\_gw}, so that they start up in a known state.
This reset pulse occurs either when the FPGA finishes configuration and goes into user mode, or when
an external reset is received via the control register (CR) in the converter board registers component.
To be able to issue an external reset, the reset bit in the CR must be unlocked via the reset
unlock bit.
The \textit{conv\_reset\_gen} component is clocked from \textit{clk\_20\_i}, so the reset
it generates is in the 20~MHz clock domain. This is also the reset that is present at the
\textit{rst\_n\_o} pin.
%A reset synchronized to the 125~MHz clock domain is generated
%inside \textit{conv\_common\_gw}, but this is not provided at the output.
Note that the VHDL of this module is Xilinx and XST-specific and porting to a different
FPGA architecture or synthesis tool is not guaranteed to provide the same results.
The \textit{conv\_reset\_gen} module has an initial value set for the counter signal after
power-up, which is guaranteed by XST to be set after the FPGA's GSR signal is de-asserted.
By default, the reset time is set to 100~ms.
%==============================================================================
% SEC: Channel logic
%==============================================================================
\pagebreak
\section{Channel logic}
\label{sec:chan-logic}
The channel logic is presented in Figure~\ref{fig:chan-logic}. The central part
thereof is a pulse generator which can be configured for pass-through mode, or
fixed-width pulse generation with subsequent pulse rejection after a pulse has
been generated. The generator is triggered by the pulse input, which can be fed
directly to the generator's input, or optionally glitch filtered, by a switch
on the converter board. The output of this pulse generator triggers lighting a pulse LED,
apart from driving the pulse output of the module.
\begin{figure}[b]
\centerline{\includegraphics[width=\textwidth]{fig/chan-logic}}
\caption{\label{fig:chan-logic} Channel logic diagram}
\end{figure}
%------------------------------------------------------------------------------
\subsection{Output enable}
\label{subsec:oen}
%------------------------------------------------------------------------------
Converter board outputs have to be enabled prior to being used. Within the
\textit{conv\_common\_gw}, there are four output enables. Apart from the global
channel output enable, there are dedicated output enables for potential front
and rear panel connections (see the converter board's specific user guide for information
on front and rear panels).
To make sure that pulses are output only when the FPGA can handle them, the global
output enable is set only after the reset period is finished. The rest of the
output enables are set one clock cycle later. This in combination with the
rest of the circuitry outside the FPGA makes sure no glitches or erroneous pulses
are output during the internal reset period.
An example connection of the output enables on the CONV-TTL-RS485~\cite{conv-ttl-rs485-ohwr} is shown in
Figure~\ref{fig:outp-enable}.
\begin{figure}
\centerline{\includegraphics[width=\textwidth]{fig/outp-enable}}
\caption{\label{fig:outp-enable} Output enable example}
\end{figure}
%------------------------------------------------------------------------------
\subsection{Glitch filter}
\label{subsec:glitch-filt}
%------------------------------------------------------------------------------
The glitch filter input (\textit{gf\_en\_n\_i}) is intended to be enabled via one
of the general-purpose switches on the converter board when the environment where
the board is placed is hazardouse and can potentially create harmful glitches on the
line. It is active-low, therefore a '0' on the pin enables the glitch filter.
The length of the glitch filter can be selected at top-level via the generic
\textit{g\_pgen\_glitch\_filt\_len}, which is in measures of \textit{clk\_20\_i} cycles.
For information on the module's implementation, consult its documentation in the
\textit{ip\_cores/general-cores/doc/} folder.
%------------------------------------------------------------------------------
\subsection{Pulse generator}
\label{subsec:pulse-gen}
%------------------------------------------------------------------------------
Figure~\ref{fig:pulse-gen} shows the implementation of the pulse generator (\textit{conv\_pulse\_gen})
block. When \textit{g\_pgen\_fixed\_width} is \textit{false},
the pulse generator is a simple pass-through. This is usable in converter boards
such as the CONV-TTL-RS485~\cite{conv-ttl-rs485-ohwr}, where the RS-485 outputs are not sensitive to the
duty cycle of the outputs pulses, and which can also be used to distribute
timing information.
When an output stage is sensitive to the pulse duty cycle, such as in the TTL to
blocking converter (CONV-TTL-BLO~\cite{conv-ttl-blo-ohwr}), the \textit{g\_pgen\_fixed\_width}
generic can be set to \textit{true} and this will synthesize a pulse generator
which outputs a pulse with a fixed width (\textit{g\_pgen\_pwidth}) and fixed
duty cycle (1/\textit{g\_pgen\_duty\_cycle\_div}).
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/pulse-gen}}
\caption{\label{fig:pulse-gen} Pulse generator block}
\end{figure}
In this latter case, a finite-state machine (FSM) handles pulse generation and rejection.
Its general operation is shown in
The operation of the pulse generator depends on whether the glitch filter is enabled.
If it is, then the pulse is assumed to be synchronized externally to the \textit{conv\_pulse\_gen}
block and it trigger input triggers the FSM directly. Alternatively, if the glitch filter
is disabled, the trigger input starts the pulse (to avoid glitches on the leading edge)
and then the pulse is synchronized and the FSM triggered to generate the fixed-width pulse.
After the pulse width has been reached, the FSM resets the input flip-flop and goes into the
rejection state.
\begin{figure}
\centerline{\includegraphics[width=\textwidth]{fig/pulse-gen-operation}}
\caption{\label{fig:pulse-gen-operation} Pulse generator operation}
\end{figure}
%------------------------------------------------------------------------------
\subsection{Pulse LED control}
\label{subsec:pulse-led}
%------------------------------------------------------------------------------
A rising edge on the \textit{pulse\_o} signal from the \textit{conv\_pulse\_gen}
block generates a 26-ms active-high pulse signal on the \textit{led\_pulse\_o} port of
\textit{conv\_common\_gw}. This port should be connected to the channel's pulse LED output.
%==============================================================================
% SEC: Memory-mapped peripherals
%==============================================================================
\pagebreak
\section{Memory-mapped peripherals}
\label{sec:memmapped-periphs}
Various memory-mapped peripherals are implemented within \textit{conv\_common\_gw},
as seen below. They are interfaced to a Wishbone interconnect, which is SDB-enabled~\cite{sdb},
granted to the \textit{xwb\_sdb\_crossbar} module used to connect the slaves to the
master.
%==============================================================================
\subsection{I$^2$C to Wishbone bridge}
\label{subsec:i2c-bridge}
%==============================================================================
The Wishbone master in the interconnect is an I$^2$C to Wishbone bridge (\textit{wb\_i2c\_bridge} from
the \textit{general-cores} library~\cite{gencores-ohwr}), which implements the protocol
defined together with ELMA for communication via the serial lines on the VME P1 connector.
Details about this protocol, as well as implementation details for \textit{wb\_i2c\_bridge} can be
found in the module's documentation under the \textit{general-cores/doc/} folder.
Upon instantiating the \textit{wb\_i2c\_bridge} inside \textit{conv\_common\_gw}, the
module's watchdog timeout generic (\textit{g\_fsm\_wdt}) is set such that the watchdog
times out in 24~ms. This value is explained in comments inside the code, as well as
in the appendix to the \textit{wb\_i2c\_bridge} module's documentation.
When an I$^2$C transfer takes place according to the defined protocol, the \textit{led\_i2c\_o}
output strobes four times. This output should be connected to a bicolor LED of choice
for signaling communication.
%==============================================================================
\subsection{Converter board registers}
\label{subsec:conv-regs}
%==============================================================================
The \textit{conv\_regs} module contains various Wishbone-addressable registers that contain status information,
as well as select control functionality.
It is the module which constrains \textit{conv\_common\_gw} to a maximum of six
pulse repetition channels, due to need of compatibility with previously-released
implementations of the \textit{conv\_regs} memory map.
Some of the bits in the converter board registers are set from inside the \textit{conv\_common\_gw}
module, but some are status bits that should be connected to external logic. Most of the bits implemented
as part of \textit{conv\_regs} are intended to be active-high logic, so adaptations for this should be made
in logic external to the \textit{conv\_common\_gw} when an external connection is needed.
The inputs that connect to bits in the status register are shown in Table~\ref{tbl:conv-regs-ext-inputs}.
Should some of these inputs not be used, such as for example the failsafe lines in the case of CONV-TTL-BLO~\cite{conv-ttl-blo-ohwr},
the corresponding lines should be connected to all-zeroes.
Finally, the \textit{g\_board\_id} and \textit{g\_gwvers} generics connect to registers in
\textit{conv\_regs} as shown in Figure~\ref{fig:bidr-gwvers}.
\begin{table}[h]
\caption{\label{tbl:conv-regs-ext-inputs} Active-high inputs to converter board registers from external logic}
\rowcolors{2}{white}{gray!25}
\centerline {
\begin{tabular}{l l p{.45\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Input port}} & \multicolumn{1}{c}{\textbf{Register}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
sw\_gp\_i & SR.SWITCHES & General-purpose switch status \\
rtmm\_i & SR.RTM[2:0] & RTM Motherboard detection lines \\
rtmp\_i & SR.RTM[5:3] & RTM Piggyback detection lines \\
line\_front\_i & LSR.FRONT & State of front-panel channel lines at FPGA input \\
line\_inv\_i & LSR.FRONTINV & State of front-panel general-purpose inverter channels at FPGA input \\
line\_rear\_i & LSR.REAR & State of rear-panel channel lines at FPGA input \\
line\_rear\_fs\_i & LSR.REARFS & State of fail-safe rear-panel inputs (whether a cable is plugged in or not) \\
sw\_multicast\_i & MSWR & Multicast switches, connected to Multicast Switch Register \\
\hline
\end{tabular}
}
\end{table}
\begin{figure}[h]
\centerline{\includegraphics[width=.7\textwidth]{fig/bidr-gwvers}}
\caption{\label{fig:bidr-gwvers} BIDR and SR.GWVERS connections}
\end{figure}
%==============================================================================
\subsection{MultiBoot}
\label{subsec:multiboot}
%==============================================================================
The \textit{xwb\_xil\_multiboot} module from the \textit{general-cores} library~\cite{gencores-ohwr}
is used to provide MultiBoot functionality via I$^2$C. To find out more about the
module and how to use it, consult its documentation under the \textit{general-cores/doc/} folder.
%==============================================================================
% Appendices
%==============================================================================
\pagebreak
\begin{appendices}
%==============================================================================
% APP: Memmap
%==============================================================================
\section{Memory map}
\label{app:memmap}
Table~\ref{tbl:memmap} shows the maximum memory map obtainable with the \textit{conv\_common\_gw}
module. This is obtained when the \textit{g\_nr\_chans} generic is set to the maximum value of
\textit{6}. Should less channels be desired, the higher-numbered registers for the channels
(e.g., CH5PCR and CH6PCR for \textit{g\_nr\_chans = 4}) can be considered as \textit{Reserved}
(read out as 0).
The following sections list the memory map of each peripheral.
\begin{table}[h]
\caption{\textit{conv\_common\_gw} memory map}
\label{tbl:memmap}
\centerline
{
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l l l p{.4\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Peripheral}} & \multicolumn{2}{c}{\textbf{Address range}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
Board registers & 0x000 & 0x0ff & Coverter board registers \\
MultiBoot & 0x100 & 0x110 & MultiBoot module \\
\hline
\end{tabular}
}
\end{table}
%%------------------------------------------------------------------------------
%% SUBSEC: conv_regs
%%------------------------------------------------------------------------------
\include{conv-regs}
%------------------------------------------------------------------------------
% SUBSEC: MultiBoot
%------------------------------------------------------------------------------
\include{multiboot-regs}
%==============================================================================
\end{appendices}
%==============================================================================
%==============================================================================
% Bibliography
%==============================================================================
\pagebreak
\bibliographystyle{ieeetr}
\bibliography{conv-common-gw}
\end{document}
\subsection{Converter board registers}
\label{subsec:wbgen:reg}
Base address: 0x00000000
{
\rowcolors{2}{white}{gray!25}
\begin{longtable}{l l l p{.5\textwidth}}
\hline
\textbf{Offset} & \textbf{Reset} & \textbf{Name}
& \textbf{Description} \\
\hline
\endfirsthead
\hline
\hline
\endhead
\hline
\endfoot
0x0 & 0x54424c4f & BIDR & Board ID Register\\
0x4 & (1) & SR & Status Register\\
0x8 & 0x00000000 & CR & Control Register\\
0xc & 0x00000000 & CH1PCR & Channel 1 Pulse Counter Register\\
0x10 & 0x00000000 & CH2PCR & Channel 2 Pulse Counter Register\\
0x14 & 0x00000000 & CH3PCR & Channel 3 Pulse Counter Register\\
0x18 & 0x00000000 & CH4PCR & Channel 4 Pulse Counter Register\\
0x1c & 0x00000000 & CH5PCR & Channel 5 Pulse Counter Register\\
0x20 & 0x00000000 & CH6PCR & Channel 6 Pulse Counter Register\\
0x24 & 0x00000000 & TVLR & Time Value Low Register\\
0x28 & 0x00000000 & TVHR & Time Value High Register\\
0x2c & 0x00000000 & TBMR & Tag Buffer Meta Register\\
0x30 & 0x00000000 & TBCYR & Tag Buffer Cycles Register\\
0x34 & 0x00000000 & TBTLR & Tag Buffer TAI Low Register\\
0x38 & 0x00000000 & TBTHR & Tag Buffer TAI High Register\\
0x3c & 0x00000000 & TBCSR & Tag Buffer Control and Status Register\\
0x40 & 0x00000000 & CH1LTSCYR & Channel 1 Latest Timestamp Cycles Register\\
0x44 & 0x00000000 & CH1LTSTLR & Channel 1 Latest Timestamp TAI Low Register\\
0x48 & 0x00000000 & CH1LTSTHR & Channel 1 Latest Timestamp TAI High Register\\
0x4c & 0x00000000 & CH2LTSCYR & Channel 2 Latest Timestamp Cycles Register\\
0x50 & 0x00000000 & CH2LTSTLR & Channel 2 Latest Timestamp TAI Low Register\\
0x54 & 0x00000000 & CH2LTSTHR & Channel 2 Latest Timestamp TAI High Register\\
0x58 & 0x00000000 & CH3LTSCYR & Channel 3 Latest Timestamp Cycles Register\\
0x5c & 0x00000000 & CH3LTSTLR & Channel 3 Latest Timestamp TAI Low Register\\
0x60 & 0x00000000 & CH3LTSTHR & Channel 3 Latest Timestamp TAI High Register\\
0x64 & 0x00000000 & CH4LTSCYR & Channel 4 Latest Timestamp Cycles Register\\
0x68 & 0x00000000 & CH4LTSTLR & Channel 4 Latest Timestamp TAI Low Register\\
0x6c & 0x00000000 & CH4LTSTHR & Channel 4 Latest Timestamp TAI High Register\\
0x70 & 0x00000000 & CH5LTSCYR & Channel 5 Latest Timestamp Cycles Register\\
0x74 & 0x00000000 & CH5LTSTLR & Channel 5 Latest Timestamp TAI Low Register\\
0x78 & 0x00000000 & CH5LTSTHR & Channel 5 Latest Timestamp TAI High Register\\
0x7c & 0x00000000 & CH6LTSCYR & Channel 6 Latest Timestamp Cycles Register\\
0x80 & 0x00000000 & CH6LTSTLR & Channel 6 Latest Timestamp TAI Low Register\\
0x84 & 0x00000000 & CH6LTSTHR & Channel 6 Latest Timestamp TAI High Register\\
0x88 & 0x00000000 & LSR & Line Status Register\\
0x8c & 0x00000000 & MSWR & Multicast Switch Register\\
\end{longtable}
}
\noindent Note (1): The reset value of the SR cannot be specified, since it is based on the
gateware version, the state of the on-board switches and whether an RTM is plugged in or not.
\vspace{11pt}
\subsubsection{BIDR -- Board ID Register}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BIDR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BIDR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BIDR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BIDR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
BIDR
} [\emph{read-only}]: ID register bits
\\
Reset value: 0x54424c4f
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{SR -- Status Register}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}PMISSE} & \multicolumn{1}{|c|}{\cellcolor{gray!25}I2C\_ERR}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c|}{\cellcolor{gray!25}WRPRES} & \multicolumn{1}{|c|}{\cellcolor{gray!25}I2C\_WDTO} & \multicolumn{6}{|c|}{\cellcolor{gray!25}RTM[5:0]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}SWITCHES[7:0]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}GWVERS[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
GWVERS
} [\emph{read-only}]: Gateware version
\\
Leftmost nibble hex value is major release decimal value \\ Rightmost nibble hex value is minor release decimal value \\ e.g. \\ 0x11 -- v1.1 \\ 0x2e -- v2.14
\end{small}
\item \begin{small}
{\bf
SWITCHES
} [\emph{read-only}]: Status of on-board switches
\\
0 -- switch is ON \\ 1 -- switch is OFF
\end{small}
\item \begin{small}
{\bf
RTM
} [\emph{read-only}]: RTM detection lines~\cite{rtm-det}
\\
0 -- line active \\ 1 -- line inactive
\end{small}
\item \begin{small}
{\bf
I2C\_WDTO
} [\emph{read/write}]: I2C communication watchdog timeout error
\\
1 -- timeout occured \\ 0 -- no timeout \\ This bit can be cleared by writing a '1' to it
\end{small}
\item \begin{small}
{\bf
WRPRES
} [\emph{read-only}]: White Rabbit present
\\
1 -- White Rabbit present \\ 0 -- White Rabbit not present
\end{small}
\item \begin{small}
{\bf
I2C\_ERR
} [\emph{read/write}]: I2C communication error
\\
1 -- attempted to address non-existing address \\ 0 -- idle \\ This bit can be cleared by writing a '1' to it
\end{small}
\item \begin{small}
{\bf
PMISSE
} [\emph{read/write}]: Pulse missed error
\\
1 -- pulse arrived during pulse rejection phase \\ 0 -- idle \\ This bit can be cleared by writing a '1' to it
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CR -- Control Register}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & \multicolumn{2}{|c|}{\cellcolor{gray!25}MPT[7:6]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{6}{|c|}{\cellcolor{gray!25}MPT[5:0]} & \multicolumn{1}{|c|}{\cellcolor{gray!25}RST} & \multicolumn{1}{|c|}{\cellcolor{gray!25}RST\_UNLOCK}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
RST\_UNLOCK
} [\emph{read/write}]: Reset unlock bit
\\
1 -- Reset bit unlocked \\ 0 -- Reset bit locked
\end{small}
\item \begin{small}
{\bf
RST
} [\emph{read/write}]: Reset bit
\\
1 -- initiate logic reset \\ 0 -- no reset
\end{small}
\item \begin{small}
{\bf
MPT
} [\emph{write-only}]: Manual Pulse Trigger
\\
Write the following sequence to trigger a pulse: \\ 0xde -- Byte 1 of magic sequence \\ 0xad -- Byte 2 of magic sequence \\ 0xbe -- Byte 3 of magic sequence \\ 0xef -- Byte 4 of magic sequence \\ Number in range 1..6 -- trigger a pulse
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH1PCR -- Channel 1 Pulse Counter Register}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1PCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1PCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1PCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1PCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH1PCR
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH2PCR -- Channel 2 Pulse Counter Register}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2PCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2PCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2PCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2PCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH2PCR
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH3PCR -- Channel 3 Pulse Counter Register}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3PCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3PCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3PCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3PCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH3PCR
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH4PCR -- Channel 4 Pulse Counter Register}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4PCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4PCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4PCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4PCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH4PCR
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH5PCR -- Channel 5 Pulse Counter Register}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5PCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5PCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5PCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5PCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH5PCR
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH6PCR -- Channel 6 Pulse Counter Register}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6PCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6PCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6PCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6PCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH6PCR
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{TVLR -- Time Value Low Register}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TVLR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TVLR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TVLR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TVLR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TVLR
} [\emph{read/write}]: TAI seconds counter bits 31..0
\\
Writing this field resets the internal cycles counter.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{TVHR -- Time Value High Register}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TVHR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TVHR
} [\emph{read/write}]: TAI seconds counter bits 39..32
\\
Writing this field resets the internal cycles counter.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{TBMR -- Tag Buffer Meta Register}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c|}{\cellcolor{gray!25}WRTAG} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{1}{|c}{-} & - & \multicolumn{6}{|c|}{\cellcolor{gray!25}CHAN[5:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CHAN
} [\emph{read-only}]: Channel mask
\\
Mask for the channel(s) that triggered time-tag storage: \\ bit 0 -- channel 1 \\ bit 1 -- channel 2 \\ ... \\ bit 5 -- channel 6
\end{small}
\item \begin{small}
{\bf
WRTAG
} [\emph{read-only}]: White Rabbit present
\\
1 - Current time tag generated with White Rabbit \\ 0 - Current time tag generated with internal counter
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\item \begin{small}
\textbf{A read from this register advances the buffer read pointer, if the ring buffer is not empty}
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{TBCYR -- Tag Buffer Cycles Register}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}TBCYR[27:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TBCYR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TBCYR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TBCYR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TBCYR
} [\emph{read-only}]: Cycles counter
\\
Value of the 8-ns cycles counter when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{TBTLR -- Tag Buffer TAI Low Register}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TBTLR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TBTLR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TBTLR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TBTLR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TBTLR
} [\emph{read-only}]: Lower part of TAI seconds counter
\\
Value of the TAI seconds counter bits 31..0 when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\pagebreak
\vspace{11pt}
\subsubsection{TBTHR -- Tag Buffer TAI High Register}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TBTHR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TBTHR
} [\emph{read-only}]: Upper part of TAI seconds counter
\\
Value of the TAI seconds counter bits 39..32 when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{TBCSR -- Tag Buffer Control and Status Register}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}CLR} & \multicolumn{1}{|c|}{\cellcolor{gray!25}EMPTY} & \multicolumn{1}{|c|}{\cellcolor{gray!25}FULL}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{1}{|c}{-} & \multicolumn{7}{|c|}{\cellcolor{gray!25}USEDW[6:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
USEDW
} [\emph{read-only}]: Buffer counter
\\
Number of samples in the ring buffer
\end{small}
\item \begin{small}
{\bf
FULL
} [\emph{read-only}]: Buffer full
\\
1 -- buffer full \\ 0 -- buffer is not full
\end{small}
\item \begin{small}
{\bf
EMPTY
} [\emph{read-only}]: Buffer empty
\\
1 -- buffer empty\\ 0 -- buffer is not empty
\end{small}
\item \begin{small}
{\bf
CLR
} [\emph{read/write}]: Clear tag buffer
\\
1 -- clear\\ 0 -- no effect
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH1LTSCYR -- Channel 1 Latest Timestamp Cycles Register}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}CH1LTSCYR[27:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1LTSCYR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1LTSCYR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1LTSCYR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH1LTSCYR
} [\emph{write-only}]: Cycles counter
\\
Value of the 8-ns cycles counter when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH1LTSTLR -- Channel 1 Latest Timestamp TAI Low Register}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1LTSTLR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1LTSTLR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1LTSTLR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1LTSTLR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH1LTSTLR
} [\emph{read-only}]: Lower part of TAI seconds counter
\\
Value of the TAI seconds counter bits 31..0 when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\pagebreak
\subsubsection{CH1LTSTHR -- Channel 1 Latest Timestamp TAI High Register}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c|}{\cellcolor{gray!25}WRTAG} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TAI
} [\emph{read-only}]: Upper part of TAI seconds counter
\\
Value of the TAI seconds counter bits 39..32 when time tag was taken.
\end{small}
\item \begin{small}
{\bf
WRTAG
} [\emph{read-only}]: White Rabbit present
\\
1 - Current time tag generated with White Rabbit \\ 0 - Current time tag generated with internal counter
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH2LTSCYR -- Channel 2 Latest Timestamp Cycles Register}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}CH2LTSCYR[27:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2LTSCYR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2LTSCYR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2LTSCYR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH2LTSCYR
} [\emph{write-only}]: Cycles counter
\\
Value of the 8-ns cycles counter when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH2LTSTLR -- Channel 2 Latest Timestamp TAI Low Register}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2LTSTLR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2LTSTLR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2LTSTLR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2LTSTLR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH2LTSTLR
} [\emph{read-only}]: Lower part of TAI seconds counter
\\
Value of the TAI seconds counter bits 31..0 when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH2LTSTHR -- Channel 2 Latest Timestamp TAI High Register}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c|}{\cellcolor{gray!25}WRTAG} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TAI
} [\emph{read-only}]: Upper part of TAI seconds counter
\\
Value of the TAI seconds counter bits 39..32 when time tag was taken.
\end{small}
\item \begin{small}
{\bf
WRTAG
} [\emph{read-only}]: White Rabbit present
\\
1 - Current time tag generated with White Rabbit \\ 0 - Current time tag generated with internal counter
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH3LTSCYR -- Channel 3 Latest Timestamp Cycles Register}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}CH3LTSCYR[27:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3LTSCYR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3LTSCYR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3LTSCYR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH3LTSCYR
} [\emph{write-only}]: Cycles counter
\\
Value of the 8-ns cycles counter when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH3LTSTLR -- Channel 3 Latest Timestamp TAI Low Register}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3LTSTLR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3LTSTLR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3LTSTLR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3LTSTLR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH3LTSTLR
} [\emph{read-only}]: Lower part of TAI seconds counter
\\
Value of the TAI seconds counter bits 31..0 when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\pagebreak
\subsubsection{CH3LTSTHR -- Channel 3 Latest Timestamp TAI High Register}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c|}{\cellcolor{gray!25}WRTAG} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TAI
} [\emph{read-only}]: Upper part of TAI seconds counter
\\
Value of the TAI seconds counter bits 39..32 when time tag was taken.
\end{small}
\item \begin{small}
{\bf
WRTAG
} [\emph{read-only}]: White Rabbit present
\\
1 - Current time tag generated with White Rabbit \\ 0 - Current time tag generated with internal counter
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH4LTSCYR -- Channel 4 Latest Timestamp Cycles Register}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}TAI[27:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TAI
} [\emph{write-only}]: Cycles counter
\\
Value of the 8-ns cycles counter when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH4LTSTLR -- Channel 4 Latest Timestamp TAI Low Register}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4LTSTLR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4LTSTLR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4LTSTLR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4LTSTLR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH4LTSTLR
} [\emph{read-only}]: Lower part of TAI seconds counter
\\
Value of the TAI seconds counter bits 31..0 when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH4LTSTHR -- Channel 4 Latest Timestamp TAI High Register}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c|}{\cellcolor{gray!25}WRTAG} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TAI
} [\emph{read-only}]: Upper part of TAI seconds counter
\\
Value of the TAI seconds counter bits 39..32 when time tag was taken.
\end{small}
\item \begin{small}
{\bf
WRTAG
} [\emph{read-only}]: White Rabbit present
\\
1 - Current time tag generated with White Rabbit \\ 0 - Current time tag generated with internal counter
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH5LTSCYR -- Channel 5 Latest Timestamp Cycles Register}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}CH5LTSCYR[27:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5LTSCYR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5LTSCYR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5LTSCYR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH5LTSCYR
} [\emph{write-only}]: Cycles counter
\\
Value of the 8-ns cycles counter when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH5LTSTLR -- Channel 5 Latest Timestamp TAI Low Register}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5LTSTLR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5LTSTLR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5LTSTLR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5LTSTLR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH5LTSTLR
} [\emph{read-only}]: Lower part of TAI seconds counter
\\
Value of the TAI seconds counter bits 31..0 when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\pagebreak
\subsubsection{CH5LTSTHR -- Channel 5 Latest Timestamp TAI High Register}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c|}{\cellcolor{gray!25}WRTAG} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TAI
} [\emph{read-only}]: Upper part of TAI seconds counter
\\
Value of the TAI seconds counter bits 39..32 when time tag was taken.
\end{small}
\item \begin{small}
{\bf
WRTAG
} [\emph{read-only}]: White Rabbit present
\\
1 - Current time tag generated with White Rabbit \\ 0 - Current time tag generated with internal counter
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH6LTSCYR -- Channel 6 Latest Timestamp Cycles Register}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}CH6LTSCYR[27:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6LTSCYR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6LTSCYR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6LTSCYR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH6LTSCYR
} [\emph{write-only}]: Cycles counter
\\
Value of the 8-ns cycles counter when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH6LTSTLR -- Channel 6 Latest Timestamp TAI Low Register}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6LTSTLR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6LTSTLR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6LTSTLR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6LTSTLR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH6LTSTLR
} [\emph{read-only}]: Lower part of TAI seconds counter
\\
Value of the TAI seconds counter bits 31..0 when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH6LTSTHR -- Channel 6 Latest Timestamp TAI High Register}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c|}{\cellcolor{gray!25}WRTAG} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TAI
} [\emph{read-only}]: Upper part of TAI seconds counter
\\
Value of the TAI seconds counter bits 39..32 when time tag was taken.
\end{small}
\item \begin{small}
{\bf
WRTAG
} [\emph{read-only}]: White Rabbit present
\\
1 - Current time tag generated with White Rabbit \\ 0 - Current time tag generated with internal counter
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{LSR -- Line Status Register}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & \multicolumn{6}{|c|}{\cellcolor{gray!25}FS[5:0]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{6}{|c|}{\cellcolor{gray!25}REAR[5:0]} & \multicolumn{2}{|c|}{\cellcolor{gray!25}FRONT\_INVTTL[3:2]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{2}{|c|}{\cellcolor{gray!25}FRONT\_INVTTL[1:0]} & \multicolumn{6}{|c|}{\cellcolor{gray!25}FRONT\_TTL[5:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
FRONT\_TTL
} [\emph{read-only}]: Front panel TTL input state
\\
Line state at board inputBit 0 -- channel 1Bit 1 -- channel 2etc.
\end{small}
\item \begin{small}
{\bf
FRONT\_INVTTL
} [\emph{read-only}]: Front panel INV-TTL input state
\\
Line state at board inputBit 0 -- channel 1Bit 1 -- channel 2etc.
\end{small}
\item \begin{small}
{\bf
REAR
} [\emph{read-only}]: Rear panel input state
\\
Line state at board inputBit 0 -- channel 1Bit 1 -- channel 2etc.
\end{small}
\item \begin{small}
{\bf
FS
} [\emph{read-only}]: Input failsafe state
\\
High if line is in failsafe mode (no cable plugged in)Bit 0 -- channel 1Bit 1 -- channel 2etc.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{MSWR -- Multicast Switch Register}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}BIT[3:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
BIT
} [\emph{read-only}]: State of MultiCast switches
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
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\section{MultiBoot controller}
\label{app:memmap}
{
\rowcolors{2}{white}{gray!25}
\begin{longtable}{l l l p{.5\textwidth}}
\hline
\textbf{Offset} & \textbf{Reset} & \textbf{Name}
& \textbf{Description} \\
\hline
\endfirsthead
\hline
\hline
\endhead
\hline
\endfoot
0x0 & 0x00000000 & CR & Control Register\\
0x4 & 0x00000000 & SR & Status Register\\
0x8 & 0x00000000 & GBBAR & Golden Bitstream Base Address Register\\
0xc & 0x00000000 & MBBAR & MultiBoot Bitstream Base Address Register\\
0x10 & 0x10000000 & FAR & Flash Access Register\\
\end{longtable}
}
\vspace{11pt}
\subsection{CR -- Control Register}
\label{app:memmap-cr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}IPROG} & \multicolumn{1}{|c|}{\cellcolor{gray!25}IPROG\_UNLOCK}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{1}{|c}{-} & \multicolumn{1}{|c|}{\cellcolor{gray!25}RDCFGREG} & \multicolumn{6}{|c|}{\cellcolor{gray!25}CFGREGADR[5:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CFGREGADR
} [\emph{read/write}]: Configuration register address
\\
Address of FPGA configuration register to read.
\end{small}
\item \begin{small}
{\bf
RDCFGREG
} [\emph{write-only}]: Read FPGA configuration register
\\
1 -- Start FPGA configuration register sequence. \\ 0 -- No effect.
\end{small}
\item \begin{small}
{\bf
IPROG\_UNLOCK
} [\emph{read/write}]: Unlock bit for the IPROG command
\\
1 -- Unlock IPROG bit. \\ 0 -- No effect.
\end{small}
\item \begin{small}
{\bf
IPROG
} [\emph{read/write}]: Start IPROG sequence
\\
1 -- Start IPROG configuration sequence \\ 0 -- No effect \\ This bit needs to be unlocked by writing the IPROG\_UNLOCK bit first. \\ A write to this bit with IPROG\_UNLOCK cleared has no effect.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsection{SR -- Status Register}
\label{app:memmap-sr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}WDTO} & \multicolumn{1}{|c|}{\cellcolor{gray!25}IMGVALID}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CFGREGIMG[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CFGREGIMG[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CFGREGIMG
} [\emph{read-only}]: Configuration register image
\\
Image of the FPGA configuration register at address CFGREGADR (see Configuration Registers section in Xilinx UG380~\cite{ug380}); validated by IMGVALID bit
\end{small}
\item \begin{small}
{\bf
IMGVALID
} [\emph{read-only}]: Configuration register image valid
\\
1 -- CFGREGIMG valid \\ 0 -- CFGREGIMG not valid;
\end{small}
\item \begin{small}
{\bf
WDTO
} [\emph{read/write}]: MultiBoot FSM stalled at one point and was reset by FSM watchdog
\\
1 -- FSM watchdog fired \\ 0 -- FSM watchdog has not fired
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsection{GBBAR -- Golden Bitstream Base Address Register}
\label{app:memmap-gbbar}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
BITS
} [\emph{read/write}]: Bits of GBBAR register
\\
31..24 -- Read or fast-read OPCODE of the flash chip (obtain it from the flash chip datasheet) \\ 23..0 -- Golden bitstream address in flash
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsection{MBBAR -- MultiBoot Bitstream Base Address Register}
\label{app:memmap-mbbar}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
BITS
} [\emph{read/write}]: Bits of MBBAR register
\\
31..24 -- Read or fast-read OPCODE of the flash chip (obtain it from the flash chip datasheet) \\ 23..0 -- MultiBoot bitstream start address in flash
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsection{FAR -- Flash Access Register}
\label{app:memmap-far}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}READY} & \multicolumn{1}{|c|}{\cellcolor{gray!25}CS} & \multicolumn{1}{|c|}{\cellcolor{gray!25}XFER} & \multicolumn{2}{|c|}{\cellcolor{gray!25}NBYTES[1:0]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}DATA[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}DATA[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}DATA[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
DATA
} [\emph{read/write}]: Flash data field
\\
23..16 -- DATA[2]; after an SPI transfer, this register contains the value of data byte 2 read from the flash \\ 15..8 -- DATA[1]; after an SPI transfer, this register contains the value of data byte 1 read from the flash \\ 7..0 -- DATA[0]; after an SPI transfer, this register contains the value of data byte 0 read from the flash
\end{small}
\item \begin{small}
{\bf
NBYTES
} [\emph{read/write}]: Number of DATA fields to send and receive in one transfer:
\\
0x0 -- Send 1 byte (DATA[0]) \\ 0x1 -- Send 2 bytes (DATA[0], DATA[1]) \\ 0x2 -- Send 3 bytes (DATA[0], DATA[1], DATA[2])
\end{small}
\item \begin{small}
{\bf
XFER
} [\emph{write-only}]: Start transfer to and from flash
\\
1 -- Start transfer \\ 0 -- Idle
\end{small}
\item \begin{small}
{\bf
CS
} [\emph{read/write}]: Chip select bit
\\
1 - Flash chip selected (CS pin low) \\ 0 - Flash chip not selected (CS pin is high)
\end{small}
\item \begin{small}
{\bf
READY
} [\emph{read-only}]: Flash access ready
\\
1 - Flash access completed \\ 0 - Flash access in progress
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
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