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conv-common-gw
Commit 108561a8 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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doc: small changes

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doc/cern-title.tex
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......@@ -9,7 +9,7 @@
\noindent \rule{\textwidth}{.1cm}
\hfill August 5, 2014
\hfill August 12, 2014
\vspace*{3cm}
......
doc/conv-common-gw.bib
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......@@ -45,3 +45,21 @@
title = {{Rear Transition Module detection}},
howpublished = {\url{http://www.ohwr.org/projects/conv-ttl-blo/wiki/RTM_board_detection}}
}
@misc{blocking,
author = "C. Gil Soriano",
title = {{Standard Blocking Output Signal Definition for CTDAH board}},
month = sep,
year = 2011,
note = {\url{http://www.ohwr.org/documents/109}}
}
@misc{ug380,
title = {{UG380 - Spartan-6 Configuration Guide}},
author = {Xilinx},
month = jan,
year = {2013},
note = {v2.5},
howpublished = {\url{http://www.xilinx.com/support/documentation/user_guides/ug380.pdf}}
}
doc/conv-common-gw.tex
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......@@ -48,7 +48,8 @@
%------------------------------------------------------------------------------
% Revision history
%------------------------------------------------------------------------------
\thispagestyle{empty}
\pagebreak
\addcontentsline{toc}{section}{Revision history}
\section*{Revision history}
\centerline
......@@ -57,20 +58,19 @@
\begin{tabular}{l c p{.6\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Date}} & \multicolumn{1}{c}{\textbf{Version}} & \multicolumn{1}{c}{\textbf{Change}} \\
\hline
\hline
05-08-2014 & 0.1 & First draft \\
12-08-2014 & 1.0 & First release \\
\hline
\end{tabular}
}
\pagebreak
\pagenumbering{roman}
\setcounter{page}{1}
\tableofcontents
%------------------------------------------------------------------------------
% List of figs, tables
%------------------------------------------------------------------------------
\pagebreak
\pdfbookmark[1]{\contentsname}{toc}
\tableofcontents
\listoffigures
\listoftables
......@@ -86,15 +86,12 @@ LSR & Line Status Register \\
MSWR & Multicast Switch Register \\
SR & Status Register \\
\end{tabular}
\pagebreak
\pagenumbering{arabic}
\setcounter{page}{1}
\addcontentsline{toc}{section}{List of abbreviations}
%==============================================================================
% SEC: Intro
%==============================================================================
\pagebreak
\section{Introduction}
\label{sec:intro}
......@@ -102,7 +99,7 @@ This document presents the common gateware for converter board projects~\cite{le
This gateware, mainly written in VHDL, is a grouping of modules common to all converter board projects.
A synthesized version thereof is intended to be downloaded to the FPGA on the converter board.
No specific FPGA is assumed for the converter boards, therefore the VHDL code is as generic as possible.
However, some details about the way that the boars are designed in the Hardware \& Timing section at CERN
However, some details about the way that the boards are designed in the Hardware \& Timing section at CERN
are assumed, and these details are described throughout the document.
The document will start with a summary of the VHDL entity's ports, continue with presenting
......@@ -162,13 +159,15 @@ The module's generics are listed here for quick reference (Table~\ref{tbl:generi
g\_pgen\_fixed\_width & Pulse generator with fixed width at output \newline
\textit{true} -- fixed-width output pulse and pulse rejection after pulse is generated \newline
\textit{false} -- pulse generator is simple pass-through \\
g\_pgen\_pwidth & Pulse width at generator output \newline
Value in number of \textit{clk\_20\_i} cycles \newline
Constrained between 20 and 40 \textit{clk\_20\_i} cycles \newline
No effect if \textit{g\_pgen\_fixed\_width} is \textit{false} \\
g\_pgen\_duty\_cycle\_div & Divider ratio of pulse rejection mechanism \newline
Output max. freq. 1/g\_pgen\_duty\_cycle\_div \newline
No effect if \textit{g\_pgen\_fixed\_width} is \textit{false} \\
g\_pgen\_pwidth & No effect if \textit{g\_pgen\_fixed\_width} is \textit{false} \newline
Pulse width at generator output \newline
Value in number of \textit{clk\_20\_i} cycles \newline
Default: 24 (1.2~${\mu}s$~\cite{blocking}) \newline
Constrained between 20 and 40 \textit{clk\_20\_i} cycles \newline
(1--2~${\mu}s$~\cite{blocking}) \\
g\_pgen\_duty\_cycle\_div & No effect if \textit{g\_pgen\_fixed\_width} is \textit{false} \newline
Divider ratio of pulse rejection mechanism \newline
Output max. freq. 1/g\_pgen\_duty\_cycle\_div \\
g\_pgen\_gf\_len & Pulse generation mechanism glitch filter length in number of \textit{clk\_20\_i} cycles \\
g\_bicolor\_led\_columns & Number of columns for bicolor LED controller \\
g\_bicolor\_led\_lines & Number of lines for bicolor LED controller \\
......@@ -363,7 +362,7 @@ rejection state.
\begin{figure}
\centerline{\includegraphics[width=\textwidth]{fig/pulse-gen-operation}}
\caption{\label{fig:pulse-gen-operation} Pulse generator operation}
\caption{\label{fig:pulse-gen-operation} Pulse generator operation with \textit{g\_pgen\_fixed\_width = true}}
\end{figure}
%------------------------------------------------------------------------------
......@@ -525,5 +524,6 @@ The following sections list the memory map of each peripheral.
\pagebreak
\bibliographystyle{ieeetr}
\bibliography{conv-common-gw}
\addcontentsline{toc}{section}{References}
\end{document}
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