Commit 0bb46c7a authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag

Merge branch 'gw_v3_dev'

parents 73525861 07f48154
......@@ -9,7 +9,7 @@
\noindent \rule{\textwidth}{.1cm}
\hfill January 26, 2014
\hfill 17 February 2017
\vspace*{3cm}
......@@ -24,7 +24,9 @@
%---------------------------------------------------------------
% name
%---------------------------------------------------------------
\noindent {\Large \textbf{Theodor-Adrian Stana (CERN/BE-CO-HT)}}
\noindent {\Large \textbf{Theodor-Adrian Stana (CERN/BE-CO-HT)}}\\
\noindent {Last modified by \textit{Denia Bouhired-Ferrag (CERN/BE-CO-HT)}}\\
\noindent \rule{\textwidth}{.05cm}
......
......@@ -21,8 +21,14 @@
note = {\url{http://www.ohwr.org/projects/conv-common-gw/repository}}
}
@misc{bib:doulos-counter,
title = {{Repository for converter board common gateware}},
note = {\url{https://www.doulos.com/knowhow/fpga/fastcounter/}}
}
@misc{board-id,
title = {{Board IDs for level conversion circuits}},
title = {{A counter for fast events, using a Flancter}},
note = {\url{http://www.ohwr.org/projects/conv-common-gw/wiki/Board-id}}
}
......
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general-cores @ 9a40120b
Subproject commit 382b46c19757e0c7c8574ebe56f32169c5a84b20
Subproject commit 9a40120ba4af4a7551f9fd8cbbe61f1d434f30bf
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.conv_common_gw_pkg.all;
entity wf_decr_counter is
generic(g_counter_lgth : natural := 4); -- default length
port(
-- INPUTS
-- nanoFIP User Interface general signal
uclk_i : in std_logic; -- 40 MHz clock
-- Signal from the wf_reset_unit
counter_rst_i : in std_logic; -- resets counter to all '1'
-- Signals from any unit
counter_decr_i : in std_logic; -- decrement enable
counter_load_i : in std_logic; -- load enable; loads counter to counter_top_i
counter_top_i : in unsigned (g_counter_lgth-1 downto 0); -- load value
-- OUTPUTS
-- Signal to any unit
counter_o : out unsigned (g_counter_lgth-1 downto 0); -- counter
counter_is_zero_o : out std_logic); -- empty counter indication
end entity wf_decr_counter;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of wf_decr_counter is
signal s_counter : unsigned (g_counter_lgth-1 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- Synchronous process Decr_Counter
Decr_Counter: process (uclk_i)
begin
if rising_edge (uclk_i) then
if counter_rst_i = '1' then
s_counter <= (others => '1');
else
if counter_load_i = '1' then
s_counter <= counter_top_i;
elsif counter_decr_i = '1' then
s_counter <= s_counter - 1;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
counter_o <= s_counter;
counter_is_zero_o <= '1' when s_counter = to_unsigned(0, s_counter'length) else '0';
end architecture ;
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