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conv-common-gw
Commit 08960e47 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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Small bug fixes to new version of conv_pulse_gen.vhd. Bug in pulse counters in… 

Small bug fixes to new version of conv_pulse_gen.vhd. Bug in pulse counters in top file conv_common_gw fixed. pulse counters were not resetting after the external loading of new values.
parent 011fbe69
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modules/conv_pulse_gen.vhd
View file @ 08960e47
......@@ -118,7 +118,7 @@ architecture behav of conv_pulse_gen is
--============================================================================
type t_state is (
IDLE, -- idle state, wait for pulse
PRE_IDLE, -- idle state, wait for pulse
CATCH_ERR, -- idle state, wait for pulse
GEN_PULSE_OUTPUT, -- pulse generation
REJ_PULSE_INPUT -- pulse rejection
......@@ -138,7 +138,7 @@ architecture behav of conv_pulse_gen is
-- Rejection time:
-- * Maximum pulse period = g_pperiod*g_pwidth
-- * Allow one cycle to change state from REJ_PULSE_INPUT to PRE_IDLE
-- * Allow one cycle to change state from REJ_PULSE_INPUT to CATCH_ERR
constant c_max_rej : natural := g_pperiod-1;
-- Rising edges result from leading edge of trigger going through a 3 stage synchrnoiser.
......@@ -219,19 +219,17 @@ gen_with_fixed_pwidth : if (g_with_fixed_pwidth = true) generate
--============================================================================
-- Generate the pulse on rising edge of trig_a_i
p_pulse_gf_off : process(pulse_out_rst_n, trig_a_i, en_i, gf_en_n_i)
p_pulse_gf_off : process(pulse_out_rst_n, trig_a_i, en_i)
begin
if pulse_out_rst_n = '0' then
pulse_out <= '0';
elsif rising_edge(trig_a_i) then
if (en_i = '1') then --and (gf_en_n_i = '1') then
if (en_i = '1') then
pulse_out <= '1';
end if;
end if;
end process p_pulse_gf_off;
--pulse_gf_on <= '0' when pulse_out_rst_n = '0' else trig_a_i and not gf_en_n_i;
--============================================================================
......@@ -289,7 +287,7 @@ gen_with_fixed_pwidth : if (g_with_fixed_pwidth = true) generate
nxt_state <= IDLE;
end if;
when PRE_IDLE =>
when CATCH_ERR =>
if pulse_cnt >= c_r_edge_sync_delay-1 then
if trig_r_edge_p_i = '1' then
......@@ -298,7 +296,7 @@ gen_with_fixed_pwidth : if (g_with_fixed_pwidth = true) generate
nxt_state <= IDLE;
end if;
else
nxt_state <= PRE_IDLE;
nxt_state <= CATCH_ERR;
end if;
---------------------------------------------------------------------
......@@ -320,7 +318,7 @@ gen_with_fixed_pwidth : if (g_with_fixed_pwidth = true) generate
---------------------------------------------------------------------
when REJ_PULSE_INPUT =>
if pulse_cnt = c_max_rej then
nxt_state <= PRE_IDLE;
nxt_state <= CATCH_ERR;
else
nxt_state <= REJ_PULSE_INPUT;
end if;
......@@ -334,7 +332,7 @@ gen_with_fixed_pwidth : if (g_with_fixed_pwidth = true) generate
-- Generate the FSM logic
p_fsm_outputs : process(state, trig_r_edge_p_i, pulse_cnt)
p_fsm_outputs : process(state, trig_r_edge_p_i, pulse_cnt, rst_n_i)
begin
case state is
......@@ -350,7 +348,7 @@ gen_with_fixed_pwidth : if (g_with_fixed_pwidth = true) generate
pulse_cnt_reset <= '1';
pulse_cnt_clr <= '0';
when PRE_IDLE =>
when CATCH_ERR =>
pulse_out_rst_n <= rst_n_i;
if pulse_cnt < c_r_edge_sync_delay-1 then
pulse_err_p_o <= trig_r_edge_p_i;
......
top/conv_common_gw.vhd
View file @ 08960e47
......@@ -60,7 +60,7 @@ entity conv_common_gw is
-- Number of repeater channels
g_nr_chans : integer := 6;
-- Number of inverter channels
g_nr_inv_chans : integer := 4;
g_nr_inv_chans : integer := 4;
-- Board ID -- 4-letter ASCII string indicating the board ID
-- see [1] for example
......@@ -74,66 +74,66 @@ entity conv_common_gw is
g_pgen_pwidth_lg : natural range 2 to 40 := 24;
g_pgen_pwidth_sh : natural range 2 to 40 := 5;
-- output pulse will be limited to period
--For continuous mode operation max freq 4.16kHz
g_pgen_pperiod_cont : natural range 2 to 5000 := 4800;
--for LONG pulses changes maximum frequency to ~104kHz
g_pgen_pperiod_lg : natural range 6 to 300 := 191;
--for SHORT pulses changes maximum frequency to ~2MHz
g_pgen_pperiod_sh : natural range 2 to 300 := 9;
-- Output pulse will be limited to period. They are given as n number of cycles
-- For continuous mode operation max freq 4.16kHz
g_pgen_pperiod_cont : natural range 2 to 5000 := 4800;
--for LONG pulses changes maximum frequency to ~104kHz
g_pgen_pperiod_lg : natural range 6 to 300 := 191;
--for SHORT pulses changes maximum frequency to ~2MHz
g_pgen_pperiod_sh : natural range 2 to 300 := 9;
-- Pulse generator glitch filter length in number of clk_20_i cycles
g_pgen_gf_len : integer := 4;
-- Burst-mode-specific generics:
g_temp_decre_step_lg : t_temp_decre_step :=
(0,0,0,0,0,0,0,0,5750,100,79,13,12,4,5,13);
g_temp_decre_step_sh : t_temp_decre_step :=
(0,0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0);
-- Single pulse temperature rise
-- For long 1.2us pulses
g_burstctrl_1_pulse_temp_rise_lg :in unsigned (19 downto 0) := x"17700";
-- For short 250ns pulses
g_burstctrl_1_pulse_temp_rise_sh :in unsigned (19 downto 0) := x"01388";
-- Maximum temperature allowed (scaled)
g_burstctrl_max_temp_lg_sh :in unsigned (39 downto 0)
:=x"02540BE400"; --For both long 1.2us pulses and short 250ns
g_pgen_gf_len : integer := 4;
-- Burst-mode-specific generics:
g_temp_decre_step_lg : t_temp_decre_step :=
(0,0,0,0,0,0,0,0,5750,100,79,13,12,4,5,13);
g_temp_decre_step_sh : t_temp_decre_step :=
(0,0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0);
-- Single pulse temperature rise
-- For long 1.2us pulses
g_burstctrl_1_pulse_temp_rise_lg :in unsigned (19 downto 0) := x"17700";
-- For short 250ns pulses
g_burstctrl_1_pulse_temp_rise_sh :in unsigned (19 downto 0) := x"01388";
-- Maximum temperature allowed (scaled)
g_burstctrl_max_temp_lg_sh :in unsigned (39 downto 0)
:=x"02540BE400"; --For both long 1.2us pulses and short 250ns
-- Generate logic with pulse counters
g_with_pulse_cnt : boolean := false;
g_with_pulse_cnt : boolean := false;
-- Generate logic with pulse timetag
g_with_pulse_timetag : boolean := false;
g_with_pulse_timetag : boolean := false;
-- Generate logic with manual trigger
g_with_man_trig : boolean := false;
g_man_trig_pwidth : integer := 24;
g_with_man_trig : boolean := false;
g_man_trig_pwidth : integer := 24;
-- Generate one-wire master for thermometer
g_with_thermometer : boolean := false;
g_with_thermometer : boolean := false;
-- Bicolor LED controller signals
g_bicolor_led_columns : integer := 6;
g_bicolor_led_lines : integer := 2
g_bicolor_led_columns : integer := 6;
g_bicolor_led_lines : integer := 2
);
port
(
-- Clocks
clk_20_i : in std_logic;
clk_125_p_i : in std_logic;
clk_125_n_i : in std_logic;
clk_20_i : in std_logic;
clk_125_p_i : in std_logic;
clk_125_n_i : in std_logic;
-- Reset output signal, synchronous to 20 MHz clock
rst_n_o : out std_logic;
-- Glitch filter active-low enable signal
gf_en_n_i : in std_logic;
-- Burst mode enable signal. Mode disabled for all versions of board
burst_en_n_i : in std_logic;
-- Pulse width selection, port low means 250ns, high means 1.2us.
pulse_width_sel_n_i : in std_logic;
burst_en_n_i : in std_logic;
-- Pulse width selection, port low means 250ns, high means 1.2us.
pulse_width_sel_n_i : in std_logic;
-- Channel enable
global_ch_oen_o : out std_logic;
pulse_front_oen_o : out std_logic;
......@@ -145,17 +145,17 @@ entity conv_common_gw is
pulse_ttl_i : in std_logic_vector(g_nr_chans-1 downto 0);
pulse_blo_i : in std_logic_vector(g_nr_chans-1 downto 0);
pulse_o : out std_logic_vector(g_nr_chans-1 downto 0);
-- Inverted pulse I/O
inv_pulse_i_n : in std_logic_vector(g_nr_inv_chans-1 downto 0);
inv_pulse_o : out std_logic_vector(g_nr_inv_chans-1 downto 0);
-- Inverted pulse I/O
inv_pulse_i_n : in std_logic_vector(g_nr_inv_chans-1 downto 0);
inv_pulse_o : out std_logic_vector(g_nr_inv_chans-1 downto 0);
-- Channel lEDs
-- 26 ms active-high pulse on pulse_o rising edge
led_pulse_o : out std_logic_vector(g_nr_chans-1 downto 0);
-- Inverted channel lEDs
-- Inverted channel lEDs
-- 26 ms active-high pulse on pulse_o rising edge
led_inv_pulse_o : out std_logic_vector(g_nr_inv_chans-1 downto 0);
......@@ -204,9 +204,9 @@ entity conv_common_gw is
-- Switch inputs (for readout from converter status register)
sw_gp_i : in std_logic_vector(7 downto 0);
sw_other_i : in std_logic_vector(31 downto 0);
-- PCB Version information
hwvers_i : in std_logic_vector (5 downto 0);
hwvers_i : in std_logic_vector (5 downto 0);
-- RTM lines
rtmm_i : in std_logic_vector(2 downto 0);
rtmp_i : in std_logic_vector(2 downto 0);
......@@ -287,17 +287,17 @@ architecture arch of conv_common_gw is
-- Max. channel count of c_max_nr_chans enforced here:
type t_pulse_led_cnt is array(c_max_nr_chans-1 downto 0)
of unsigned(18 downto 0);
type t_inv_pulse_led_cnt is array(g_nr_inv_chans-1 downto 0)
of unsigned(18 downto 0);
type t_temp_rise_cnt is array(c_max_nr_chans-1 downto 0)
of unsigned(39 downto 0);
type t_pulse_cnt is array(c_max_nr_chans-1 downto 0)
of unsigned(31 downto 0);
type t_ch_pcr is array(c_max_nr_chans-1 downto 0)
of std_logic_vector(31 downto 0);
-- Latest timestamp
type t_lts_tai is array(c_max_nr_chans-1 downto 0)
of std_logic_vector(39 downto 0);
......@@ -383,10 +383,16 @@ architecture arch of conv_common_gw is
signal fwdg_pmisse_bit_rst : std_logic_vector(c_max_nr_chans-1 downto 0);
signal fwdg_pmisse_bit_rst_ld : std_logic;
signal pmisse_bits_or : std_logic;
--signals for pulse counters
signal rst_ttl_cnt : std_logic_vector(c_max_nr_chans-1 downto 0);
signal rst_blo_cnt : std_logic_vector(c_max_nr_chans-1 downto 0);
signal pulse_cnt : t_pulse_cnt;
signal ttl_pulse_cnt : t_pulse_cnt;
signal ttl_pulse_cnt : t_pulse_cnt;
signal blo_pulse_cnt : t_pulse_cnt;
signal ttl_pulse_c : t_pulse_cnt;
signal ttl_pulse_cnt_offset : t_pulse_cnt;
signal blo_pulse_cnt_offset : t_pulse_cnt;
signal ttl_pulse_c : t_pulse_cnt;
signal blo_pulse_c : t_pulse_cnt;
signal ch_ttl_pcr : t_ch_pcr;
signal ch_ttl_pcr_ld : std_logic_vector(c_max_nr_chans-1 downto 0);
......@@ -472,6 +478,7 @@ architecture arch of conv_common_gw is
signal CONTROL : std_logic_vector(35 downto 0);
signal CLK : std_logic;
signal TRIG0_in : std_logic_vector(7 downto 0);
-- signal TRIG1_in : std_logic_vector(7 downto 0);
-- signal TRIG2_in : std_logic_vector(7 downto 0);
-- signal TRIG3_in : std_logic_vector(7 downto 0);
......@@ -492,26 +499,26 @@ begin
---------------------------------------------------------------------------------------------------
-- CHIPSCOPE --
---------------------------------------------------------------------------------------------------
chipscope_ila_1 : chipscope_ila
port map (
CONTROL => CONTROL,
CLK => clk_20_i,
TRIG0 => TRIG0_in);
-- chipscope_ila_1 : chipscope_ila
-- port map (
-- CONTROL => CONTROL,
-- CLK => clk_20_i,
-- TRIG0 => TRIG0_in);
chipscope_icon_1 : chipscope_icon
port map ( CONTROL0 => CONTROL);
-- chipscope_icon_1 : chipscope_icon
-- port map ( CONTROL0 => CONTROL);
TRIG0_in(0) <= pulse_outp_err_sh_p(5);
TRIG0_in(1) <= burst_outp_err_sh_p(5);
-- TRIG0_in(0) <= pulse_outp_err_sh_p(5);
-- TRIG0_in(1) <= burst_outp_err_sh_p(5);
TRIG0_in(2) <= trig_pgen(5);
TRIG0_in(3) <= pulse_outp_sh(5);
-- TRIG0_in(2) <= trig_pgen(5);
-- TRIG0_in(3) <= pulse_outp_sh(5);
TRIG0_in(4) <= pulse_outp_err_lg_p(5);
TRIG0_in(5) <= burst_outp_err_lg_p(5);
TRIG0_in(6) <= pulse_outp_lg(5);
TRIG0_in(7) <= ch_ttl_pcr_ld(5);
-- TRIG0_in(4) <= pulse_outp_err_lg_p(5);
-- TRIG0_in(5) <= burst_outp_err_lg_p(5);
-- TRIG0_in(6) <= pulse_outp_lg(5);
-- TRIG0_in(7) <= ch_ttl_pcr_ld(5);
--============================================================================
......@@ -540,7 +547,7 @@ begin
generic map
(
-- Reset time: 50ns * 2 * (10**6) = 100 ms
g_reset_time => 2*(10**4)
g_reset_time => 2*(10**6)
)
port map
(
......@@ -580,14 +587,14 @@ begin
ttl_oen <= '0';
invttl_oen <= '0';
rear_oen <= '0';
burst_en_n <= '0';
burst_en_n <= '0';
else
global_oen <= '1';
if global_oen = '1' then
ttl_oen <= '1';
invttl_oen <= '1';
rear_oen <= '1';
burst_en_n <= burst_en_n_i;
burst_en_n <= burst_en_n_i;
end if;
end if;
end if;
......@@ -629,9 +636,9 @@ gen_no_man_trig : if (g_with_man_trig = false) generate
trig_man <= (others => '0');
end generate gen_no_man_trig;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Glitch filter
--------------------------------------------------------------------------------
gen_pulse_chan_logic : for i in 0 to g_nr_chans-1 generate
-- Synchronize the asynchronous trigger input into the 20 MHz clock
......@@ -668,7 +675,7 @@ gen_pulse_chan_logic : for i in 0 to g_nr_chans-1 generate
trig_chan(i) <= trig_a(i) when (gf_en_n_i = '1') else
trig_degl(i);
-- The trigger to the pulse generator is either manual OR from the channel input
trig_pgen(i) <= trig_chan(i) or trig_man(i);
......@@ -680,6 +687,7 @@ gen_pulse_chan_logic : for i in 0 to g_nr_chans-1 generate
-- NOTE: glitch-filtered signal is also synced in 20MHz clock domain, but
-- another sync chain here avoids extra logic complication and should have
-- no influence on the correctness of the pulse counter value
cmp_sync_ffs : gc_sync_ffs
port map
(
......@@ -690,14 +698,25 @@ gen_pulse_chan_logic : for i in 0 to g_nr_chans-1 generate
npulse_o => trig_chan_fedge_p(i)
);
--------------------------------------------------------------------------------
-- Pulse counters:
--------------------------------------------------------------------------------
-- Use Flacter based fast counters to count fast pulses
-- See for more details https://www.doulos.com/knowhow/fpga/fastcounter/
-- The counter below has additional integer output value of the counter plus a
-- reset signal that depends on the system reset in addition to the counter load pulse
--------------------------------------------------------------------------------
gen_pulse_cnt : if (g_with_pulse_cnt = true) generate
rst_ttl_cnt(i) <= rst_20 or ch_ttl_pcr_ld(i);
rst_blo_cnt(i) <= rst_20 or ch_blo_pcr_ld(i);
cmp_pulse_cnt_ttl: fastevent_counter
port map(
sysclk_i => clk_20_i,
rstcount_i => rst_20,
rstcount_i => rst_ttl_cnt(i),
en_i => '1',
trig_i => pulse_ttl_i(i),
count_int_o => ttl_pulse_c(i)
......@@ -706,37 +725,31 @@ cmp_pulse_cnt_ttl: fastevent_counter
cmp_pulse_cnt_blo: fastevent_counter
port map(
sysclk_i => clk_20_i,
rstcount_i => rst_20,
rstcount_i => rst_blo_cnt(i),
en_i => '1',
trig_i => pulse_blo_i(i),
count_int_o => blo_pulse_c(i)
);
-- First, the pulse counters for the used channels (up to g_nr_chans)
p_pulse_cnt : process (clk_20_i)
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
pulse_cnt(i) <= (others => '0');
ttl_pulse_cnt(i) <= (others => '0');
blo_pulse_cnt(i) <= (others => '0');
elsif (ch_ttl_pcr_ld(i) = '1') then
ttl_pulse_cnt(i) <= unsigned(ch_ttl_pcr(i));
elsif (ch_blo_pcr_ld(i) = '1') then
blo_pulse_cnt(i) <= unsigned(ch_blo_pcr(i));
else
ttl_pulse_cnt(i) <= ttl_pulse_c(i);
blo_pulse_cnt(i) <= blo_pulse_c(i);
-- if (trig_chan_redge_p(i) = '1') then
-- pulse_cnt(i) <= pulse_cnt(i) + 1;
-- if (trig_chan_ttl_redge_p(i) = '1') then
-- ttl_pulse_cnt(i) <= ttl_pulse_cnt(i) + 1;
-- elsif (trig_chan_blo_redge_p(i) = '1') then
-- blo_pulse_cnt(i) <= blo_pulse_cnt(i) + 1;
-- end if;
end if;
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
pulse_cnt(i) <= (others => '0');
ttl_pulse_cnt(i) <= (others => '0');
blo_pulse_cnt(i) <= (others => '0');
ttl_pulse_cnt_offset(i) <= (others => '0');
blo_pulse_cnt_offset(i) <= (others => '0');
elsif (ch_ttl_pcr_ld(i) = '1') then
ttl_pulse_cnt_offset(i) <= unsigned(ch_ttl_pcr(i));
elsif (ch_blo_pcr_ld(i) = '1') then
blo_pulse_cnt_offset(i) <= unsigned(ch_blo_pcr(i));
else
ttl_pulse_cnt(i) <= ttl_pulse_cnt_offset(i)+ ttl_pulse_c(i);
blo_pulse_cnt(i) <= blo_pulse_cnt_offset(i)+ blo_pulse_c(i);
end if;
end if;
end process p_pulse_cnt;
......@@ -779,21 +792,21 @@ end generate gen_pulse_cnt;
en_i => '1',
trig_a_i => trig_pgen(i),
trig_r_edge_p_i => trig_chan_redge_p(i),
trig_f_edge_p_i => trig_chan_fedge_p(i),
trig_r_edge_p_i => trig_chan_redge_p(i),
trig_f_edge_p_i => trig_chan_fedge_p(i),
pulse_err_p_o => pulse_outp_err_cont (i),
pulse_o => pulse_outp_cont(i)
);
----------------------------------------------------------------------------------------------
-- Instantiate pulse generator + burst controller block for the channel for long pulse operation
-------------------------------------------------------------------------------------------------
-- BURST MODE WITH LONG PULSES
----------------------------------
--Instantiate pulse generator block for minimum pulse width and minimum allowed duty cycle
cmp_pulse_gen_lg : conv_pulse_gen
cmp_pulse_gen_lg : conv_pulse_gen
generic map
(
g_with_fixed_pwidth => g_pgen_fixed_width,
......@@ -810,8 +823,8 @@ end generate gen_pulse_cnt;
en_i => '1',
trig_a_i => trig_pgen(i),
trig_r_edge_p_i => trig_chan_redge_p(i),
trig_f_edge_p_i => trig_chan_fedge_p(i),
trig_r_edge_p_i => trig_chan_redge_p(i),
trig_f_edge_p_i => trig_chan_fedge_p(i),
pulse_err_p_o => pulse_outp_err_lg_p (i),
......@@ -819,31 +832,31 @@ end generate gen_pulse_cnt;
pulse_r_edge_p_o => pulse_r_edge_lg_p(i),
pulse_f_edge_p_o => pulse_f_edge_lg_p(i)
);
----------------------------------------------------------------------------------
-- Instantiate burst control block for the channel
cmp_burst_ctrl_lg : conv_dyn_burst_ctrl
generic map
(
g_pwidth => g_pgen_pwidth_lg,
g_temp_decre_step => g_temp_decre_step_lg,
g_1_pulse_temp_rise => g_burstctrl_1_pulse_temp_rise_lg,
g_max_temp => g_burstctrl_max_temp_lg_sh
)
port map
(
clk_i => clk_20_i,
rst_n_i => rst_20_n,
en_i => '1',
pulse_burst_i => pulse_outp_lg(i),
pulse_r_edge_p_i => pulse_r_edge_lg_p(i),
pulse_f_edge_p_i => pulse_f_edge_lg_p(i),
temp_rise_o => temp_rise_c_lg(i),
pulse_burst_o => burst_outp_lg(i),
burst_err_p_o => burst_outp_err_lg_p(i)
);
----------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Instantiate burst control block for the channel
cmp_burst_ctrl_lg : conv_dyn_burst_ctrl
generic map
(
g_pwidth => g_pgen_pwidth_lg,
g_temp_decre_step => g_temp_decre_step_lg,
g_1_pulse_temp_rise => g_burstctrl_1_pulse_temp_rise_lg,
g_max_temp => g_burstctrl_max_temp_lg_sh
)
port map
(
clk_i => clk_20_i,
rst_n_i => rst_20_n,
en_i => '1',
pulse_burst_i => pulse_outp_lg(i),
pulse_r_edge_p_i => pulse_r_edge_lg_p(i),
pulse_f_edge_p_i => pulse_f_edge_lg_p(i),
temp_rise_o => temp_rise_c_lg(i),
pulse_burst_o => burst_outp_lg(i),
burst_err_p_o => burst_outp_err_lg_p(i)
);
----------------------------------------------------------------------------------------------
-- Instantiate pulse generator + burst controller block for the channel for SHORT pulse operation
-------------------------------------------------------------------------------------------------
-- BURST MODE WITH SHORT PULSES
......@@ -866,8 +879,8 @@ end generate gen_pulse_cnt;
en_i => '1',
trig_a_i => trig_pgen(i),
trig_r_edge_p_i => trig_chan_redge_p(i),
trig_f_edge_p_i => trig_chan_fedge_p(i),
trig_r_edge_p_i => trig_chan_redge_p(i),
trig_f_edge_p_i => trig_chan_fedge_p(i),
pulse_err_p_o => pulse_outp_err_sh_p (i),
......@@ -876,63 +889,63 @@ end generate gen_pulse_cnt;
pulse_f_edge_p_o => pulse_f_edge_sh_p(i)
);
----------------------------------------------------------------------------------
-- Instantiate burst control block for the channel
cmp_burst_ctrl_sh : conv_dyn_burst_ctrl
generic map
(
g_pwidth => g_pgen_pwidth_sh,
g_temp_decre_step => g_temp_decre_step_sh,
g_1_pulse_temp_rise => g_burstctrl_1_pulse_temp_rise_sh,
g_max_temp => g_burstctrl_max_temp_lg_sh
)
port map
(
clk_i => clk_20_i,
rst_n_i => rst_20_n,
en_i => '1',
pulse_burst_i => pulse_outp_sh(i),
pulse_r_edge_p_i => pulse_r_edge_sh_p(i),
pulse_f_edge_p_i => pulse_f_edge_sh_p(i),
temp_rise_o => temp_rise_c_sh(i),
pulse_burst_o => burst_outp_sh(i),
burst_err_p_o => burst_outp_err_sh_p(i)
);
----------------------------------------------------------------------
--Select output depending on mode of operation.
----------------------------------------------------------------------
pulse_outp (i) <= (burst_outp_lg(i) and pulse_width_sel_n_i) or
(burst_outp_sh(i) and not pulse_width_sel_n_i)
when burst_en_n = '0'
else pulse_outp_cont(i);
----------------------------------------------------------------------
--Generate error pulses depending on mode of operation
----------------------------------------------------------------------
-- flim_pmisse_p gives out a pulse when a pulse is missed because its
-- frequency is above the set maximum frequency
flim_pmisse_p (i) <= (pulse_outp_err_lg_p(i) and pulse_width_sel_n_i) or
(pulse_outp_err_sh_p(i) and not pulse_width_sel_n_i)
when burst_en_n = '0'
else pulse_outp_err_cont(i) ;
----------------------------------------------------------------------------------
-- Instantiate burst control block for the channel
cmp_burst_ctrl_sh : conv_dyn_burst_ctrl
generic map
(
g_pwidth => g_pgen_pwidth_sh,
g_temp_decre_step => g_temp_decre_step_sh,
g_1_pulse_temp_rise => g_burstctrl_1_pulse_temp_rise_sh,
g_max_temp => g_burstctrl_max_temp_lg_sh
)
port map
(
clk_i => clk_20_i,
rst_n_i => rst_20_n,
en_i => '1',
pulse_burst_i => pulse_outp_sh(i),
pulse_r_edge_p_i => pulse_r_edge_sh_p(i),
pulse_f_edge_p_i => pulse_f_edge_sh_p(i),
temp_rise_o => temp_rise_c_sh(i),
pulse_burst_o => burst_outp_sh(i),
burst_err_p_o => burst_outp_err_sh_p(i)
);
----------------------------------------------------------------------
--Select output depending on mode of operation.
----------------------------------------------------------------------
pulse_outp (i) <= (burst_outp_lg(i) and pulse_width_sel_n_i) or
(burst_outp_sh(i) and not pulse_width_sel_n_i)
when burst_en_n = '0'
else pulse_outp_cont(i);
----------------------------------------------------------------------
--Generate error pulses depending on mode of operation
----------------------------------------------------------------------
-- flim_pmisse_p gives out a pulse when a pulse is missed because its
-- frequency is above the set maximum frequency
flim_pmisse_p (i) <= (pulse_outp_err_lg_p(i) and pulse_width_sel_n_i) or
(pulse_outp_err_sh_p(i) and not pulse_width_sel_n_i)
when burst_en_n = '0'
else pulse_outp_err_cont(i) ;
-- fwdg_pmisse_p gives out a pulse when a pulse is cutoff because the
-- frequency watchdog only supports a high frequency for a limited period
fwdg_pmisse_p (i) <= (burst_outp_err_lg_p(i) and pulse_width_sel_n_i) or
(burst_outp_err_sh_p(i) and not pulse_width_sel_n_i)
when burst_en_n = '0'
else '0' ;
pmisse_p (i) <= flim_pmisse_p (i) or fwdg_pmisse_p (i);
-----------------------------------------------------------------------
-- frequency watchdog only supports a high frequency for a limited period
fwdg_pmisse_p (i) <= (burst_outp_err_lg_p(i) and pulse_width_sel_n_i) or
(burst_outp_err_sh_p(i) and not pulse_width_sel_n_i)
when burst_en_n = '0'
else '0' ;
pmisse_p (i) <= flim_pmisse_p (i) or fwdg_pmisse_p (i);
-----------------------------------------------------------------------
-- Process to flash pulse LED when a pulse is output
-- LED flash length: 26 ms
p_pulse_led : process (clk_20_i) is
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
pulse_outp_d0(i) <= '0';
pulse_outp_d0(i) <= '0';
pulse_outp_redge_p(i) <= '0';
led_pulse_cnt(i) <= (others => '0');
led_pulse(i) <= '0';
......@@ -1308,23 +1321,23 @@ end generate gen_line_unused_chans;
if rising_edge(clk_20_i) then
for i in 0 to g_nr_chans-1 loop
if (rst_20_n = '0') then
flim_pmisse_bit(i) <= '0';
fwdg_pmisse_bit (i)<= '0';
pmisse_bit(i) <= '0';
flim_pmisse_bit(i) <= '0';
fwdg_pmisse_bit (i)<= '0';
pmisse_bit(i) <= '0';
elsif (pmisse_p(i) = '1') then
if flim_pmisse_p (i) = '1' then
flim_pmisse_bit(i)<= '1';
end if;
if fwdg_pmisse_p (i) = '1' then
fwdg_pmisse_bit(i) <= '1';
end if;
if flim_pmisse_p (i) = '1' then
flim_pmisse_bit(i)<= '1';
end if;
if fwdg_pmisse_p (i) = '1' then
fwdg_pmisse_bit(i) <= '1';
end if;
else
if (flim_pmisse_bit_rst_ld = '1') and (flim_pmisse_bit_rst(i) = '1') then
flim_pmisse_bit(i) <= '0';
end if;
if (fwdg_pmisse_bit_rst_ld = '1') and (fwdg_pmisse_bit_rst(i) = '1') then
fwdg_pmisse_bit(i) <= '0';
end if;
if (flim_pmisse_bit_rst_ld = '1') and (flim_pmisse_bit_rst(i) = '1') then
flim_pmisse_bit(i) <= '0';
end if;
if (fwdg_pmisse_bit_rst_ld = '1') and (fwdg_pmisse_bit_rst(i) = '1') then
fwdg_pmisse_bit(i) <= '0';
end if;
end if;
pmisse_bit(i) <= flim_pmisse_bit(i) or fwdg_pmisse_bit(i);
end loop;
......@@ -1514,7 +1527,7 @@ end generate gen_latest_timestamp_unused_chans;
reg_ch6ttlpcr_i => std_logic_vector(ttl_pulse_cnt(5)),
reg_ch6ttlpcr_load_o => ch_ttl_pcr_ld(5),
reg_ch1blopcr_o => ch_blo_pcr(0),
reg_ch1blopcr_o => ch_blo_pcr(0),
reg_ch1blopcr_i => std_logic_vector(blo_pulse_cnt(0)),
reg_ch1blopcr_load_o => ch_blo_pcr_ld(0),
reg_ch2blopcr_o => ch_blo_pcr(1),
......@@ -1532,7 +1545,7 @@ end generate gen_latest_timestamp_unused_chans;
reg_ch6blopcr_o => ch_blo_pcr(5),
reg_ch6blopcr_i => std_logic_vector(blo_pulse_cnt(5)),
reg_ch6blopcr_load_o => ch_blo_pcr_ld(5),
reg_tvlr_o => tvlr,
reg_tvlr_i => tm_tai(31 downto 0),
reg_tvlr_load_o => tvlr_ld,
......@@ -1587,9 +1600,9 @@ end generate gen_latest_timestamp_unused_chans;
reg_oswr_switches_i => sw_other_i,
reg_uidlr_i => id (31 downto 0),
reg_uidhr_i => id (63 downto 32),
reg_uidlr_i => id (31 downto 0),
reg_uidhr_i => id (63 downto 32),
reg_tempr_i => temper
);
......@@ -1626,8 +1639,8 @@ end generate gen_latest_timestamp_unused_chans;
id_o => tmp_id,
temper_o => tmp_temper,
id_read_o => onewire_read_p,
id_ok_o => open
);
id_ok_o => open
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- pps generator based on the 20 MHz clk
......
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