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Commit 07f48154 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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deleted unused vhd files in modules

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--==============================================================================
-- CERN (BE-CO-HT)
-- Burst mode control module
--==============================================================================
--
-- author: Denia Bouhired (denia.bouhired@cern.ch)
--
-- Date of creation: 19-09-2016
--
-- version: 1.0
--
-- description:
-- This module serves as a burst mode controller. When pulses of pre-defined length (250 ns) arrive, this module evaluates whether the module needs some "cool-off" time every burst_length number of pulses. Burst-length is the maximum number of pulses the board can handle at maximum frequency 2MHz and is determined through direct laboratory measurements on board prototypes. It is considered a pure hardware limitation. For version 1 this is set to absolute maximum of 1000 but the generic value can be changed for lower values.
-- dependencies:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 19-09-2016 Denia Bouhired File created.
--
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- use work.gencores_pkg.all;
-- use work.wishbone_pkg.all;
use work.conv_common_gw_pkg.all;
entity conv_burst_ctrl is
generic
(
-- Short pulse width, in number of clk_i cycles
-- Default short pulse width (20 MHz clock): 250 ns = 5 clk cycles
g_pwidth : natural range 2 to 40 := 5;
-- Duty cycle divider: D = 1/g_duty_cycle_div
g_duty_cycle_div : natural := 200;
-- Number of pulses allowed before decision is made on whether to continue burst
-- Maximum number of pulses that can be received at the worst case 2MHz scenario
g_max_burst_len : natural := 1000; -- Check every "g_eval_burst_len" pulses
-- Burst is evaluated after g_max_burst_len or after a timeout g_burst_timeout set to 1 s.
--g_cnt_size : natural := 32;
g_burst_timeout : natural := 200000 -- 20000000 corresponds to 1 second timeout
-- 60000 corresponds to 3ms timeout
);
port
(
-- Clock and active-low reset inputs
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Enable input, pulse generation is enabled when '1'
en_i : in std_logic;
pulse_burst_i : in std_logic;
pulse_burst_o : out std_logic;
-- Burst error output, pulses high for one clock cycle when a pulse arrives
-- within a burst rejection phase
burst_err_p_o : out std_logic
);
end entity conv_burst_ctrl;
architecture behav of conv_burst_ctrl is
--============================================================================
-- Type declarations
--============================================================================
type t_state is (
IDLE, --Idle state wait for pulse to arrive
GEN_PULSE_ON, --Continue generating pulses and counting them
GEN_PULSE_OFF, --And count pulse OFF time
REJ_PULSE --Reject pulses and start cool-off period
);
--============================================================================
-- Constant declarations
--============================================================================
-- This bit can be done by adding second counter to count pulse on time
constant c_average_pulse_off : natural := (g_duty_cycle_div)*g_pwidth; -- 250 ns * (200)
constant c_max_burst_rej : natural := g_max_burst_len*c_average_pulse_off; -- (250ns * (200)) *1000
--============================================================================
-- Function and procedure declarations
--============================================================================
--============================================================================
-- Signal declarations
--============================================================================
signal burst_ctrl_rst : std_logic;
-- Pulse burst trigger
signal pulse_train_in : std_logic;
--signal pulse_redge_p : std_logic;
--signal pulse_burst_sf : std_logic;
-- Pulse, pulse ON/OFF, burst length counters
signal pulse_cnt : unsigned(31 downto 0); -- Pulse counter
---signal cumul_pulse_on_c : unsigned(g_cnt_size-1 downto 0); -- Cumulative PULSE ON counter
---signal cumul_pulse_off_c : unsigned(g_cnt_size-1 downto 0); -- Cumulative PULSE OFF counter
signal cumul_burst_time : unsigned(31 downto 0); -- Cumulative burst time (ON and OFF)
signal burst_rq_off_c : unsigned(31 downto 0); -- Required rejection time for current burst
-- Flag new pulse
signal new_pulse : boolean;
--Flag burst rejection
--signal rej_active : boolean;
-- FSM signal
signal state : t_state;
signal nxt_state : t_state;
signal pulse_train_in_d0 : std_logic;
signal pulse_train_in_r_edge_p : std_logic;
--==============================================================================
-- architecture begin
--==============================================================================
begin
-- Generate the pulse on rising edge of pulse_burst_i
p_pulse_redge: process (burst_ctrl_rst, pulse_burst_i, en_i)
begin
if (burst_ctrl_rst = '1') then
pulse_train_in <= '0';
else
-- if (en_i = '1') then
pulse_train_in <= pulse_burst_i;
-- end if;
end if;
end process p_pulse_redge;
p_pulse_redge_detect : process (clk_i) is
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
pulse_train_in_d0 <= '0';
pulse_train_in_r_edge_p <= '0';
else
pulse_train_in_d0 <= pulse_burst_i;
pulse_train_in_r_edge_p <= pulse_burst_i and (not pulse_train_in_d0);
end if;
end if;
end process p_pulse_redge_detect;
-- Synchronize the trigger in clk_i domain
-- cmp_sync_ffs : gc_sync_ffs
-- generic map
-- (
-- g_sync_edge => "positive"
-- )
-- port map
-- (
-- clk_i => clk_i,
-- rst_n_i => rst_n_i,
-- data_i => pulse_burst,
-- ppulse_o => pulse_redge_p
-- );
--pulse_redge_p <= pulse_burst;
-- process (clk_i)
-- begin
-- if rising_edge(clk_i) then
pulse_burst_o <= pulse_train_in;
-- end if;
-- end process;
--============================================================================
-- Burst length adjustment logic
--============================================================================
--Synchronous procees to define state conditions
p_fsm_transitions: process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
state <= IDLE;
elsif (en_i = '1') then
state <= nxt_state;
end if;
end if;
end process;
-- FSM States
p_FSM_states: process(state, pulse_train_in, cumul_burst_time, pulse_cnt, burst_rq_off_c)
begin
case state is
---------------------------------------------------------------------
-- IDLE
---------------------------------------------------------------------
-- Clear all values and go to pulse generation state when the
-- appropriate input arrives
---------------------------------------------------------------------
when IDLE =>
if (pulse_train_in = '1') then
nxt_state <= GEN_PULSE_ON;
else
nxt_state <= state;
end if;
---------------------------------------------------------------------
-- GEN_PULSE_ON
---------------------------------------------------------------------
-- When a new pulse arrives increment the pulse ON cycle counter and the pulse ON counter
-- Got to GEN_PULSE_OFF state when the pulse is OFF
---------------------------------------------------------------------
when GEN_PULSE_ON =>
if (pulse_train_in = '1') then
nxt_state <= state;
else
nxt_state <= GEN_PULSE_OFF;
end if;
---------------------------------------------------------------------
-- GEN_PULSE_OFF
---------------------------------------------------------------------
-- Count the number of cycles of pulse OFF
-- Go to GEN_PULSE_ON state when new pulse arrives
-- If the maximum number of pulses per burst is reached, go to REJ_PULSE state
-- If the the burst time out is reached got to TIMEOUT state
---------------------------------------------------------------------
when GEN_PULSE_OFF =>
-- If maximum number of consecutive pulses is reached start rejection phase
if (pulse_cnt = g_max_burst_len or cumul_burst_time >= g_burst_timeout) then
if (cumul_burst_time < burst_rq_off_c) then
nxt_state <= REJ_PULSE;
else
nxt_state <= IDLE;
end if;
elsif (pulse_train_in = '1' ) then
nxt_state <= GEN_PULSE_ON;
end if;
---------------------------------------------------------------------
-- REJ_PULSE
---------------------------------------------------------------------
-- Start pulse rejection until c_max_burst_rej time is reached
-- the go back to IDLE state
---------------------------------------------------------------------
when REJ_PULSE =>
if (cumul_burst_time >= burst_rq_off_c) then
nxt_state <= IDLE;
else
nxt_state <= state;
end if;
when others =>
nxt_state <= IDLE;
end case;
end process p_FSM_states;
-- FSM Outputs
p_FSM_outputs: process(clk_i)
begin
if rising_edge (clk_i) then
case state is
---------------------------------------------------------------------
-- IDLE
---------------------------------------------------------------------
-- Clear all values and go to pulse generation state when the
-- appropriate input arrives
---------------------------------------------------------------------
when IDLE =>
pulse_cnt <= (others => '0');
cumul_burst_time <= (others => '0');
burst_rq_off_c <= (others => '0');
burst_ctrl_rst <= '0';
new_pulse <= false;
--rej_active <= false;
if (pulse_train_in = '1') then
cumul_burst_time <= cumul_burst_time + 1;
new_pulse <= true;
end if;
---------------------------------------------------------------------
-- GEN_PULSE_ON
---------------------------------------------------------------------
-- When a new pulse arrives increment the pulse ON cycle counter and the pulse ON counter
-- Got to GEN_PULSE_OFF state when the pulse is OFF
---------------------------------------------------------------------
when GEN_PULSE_ON =>
cumul_burst_time <= cumul_burst_time + 1;
if (new_pulse) then -- count only new pulses, once
pulse_cnt <= pulse_cnt + 1;
new_pulse <= false; -- A new pulse has already been counted
burst_rq_off_c <= burst_rq_off_c + c_average_pulse_off;
end if;
---------------------------------------------------------------------
-- GEN_PULSE_OFF
---------------------------------------------------------------------
-- Count the number of cycles of pulse OFF
-- Go to GEN_PULSE_ON state when new pulse arrives
-- If the maximum number of pulses per burst is reached, go to REJ_PULSE state
-- If the the burst time out is reached got to TIMEOUT state
---------------------------------------------------------------------
when GEN_PULSE_OFF =>
cumul_burst_time <= cumul_burst_time + 1;
-- If maximum number of consecutive pulses is reached start rejection phase
if (pulse_cnt = g_max_burst_len or cumul_burst_time >= g_burst_timeout) then
if (cumul_burst_time < burst_rq_off_c) then
burst_ctrl_rst <= '1';
end if;
elsif (pulse_train_in = '1' ) then
new_pulse <= true;
end if;
---------------------------------------------------------------------
-- REJ_PULSE
---------------------------------------------------------------------
-- Start pulse rejection until c_max_burst_rej time is reached
-- the go back to IDLE state
---------------------------------------------------------------------
when REJ_PULSE =>
if (cumul_burst_time >= burst_rq_off_c) then
burst_ctrl_rst <= '0';
else
cumul_burst_time <= cumul_burst_time + 1;
end if;
-- Error pulse is generated for one clock cycle each time a pulse arrives during rejection mode
burst_err_p_o <= '0';
if pulse_train_in_r_edge_p = '1' then
burst_err_p_o <= '1';
end if;
end case;
end if;
end process p_FSM_outputs;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
modules/conv_burst_ctrl_v1.vhd deleted 100644 → 0
View file @ a3ecf6f4
--==============================================================================
-- CERN (BE-CO-HT)
-- Burst mode control module
--==============================================================================
--
-- author: Denia Bouhired (denia.bouhired@cern.ch)
--
-- Date of creation: 19-09-2016
--
-- version: 1.0
--
-- description:
-- This module serves as a burst mode controller. When pulses of pre-defined length (250 ns) arrive, this module evaluates whether the module needs some "cool-off" time every burst_length number of pulses. Burst-length is the maximum number of pulses the board can handle at maximum frequency 2MHz and is determined through direct laboratory measurements on board prototypes. It is considered a pure hardware limitation. For version 1 this is set to absolute maximum of 1000 but the generic value can be changed for lower values.
-- dependencies:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 19-09-2016 Denia Bouhired File created.
--
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.conv_common_gw_pkg.all;
entity conv_burst_ctrl is
generic
(
-- Short pulse width, in number of clk_i cycles
-- Default short pulse width (20 MHz clock): 250 ns = 5 clk cycles
g_pwidth : natural range 2 to 40 := 5;
-- Duty cycle divider: D = 1/g_duty_cycle_div
g_duty_cycle_div : natural := 200;
-- Number of pulses allowed before decision is made on whether to continue burst
-- Maximum number of pulses that can be received at the worst case 2MHz scenario
g_max_burst_len : natural := 1000; -- Check every "g_eval_burst_len" pulses
-- Burst is evaluated after g_max_burst_len or after a timeout g_burst_timeout set to 1 s.
--g_cnt_size : natural := 32;
g_burst_timeout : natural := 200000 -- 20000000 corresponds to 1 second timeout
-- 60000 corresponds to 3ms timeout
);
port
(
-- Clock and active-low reset inputs
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Enable input, pulse generation is enabled when '1'
en_i : in std_logic;
pulse_burst_i : in std_logic;
pulse_burst_o : out std_logic;
-- Burst error output, pulses high for one clock cycle when a pulse arrives
-- within a burst rejection phase
burst_err_p_o : out std_logic
);
end entity conv_burst_ctrl;
architecture behav of conv_burst_ctrl is
--============================================================================
-- Type declarations
--============================================================================
type t_state is (
IDLE, --Idle state wait for pulse to arrive
GEN_PULSE_ON, --Continue generating pulses and counting them
GEN_PULSE_OFF, --And count pulse OFF time
REJ_PULSE --Reject pulses and start cool-off period
);
--============================================================================
-- Constant declarations
--============================================================================
-- This bit can be done by adding second counter to count pulse on time
constant c_average_pulse_off : natural := (g_duty_cycle_div)*g_pwidth; -- 250 ns * (200)
constant c_max_burst_rej : natural := g_max_burst_len*c_average_pulse_off; -- (250ns * (200)) *1000
--============================================================================
-- Function and procedure declarations
--============================================================================
--============================================================================
-- Signal declarations
--============================================================================
signal burst_ctrl_rst : std_logic;
-- Pulse burst trigger
signal pulse_train_in : std_logic;
--signal pulse_redge_p : std_logic;
--signal pulse_burst_sf : std_logic;
-- Pulse, pulse ON/OFF, burst length counters
signal pulse_cnt : unsigned(31 downto 0); -- Pulse counter
---signal cumul_pulse_on_c : unsigned(g_cnt_size-1 downto 0); -- Cumulative PULSE ON counter
---signal cumul_pulse_off_c : unsigned(g_cnt_size-1 downto 0); -- Cumulative PULSE OFF counter
signal cumul_burst_time : unsigned(31 downto 0); -- Cumulative burst time (ON and OFF)
signal burst_rq_off_c : unsigned(31 downto 0); -- Required rejection time for current burst
-- Flag new pulse
signal new_pulse : boolean;
--Flag burst rejection
signal rej_active : boolean;
-- FSM signal
signal state : t_state;
--==============================================================================
-- architecture begin
--==============================================================================
begin
-- Generate the pulse on rising edge of pulse_burst_i
p_pulse_redge: process(burst_ctrl_rst, pulse_burst_i)
begin
if (burst_ctrl_rst = '1') then
pulse_train_in <= '0';
elsif rising_edge(pulse_burst_i) then
if (en_i = '1' and not rej_active) then
pulse_train_in <= pulse_burst_i;
burst_err_p_o <= '0';
else
pulse_train_in <= '0';
burst_err_p_o <= '1';
end if;
else
pulse_train_in <= '0';
burst_err_p_o <= '0';
end if;
end process p_pulse_redge;
-- Synchronize the trigger in clk_i domain
-- cmp_sync_ffs : gc_sync_ffs
-- generic map
-- (
-- g_sync_edge => "positive"
-- )
-- port map
-- (
-- clk_i => clk_i,
-- rst_n_i => rst_n_i,
-- data_i => pulse_burst,
-- ppulse_o => pulse_redge_p
-- );
--pulse_redge_p <= pulse_burst;
process (clk_i)
begin
if rising_edge(clk_i) then
pulse_burst_o <= pulse_train_in;
end if;
end process;
--============================================================================
-- Burst length adjustment logic
--============================================================================
-- Generate FSM logic
p_burst_length: process(clk_i)
begin
if rising_edge (clk_i) then -- ***CHECK WHAT ELSE NEEDS TO BE RESET
if (rst_n_i = '0') then
state <= IDLE;
burst_ctrl_rst <= '1';
--pulse_burst_sf <= '0';
pulse_cnt <= (others => '0');
---cumul_pulse_on_c <= (others => '0');
---cumul_pulse_off_c <= (others => '0');
cumul_burst_time <= (others => '0');
burst_rq_off_c <= (others => '0');
new_pulse <= false;
rej_active <= false;
--burst_err_p_o <= '0';
elsif (en_i = '1') then
--pulse_burst_sf <= pulse_burst;
case state is
---------------------------------------------------------------------
-- IDLE
---------------------------------------------------------------------
-- Clear all values and go to pulse generation state when the
-- appropriate input arrives
---------------------------------------------------------------------
when IDLE =>
--pulse_burst_sf <= pulse_burst;
pulse_cnt <= (others => '0');
---cumul_pulse_on_c <= (others => '0');
---cumul_pulse_off_c <= (others => '0');
cumul_burst_time <= (others => '0');
burst_rq_off_c <= (others => '0');
burst_ctrl_rst <= '0';
rej_active <= false;
if (pulse_train_in = '1') then
new_pulse <= true;
state <= GEN_PULSE_ON;
---cumul_pulse_on_c <= cumul_pulse_on_c + 1;
cumul_burst_time <= cumul_burst_time + 1;
end if;
---------------------------------------------------------------------
-- GEN_PULSE_ON
---------------------------------------------------------------------
-- When a new pulse arrives increment the pulse ON cycle counter and the pulse ON counter
-- Got to GEN_PULSE_OFF state when the pulse is OFF
---------------------------------------------------------------------
when GEN_PULSE_ON =>
----cumul_burst_time <= cumul_pulse_on_c + cumul_pulse_off_c + 1;
cumul_burst_time <= cumul_burst_time + 1;
if (pulse_train_in = '1') then
---cumul_pulse_on_c <= cumul_pulse_on_c + 1;
if (new_pulse) then -- count only new pulses, once
pulse_cnt <= pulse_cnt + 1;
new_pulse <= false; -- A new pulse has already been counted
burst_rq_off_c <= burst_rq_off_c + c_average_pulse_off;
end if;
else
state <= GEN_PULSE_OFF;
---cumul_pulse_off_c <= cumul_pulse_off_c + 1;
end if;
---------------------------------------------------------------------
-- GEN_PULSE_OFF
---------------------------------------------------------------------
-- Count the number of cycles of pulse OFF
-- Go to GEN_PULSE_ON state when new pulse arrives
-- If the maximum number of pulses per burst is reached, go to REJ_PULSE state
-- If the the burst time out is reached got to TIMEOUT state
---------------------------------------------------------------------
when GEN_PULSE_OFF =>
----cumul_burst_time <= cumul_pulse_on_c + cumul_pulse_off_c + 1;
cumul_burst_time <= cumul_burst_time + 1;
if (pulse_train_in = '1' ) then
new_pulse <= true; --waiting for new pulse
state <= GEN_PULSE_ON;
---cumul_pulse_on_c <= cumul_pulse_on_c + 1;
-- If maximum number of consecutive pulses is reached start rejection phase
elsif (pulse_cnt = g_max_burst_len or cumul_burst_time >= g_burst_timeout) then
if (cumul_burst_time < burst_rq_off_c) then
rej_active <= true;
state <= REJ_PULSE;
end if;
else
---cumul_pulse_off_c <= cumul_pulse_off_c + 1;
end if;
---------------------------------------------------------------------
-- REJ_PULSE
---------------------------------------------------------------------
-- Start pulse rejection until c_max_burst_rej time is reached
-- the go back to IDLE state
---------------------------------------------------------------------
when REJ_PULSE =>
if (cumul_burst_time >= burst_rq_off_c) then
rej_active <= false;
state <= IDLE;
else
cumul_burst_time <= cumul_burst_time + 1;
end if;
when others =>
state <= IDLE;
end case;
end if;
end if;
end process p_burst_length;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
modules/conv_dyn_burst_ctrl_long_pulse.vhd deleted 100644 → 0
View file @ a3ecf6f4
--==============================================================================
-- CERN (BE-CO-HT)
-- Burst mode control module
--==============================================================================
--
-- author: Denia Bouhired (denia.bouhired@cern.ch)
--
-- Date of creation: 19-09-2016
--
-- version: 1.0
--
-- description:
-- This module serves as a burst mode controller. When pulses of pre-defined length (250 ns) arrive, this module evaluates whether the module needs some "cool-off" time every burst_length number of pulses. Burst-length is the maximum number of pulses the board can handle at maximum frequency 2MHz and is determined through direct laboratory measurements on board prototypes. It is considered a pure hardware limitation. For version 1 this is set to absolute maximum of 1000 but the generic value can be changed for lower values.
-- dependencies:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 19-09-2016 Denia Bouhired File created.
-- 11-01-2017 Denia Bouhired Small modifications to improve code.
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.conv_common_gw_pkg.all;
entity conv_dyn_burst_ctrl is
generic
(
-- Fixed pulse width set to 5 clock cycles = 5* 50ns = 250 ns
g_pwidth : natural range 2 to 40 := 5;
-- Scaled temperature rise resulting from single pulse. This number can be defined empirically or derived from temperature measurements on the board.
g_1_pulse_temp_rise :in unsigned (19 downto 0) := x"0A410";
-- Scaled maximum temperature ceiling before pulse inhibition is necessary to lower temperature
--g_max_temp :in unsigned (39 downto 0) := x"174876E800"
g_max_temp :in unsigned (39 downto 0) := x"00000186A0"--100000
);
port
(
-- Clock and active-low reset inputs
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Enable input, pulse generation is enabled when '1'
en_i : in std_logic;
--Input pulse burst or pulse train
pulse_burst_i : in std_logic;
--Dynamically controlled ouput pulse train.
pulse_burst_o : out std_logic;
-- output used for debugging. OUGHT TO BE DELETED
temp_rise_c : out unsigned (39 downto 0) ;
-- Burst error output, pulses high for one clock cycle when a pulse arrives
-- within a burst rejection phase
burst_err_p_o : out std_logic
);
end entity conv_dyn_burst_ctrl;
architecture behav of conv_dyn_burst_ctrl is
type t_temp_decre is array (0 to 14) of integer;
--============================================================================
-- Function and procedure declarations
--============================================================================
function f_temp_resolution (pwidth : natural) return natural is
begin
if pwidth = 5 then --250ns wide pulses
return 5;
else
return 24; --1.2us wide pulses
end if;
end function f_temp_resolution;
--============================================================================
-- Signal declarations
--============================================================================
--signal temp_decre : t_temp_decre := (0, 769, 31, 104, 14, 82,0,0);
signal temp_decre : t_temp_decre := (0,0,0,0,0,0,0,5750,100,79,13,12,4,5,13);
signal burst_ctrl_rst : std_logic;
signal pulse_train_in : std_logic;
signal temp_rise : unsigned (39 downto 0) ;
signal test : integer ;
signal temp_fall : unsigned (39 downto 0) ;
signal single_cycle_cnt : integer;
signal n_cycle_cnt : integer;
signal pulse_train_in_d0 : std_logic;
signal pulse_train_in_r_edge_p : std_logic;
signal pulse_train_in_f_edge_p : std_logic;
constant thermal_res : natural := f_temp_resolution (g_pwidth); -- thermal resolution in clock cycles
begin
-- Generate the pulse on rising edge of pulse_burst_i
p_pulse_redge: process (burst_ctrl_rst, pulse_burst_i)
begin
--if rising_edge(clk_i) then
--TO DOooo consider moving within else statement
if (burst_ctrl_rst = '1') then
if falling_edge(pulse_burst_i) then --pulse_burst_i) then -- wait for pulse to finish before cutoff
--TODO why not use falling edge 1-clk-cycle pulse
pulse_train_in <= '0';
end if;
elsif (en_i = '1') then
pulse_train_in <= pulse_burst_i; --re-activate output only if input line is off
end if;
--end if;
--end if;
end process p_pulse_redge;
pulse_burst_o <= pulse_train_in; --copy controlled input burst to output
temp_rise_c <= temp_rise; --TODO to delete as output is not really necessary
-- TODO is it necessary since pulse should already be synchronised to clock domain?/
p_pulse_redge_detect : process (clk_i) is
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
pulse_train_in_d0 <= '0';
pulse_train_in_r_edge_p <= '0';
elsif (en_i='1') then
pulse_train_in_d0 <= pulse_burst_i;
pulse_train_in_r_edge_p <= pulse_burst_i and (not pulse_train_in_d0);
pulse_train_in_f_edge_p <= (not pulse_burst_i) and pulse_train_in_d0;
end if;
end if;
end process p_pulse_redge_detect;
p_n_cycle_cnt : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
single_cycle_cnt <= 1;
n_cycle_cnt <= 1;
else
if pulse_train_in_r_edge_p = '1' then --and burst_ctrl_rst = '0' then
--reset counters in the event of a new pulse
single_cycle_cnt <= 1;
n_cycle_cnt <= 1;
elsif pulse_train_in = '0' then --TODO change condition of if statement, try with falling edge
single_cycle_cnt <= single_cycle_cnt+1;
if single_cycle_cnt = thermal_res then
if n_cycle_cnt < 15 then
n_cycle_cnt <= n_cycle_cnt + 1;
end if;
single_cycle_cnt <= 1;
--temp_fall <= to_unsigned(temp_decre(n_cycle_cnt), 40);
end if;
end if;
end if;
end if;
end process p_n_cycle_cnt;
p_thermal_sim : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
temp_rise <= (others => '0');
burst_ctrl_rst <= '1';
burst_err_p_o <= '0';
else
if (temp_rise) >= 0 and ((temp_rise) <= (g_max_temp)) then
burst_err_p_o <= '0';
if pulse_train_in_f_edge_p = '1' then --wait until pulse finishes before repetition
burst_ctrl_rst <= '0';
elsif pulse_train_in_r_edge_p = '1' then --new pulse
if burst_ctrl_rst = '1' then
burst_err_p_o <= '1';
--end if;
--if burst_ctrl_rst = '0' then -- temperature less than maximum
else
temp_rise <= temp_rise + g_1_pulse_temp_rise;
--else ;
end if;
--burst_err_p_o <= '0';
--elsif signed(temp_rise) /= 0 and pulse_train_in = '0' then
elsif (temp_rise) /= 0 then --and pulse_burst_i = '0' then --temperature fall between pulses
test <= temp_decre(n_cycle_cnt-1);
if temp_rise > temp_decre(n_cycle_cnt-1) then
temp_rise <= temp_rise - to_unsigned(temp_decre(n_cycle_cnt-1), 40);
else
temp_rise <= (others => '0');
end if;
end if;
--elsif (signed(temp_rise) > signed(g_max_temp)) and pulse_train_in = '0' then -- and
elsif ((temp_rise) > (g_max_temp)) then -- and pulse_burst_i = '0' then -- and (pulse_train_in_f_edge_p = '1') then
burst_ctrl_rst <= '1';
burst_err_p_o <= '0';
if pulse_train_in_r_edge_p = '1' then
burst_err_p_o <= '1';
end if;
temp_rise <= temp_rise - temp_decre(n_cycle_cnt-1);
end if;
end if;
end if;
end process p_thermal_sim;
end architecture behav;
\ No newline at end of file
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