Commit 07d56e36 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

Added glitch filter to pulse repetition

parent 55fafcd6
......@@ -62,11 +62,14 @@ use ieee.numeric_std.all;
entity conv_pulse_gen is
generic
(
-- This generic enables elaboration of the fixed pulse width logic
g_with_fixed_pwidth : boolean;
-- Pulse width, in number of clk_i cycles
-- Default pulse width (20 MHz clock): 1.2 us
-- Minimum allowable pulse width (20 MHz clock): 1 us
-- Maximum allowable pulse width (20 MHz clock): 2 us
g_pwidth : natural range 20 to 40 := 24;
g_pwidth : natural range 20 to 40 := 24;
-- Duty cycle divider: D = 1/g_duty_cycle_div
g_duty_cycle_div : natural := 5
......@@ -186,6 +189,12 @@ architecture behav of conv_pulse_gen is
--==============================================================================
begin
gen_without_fixed_pwidth : if (g_with_fixed_pwidth = false) generate
pulse_o <= trig_a_i;
pulse_err_p_o <= '0';
end generate gen_without_fixed_pwidth;
gen_with_fixed_pwidth : if (g_with_fixed_pwidth = true) generate
--============================================================================
-- Output logic
--============================================================================
......@@ -379,6 +388,8 @@ begin
end if;
end process p_pulse_width;
end generate gen_with_fixed_pwidth;
end architecture behav;
--==============================================================================
-- architecture end
......
......@@ -59,6 +59,17 @@ entity conv_common_gw is
(
-- Number of repeater channels
g_nr_chans : integer := 6;
g_nr_inv_chans : integer := 4;
-- Generate pulse repetition logic with fixed output pulse width
g_pgen_fixed_width : boolean;
-- Pulse width at pulse generator output (fixed output pulse width only)
g_pgen_pwidth : natural range 20 to 40 := 24;
-- Duty cycle divider ratio for pulse generator
-- output pulse will be limited to 1/g_pgen_duty_cycle_div
g_pgen_duty_cycle_div : natural := 5;
-- Pulse generator glitch filter length in number of clk_20_i cycles
g_pgen_gf_len : integer := 4;
-- Bicolor LED controller signals
g_bicolor_led_columns : integer := 6;
......@@ -74,6 +85,29 @@ entity conv_common_gw is
-- Reset output signal, synchronous to 20 MHz clock
rst_n_o : out std_logic;
-- Glitch filter active-low enable signal
gf_en_n_i : in std_logic;
-- Channel enable
global_ch_oen_o : out std_logic;
pulse_front_oen_o : out std_logic;
pulse_rear_oen_o : out std_logic;
inv_oen_o : out std_logic;
-- Front panel channels
pulse_front_i : in std_logic_vector(g_nr_chans-1 downto 0);
pulse_front_o : out std_logic_vector(g_nr_chans-1 downto 0);
inv_i : in std_logic_vector(g_nr_inv_chans-1 downto 0);
inv_o : out std_logic_vector(g_nr_inv_chans-1 downto 0);
-- Rear panel channels
pulse_rear_i : in std_logic_vector(g_nr_chans-1 downto 0);
pulse_rear_o : out std_logic_vector(g_nr_chans-1 downto 0);
-- Channel leds
led_front_o : out std_logic_vector(g_nr_chans-1 downto 0);
led_rear_o : out std_logic_vector(g_nr_chans-1 downto 0);
-- Bicolor LED signals
bicolor_led_state_i : in std_logic_vector(2*g_bicolor_led_columns*g_bicolor_led_lines-1 downto 0);
bicolor_led_col_o : out std_logic_vector(g_bicolor_led_columns-1 downto 0);
......@@ -88,6 +122,9 @@ architecture arch of conv_common_gw is
--============================================================================
-- Type declarations
--============================================================================
type t_pulse_led_cnt is array(0 to g_nr_chans-1) of unsigned(18 downto 0);
type t_pulse_cnt is array(0 to g_nr_chans-1) of unsigned(31 downto 0);
type t_ch_pcr is array(0 to g_nr_chans-1) of std_logic_vector(31 downto 0);
--============================================================================
-- Constant declarations
......@@ -148,13 +185,71 @@ architecture arch of conv_common_gw is
);
end component conv_reset_gen;
component conv_pulse_gen is
generic
(
-- This generic enables elaboration of the fixed pulse width logic
g_with_fixed_pwidth : boolean;
-- Pulse width, in number of clk_i cycles
-- Default pulse width (20 MHz clock): 1.2 us
-- Minimum allowable pulse width (20 MHz clock): 1 us
-- Maximum allowable pulse width (20 MHz clock): 2 us
g_pwidth : natural range 20 to 40 := 24;
-- Duty cycle divider: D = 1/g_duty_cycle_div
g_duty_cycle_div : natural := 5
);
port
(
-- Clock and active-low reset inputs
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Glitch filter enable input
-- '1' - Glitch filter disabled (glitch-sensitive, no output jitter)
-- '0' - Glitch filter enabled (glitch-insensitive, with output jitter)
gf_en_n_i : in std_logic;
-- Enable input, pulse generation is enabled when '1'
en_i : in std_logic;
-- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays.
trig_a_i : in std_logic;
-- Pulse error output, pulses high for one clock cycle when a pulse arrives
-- within a pulse period
pulse_err_p_o : out std_logic;
-- Pulse output, active-high
-- latency:
-- glitch filter disabled: none
-- glitch filter enabled: glitch filter length + 5 clk_i cycles
pulse_o : out std_logic
);
end component conv_pulse_gen;
--============================================================================
-- Signal declarations
--============================================================================
-- Per-domain clock and reset signals
signal clk_125 : std_logic;
signal rst_125_n : std_logic;
signal rst_20_n : std_logic;
signal clk_125 : std_logic;
signal rst_125_n : std_logic;
signal rst_20_n : std_logic;
-- Pulse logic signals
signal trig_a : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_synced : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_degl : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_chan : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_pgen : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_d0 : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_redge_p : std_logic_vector(g_nr_chans-1 downto 0);
signal led_pulse : std_logic_vector(g_nr_chans-1 downto 0);
signal led_pulse_cnt : t_pulse_led_cnt;
--==============================================================================
-- architecture begin
......@@ -181,6 +276,128 @@ begin
-- Output reset signal is synchronous to the 20 MHz clock
rst_n_o <= rst_20_n;
--============================================================================
-- Output enable logic
--============================================================================
global_ch_oen_o <= '1';
pulse_front_oen_o <= '1';
inv_oen_o <= '1';
pulse_rear_oen_o <= '1';
--============================================================================
-- Pulse repetition logic
--============================================================================
trig_a <= pulse_front_i or pulse_rear_i;
gen_pulse_chan_logic : for i in 0 to g_nr_chans-1 generate
-- Synchronize the asynchronous trigger input into the 20 MHz clock
-- domain before passing it to the glitch filter
--
-- Reset value is '1' to avoid pulses being counted by pulse counter on
-- startup, when the board is in TTL-BAR repetition mode.
cmp_trig_sync : gc_sync_ffs
generic map
(
g_sync_edge => "positive"
)
port map
(
clk_i => clk_20_i,
rst_n_i => '1',
data_i => trig_a(i),
synced_o => trig_synced(i)
);
-- Deglitch synchronized trigger signal
--
-- Reset value is '1' to avoid pulses being counted by pulse counter on
-- startup, when the board is in TTL-BAR repetition mode.
cmp_inp_glitch_filt : gc_glitch_filt
generic map
(
g_len => g_pgen_gf_len
)
port map
(
clk_i => clk_20_i,
rst_n_i => '1',
dat_i => trig_synced(i),
dat_o => trig_degl(i)
);
-- Now that we have a deglitched signal, generate the MUX to select between
-- deglitched and direct channel input
trig_chan(i) <= trig_a(i) when (gf_en_n_i = '1') else
trig_degl(i);
-- The trigger to the pulse generator is multiplexed between manually triggered or
-- channel input
trig_pgen(i) <= trig_chan(i);
-- Instantiate pulse generator block for the channel
cmp_pulse_gen : conv_pulse_gen
generic map
(
g_with_fixed_pwidth => g_pgen_fixed_width,
g_pwidth => g_pgen_pwidth,
g_duty_cycle_div => g_pgen_duty_cycle_div
)
port map
(
clk_i => clk_20_i,
rst_n_i => '1',
gf_en_n_i => gf_en_n_i,
en_i => '1',
trig_a_i => trig_pgen(i),
pulse_err_p_o => open,
pulse_o => pulse_outp(i)
);
-- Process to flash pulse LED when a pulse is output
-- LED flash length: 26 ms
p_pulse_led : process (clk_20_i) is
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
pulse_outp_d0(i) <= '0';
pulse_outp_redge_p(i) <= '0';
led_pulse_cnt(i) <= (others => '0');
led_pulse(i) <= '0';
else
pulse_outp_d0(i) <= pulse_outp(i);
pulse_outp_redge_p(i) <= pulse_outp(i) and (not pulse_outp_d0(i));
case led_pulse(i) is
when '0' =>
if (pulse_outp_redge_p(i) = '1') then
led_pulse(i) <= '1';
end if;
when '1' =>
led_pulse_cnt(i) <= led_pulse_cnt(i) + 1;
if (led_pulse_cnt(i) = (led_pulse_cnt(i)'range => '1')) then
led_pulse(i) <= '0';
end if;
when others =>
led_pulse(i) <= '0';
end case;
end if;
end if;
end process p_pulse_led;
end generate gen_pulse_chan_logic;
-- Channel output assignments
pulse_front_o <= pulse_outp;
pulse_rear_o <= pulse_outp;
inv_o <= inv_i;
led_front_o <= led_pulse;
led_rear_o <= led_pulse;
--============================================================================
-- Bicolor LED matrix logic
--============================================================================
......
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