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conv-common-gw
Commit 011fbe69 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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Major changes: conv_pulse_gen.vhd has been almost completely rewritten. Also top… 

Major changes: conv_pulse_gen.vhd has been almost completely rewritten. Also top file now uses pulse periods instead of duty cycles, this is to be able to cope with none round duty cycles
parent 4b29f817
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Showing with 270 additions and 283 deletions
modules/conv_dyn_burst_ctrl.vhd
View file @ 011fbe69
...@@ -193,9 +193,10 @@ entity conv_dyn_burst_ctrl is ...@@ -193,9 +193,10 @@ entity conv_dyn_burst_ctrl is
-- i.e. temp_rise >= g_max_temp. -- i.e. temp_rise >= g_max_temp.
------------------------------------------------------------------------ ------------------------------------------------------------------------
when PULSE_REJECT => when PULSE_REJECT =>
if (pulse_f_edge_p_i = '1' and temp_rise <= g_max_temp) OR if pulse_f_edge_p_i = '1' and temp_rise <= g_max_temp then
temp_rise = 0 then
nxt_state <= PULSE_REPEAT; nxt_state <= PULSE_REPEAT;
elsif temp_rise = 0 then
nxt_state <= IDLE;
else else
nxt_state <= PULSE_REJECT; nxt_state <= PULSE_REJECT;
end if; end if;
......
modules/conv_pulse_gen.vhd
View file @ 011fbe69
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top/conv_common_gw.vhd
View file @ 011fbe69
...@@ -73,14 +73,14 @@ entity conv_common_gw is ...@@ -73,14 +73,14 @@ entity conv_common_gw is
-- Pulse width at pulse generator output (valid with fixed output pulse width) -- Pulse width at pulse generator output (valid with fixed output pulse width)
g_pgen_pwidth_lg : natural range 2 to 40 := 24; g_pgen_pwidth_lg : natural range 2 to 40 := 24;
g_pgen_pwidth_sh : natural range 2 to 40 := 5; g_pgen_pwidth_sh : natural range 2 to 40 := 5;
-- Duty cycle divider ratio for pulse generator
-- output pulse will be limited to 1/g_pgen_duty_cycle_div -- output pulse will be limited to period
--For continuous mode operation max freq 4.16kHz --For continuous mode operation max freq 4.16kHz
g_pgen_duty_cycle_div_cont : natural range 2 to 200 := 200; g_pgen_pperiod_cont : natural range 2 to 5000 := 4800;
--for LONG pulses changes maximum frequency to ~104kHz --for LONG pulses changes maximum frequency to ~104kHz
g_pgen_duty_cycle_div_lg : natural range 6 to 300 := 8; g_pgen_pperiod_lg : natural range 6 to 300 := 191;
--for SHORT pulses changes maximum frequency to ~2MHz --for SHORT pulses changes maximum frequency to ~2MHz
g_pgen_duty_cycle_div_sh : natural range 2 to 300 := 2; g_pgen_pperiod_sh : natural range 2 to 300 := 9;
-- Pulse generator glitch filter length in number of clk_20_i cycles -- Pulse generator glitch filter length in number of clk_20_i cycles
g_pgen_gf_len : integer := 4; g_pgen_gf_len : integer := 4;
...@@ -320,8 +320,7 @@ architecture arch of conv_common_gw is ...@@ -320,8 +320,7 @@ architecture arch of conv_common_gw is
signal trig_degl : std_logic_vector(g_nr_chans-1 downto 0); signal trig_degl : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_chan : std_logic_vector(g_nr_chans-1 downto 0); signal trig_chan : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_chan_redge_p : std_logic_vector(g_nr_chans-1 downto 0); signal trig_chan_redge_p : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_chan_ttl_redge_p : std_logic_vector(g_nr_chans-1 downto 0); signal trig_chan_fedge_p : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_chan_blo_redge_p : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_man : std_logic_vector(g_nr_chans-1 downto 0); signal trig_man : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_pgen : std_logic_vector(g_nr_chans-1 downto 0); signal trig_pgen : std_logic_vector(g_nr_chans-1 downto 0);
signal burst_en_n : std_logic; signal burst_en_n : std_logic;
...@@ -473,11 +472,11 @@ architecture arch of conv_common_gw is ...@@ -473,11 +472,11 @@ architecture arch of conv_common_gw is
signal CONTROL : std_logic_vector(35 downto 0); signal CONTROL : std_logic_vector(35 downto 0);
signal CLK : std_logic; signal CLK : std_logic;
signal TRIG0_in : std_logic_vector(7 downto 0); signal TRIG0_in : std_logic_vector(7 downto 0);
signal TRIG1_in : std_logic_vector(7 downto 0); -- signal TRIG1_in : std_logic_vector(7 downto 0);
signal TRIG2_in : std_logic_vector(7 downto 0); -- signal TRIG2_in : std_logic_vector(7 downto 0);
signal TRIG3_in : std_logic_vector(7 downto 0); -- signal TRIG3_in : std_logic_vector(7 downto 0);
signal TRIG4_in : std_logic_vector(7 downto 0); -- signal TRIG4_in : std_logic_vector(7 downto 0);
signal TRIG5_in : std_logic_vector(7 downto 0); -- signal TRIG5_in : std_logic_vector(7 downto 0);
-- signal TRIG6_in : std_logic_vector(7 downto 0); -- signal TRIG6_in : std_logic_vector(7 downto 0);
-- signal TRIG7_in : std_logic_vector(7 downto 0); -- signal TRIG7_in : std_logic_vector(7 downto 0);
-- signal TRIG8_in : std_logic_vector(7 downto 0); -- signal TRIG8_in : std_logic_vector(7 downto 0);
...@@ -497,22 +496,22 @@ begin ...@@ -497,22 +496,22 @@ begin
port map ( port map (
CONTROL => CONTROL, CONTROL => CONTROL,
CLK => clk_20_i, CLK => clk_20_i,
TRIG0 => TRIG0_in, TRIG0 => TRIG0_in);
TRIG1 => TRIG1_in,
TRIG2 => TRIG2_in,
TRIG3 => TRIG3_in,
TRIG4 => TRIG4_in,
TRIG5 => TRIG5_in);
chipscope_icon_1 : chipscope_icon chipscope_icon_1 : chipscope_icon
port map ( CONTROL0 => CONTROL); port map ( CONTROL0 => CONTROL);
TRIG0_in(7 downto 0) <= std_logic_vector(temp_rise_c_sh(3)(7 downto 0));
TRIG1_in(7 downto 0) <= std_logic_vector(temp_rise_c_sh(3)(15 downto 8)); TRIG0_in(0) <= pulse_outp_err_sh_p(5);
TRIG2_in(7 downto 0) <= std_logic_vector(temp_rise_c_sh(3)(23 downto 16)); TRIG0_in(1) <= burst_outp_err_sh_p(5);
TRIG3_in(7 downto 0) <= std_logic_vector(temp_rise_c_sh(3)(31 downto 24));
TRIG4_in(7 downto 0) <= std_logic_vector(temp_rise_c_sh(3)(39 downto 32)); TRIG0_in(2) <= trig_pgen(5);
TRIG5_in(5 downto 0) <= pulse_outp_err_lg_p; TRIG0_in(3) <= pulse_outp_sh(5);
TRIG0_in(4) <= pulse_outp_err_lg_p(5);
TRIG0_in(5) <= burst_outp_err_lg_p(5);
TRIG0_in(6) <= pulse_outp_lg(5);
TRIG0_in(7) <= ch_ttl_pcr_ld(5);
--============================================================================ --============================================================================
...@@ -669,6 +668,10 @@ gen_pulse_chan_logic : for i in 0 to g_nr_chans-1 generate ...@@ -669,6 +668,10 @@ gen_pulse_chan_logic : for i in 0 to g_nr_chans-1 generate
trig_chan(i) <= trig_a(i) when (gf_en_n_i = '1') else trig_chan(i) <= trig_a(i) when (gf_en_n_i = '1') else
trig_degl(i); trig_degl(i);
-- The trigger to the pulse generator is either manual OR from the channel input
trig_pgen(i) <= trig_chan(i) or trig_man(i);
-- Now, sync this channel trigger signal before passing it to the counters -- Now, sync this channel trigger signal before passing it to the counters
-- --
-- The pulse counter is triggered only by a pulse that actually makes it -- The pulse counter is triggered only by a pulse that actually makes it
...@@ -682,17 +685,11 @@ gen_pulse_chan_logic : for i in 0 to g_nr_chans-1 generate ...@@ -682,17 +685,11 @@ gen_pulse_chan_logic : for i in 0 to g_nr_chans-1 generate
( (
clk_i => clk_20_i, clk_i => clk_20_i,
rst_n_i => rst_20_n, rst_n_i => rst_20_n,
data_i => trig_chan(i), data_i => trig_pgen(i),
ppulse_o => trig_chan_redge_p(i) ppulse_o => trig_chan_redge_p(i),
npulse_o => trig_chan_fedge_p(i)
); );
-- AND the ttl line with the de-glitched pulse in order to determine
-- source of pulse. If ANDed signal is 1 then TTL source.
trig_chan_ttl_redge_p(i) <= trig_chan_redge_p(i) and line_front_i (i);
-- AND the blo line with the de-glitched pulse in order to determine
-- source of pulse. If ANDed signal is 1 then BLO source.
trig_chan_blo_redge_p(i) <= trig_chan_redge_p(i) and line_rear_i (i);
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
gen_pulse_cnt : if (g_with_pulse_cnt = true) generate gen_pulse_cnt : if (g_with_pulse_cnt = true) generate
...@@ -757,8 +754,6 @@ end generate gen_pulse_cnt_unused_chans; ...@@ -757,8 +754,6 @@ end generate gen_pulse_cnt_unused_chans;
end generate gen_pulse_cnt; end generate gen_pulse_cnt;
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- The trigger to the pulse generator is either manual OR from the channel input
trig_pgen(i) <= trig_chan(i) or trig_man(i);
------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------
-- Instantiate pulse generator + burst controller block for the channel for LONG pulse operation -- Instantiate pulse generator + burst controller block for the channel for LONG pulse operation
...@@ -772,7 +767,7 @@ end generate gen_pulse_cnt; ...@@ -772,7 +767,7 @@ end generate gen_pulse_cnt;
( (
g_with_fixed_pwidth => g_pgen_fixed_width, g_with_fixed_pwidth => g_pgen_fixed_width,
g_pwidth => g_pgen_pwidth_lg, g_pwidth => g_pgen_pwidth_lg,
g_duty_cycle_div => g_pgen_duty_cycle_div_cont g_pperiod => g_pgen_pperiod_cont
) )
port map port map
( (
...@@ -784,6 +779,8 @@ end generate gen_pulse_cnt; ...@@ -784,6 +779,8 @@ end generate gen_pulse_cnt;
en_i => '1', en_i => '1',
trig_a_i => trig_pgen(i), trig_a_i => trig_pgen(i),
trig_r_edge_p_i => trig_chan_redge_p(i),
trig_f_edge_p_i => trig_chan_fedge_p(i),
pulse_err_p_o => pulse_outp_err_cont (i), pulse_err_p_o => pulse_outp_err_cont (i),
...@@ -801,7 +798,7 @@ end generate gen_pulse_cnt; ...@@ -801,7 +798,7 @@ end generate gen_pulse_cnt;
( (
g_with_fixed_pwidth => g_pgen_fixed_width, g_with_fixed_pwidth => g_pgen_fixed_width,
g_pwidth => g_pgen_pwidth_lg, g_pwidth => g_pgen_pwidth_lg,
g_duty_cycle_div => g_pgen_duty_cycle_div_lg g_pperiod => g_pgen_pperiod_lg
) )
port map port map
( (
...@@ -813,6 +810,8 @@ end generate gen_pulse_cnt; ...@@ -813,6 +810,8 @@ end generate gen_pulse_cnt;
en_i => '1', en_i => '1',
trig_a_i => trig_pgen(i), trig_a_i => trig_pgen(i),
trig_r_edge_p_i => trig_chan_redge_p(i),
trig_f_edge_p_i => trig_chan_fedge_p(i),
pulse_err_p_o => pulse_outp_err_lg_p (i), pulse_err_p_o => pulse_outp_err_lg_p (i),
...@@ -855,7 +854,7 @@ end generate gen_pulse_cnt; ...@@ -855,7 +854,7 @@ end generate gen_pulse_cnt;
( (
g_with_fixed_pwidth => g_pgen_fixed_width, g_with_fixed_pwidth => g_pgen_fixed_width,
g_pwidth => g_pgen_pwidth_sh, g_pwidth => g_pgen_pwidth_sh,
g_duty_cycle_div => g_pgen_duty_cycle_div_sh g_pperiod => g_pgen_pperiod_sh
) )
port map port map
( (
...@@ -867,6 +866,8 @@ end generate gen_pulse_cnt; ...@@ -867,6 +866,8 @@ end generate gen_pulse_cnt;
en_i => '1', en_i => '1',
trig_a_i => trig_pgen(i), trig_a_i => trig_pgen(i),
trig_r_edge_p_i => trig_chan_redge_p(i),
trig_f_edge_p_i => trig_chan_fedge_p(i),
pulse_err_p_o => pulse_outp_err_sh_p (i), pulse_err_p_o => pulse_outp_err_sh_p (i),
......
top/conv_common_gw_pkg.vhd
View file @ 011fbe69
...@@ -85,11 +85,11 @@ package conv_common_gw_pkg is ...@@ -85,11 +85,11 @@ package conv_common_gw_pkg is
-- Pulse width at pulse generator output (valid with fixed output pulse width) -- Pulse width at pulse generator output (valid with fixed output pulse width)
g_pgen_pwidth_lg : natural range 2 to 40 := 24; --**DB: was 20 to 40 g_pgen_pwidth_lg : natural range 2 to 40 := 24; --**DB: was 20 to 40
g_pgen_pwidth_sh : natural range 2 to 40 := 5; g_pgen_pwidth_sh : natural range 2 to 40 := 5;
-- Duty cycle divider ratio for pulse generator
-- output pulse will be limited to 1/g_pgen_duty_cycle_div -- output pulse will be limited to pulse period
g_pgen_duty_cycle_div_cont : natural range 2 to 200 := 200; --For continuous mode operation max freq 4.12kHz g_pgen_pperiod_cont : natural range 2 to 5000 := 4800; --For continuous mode operation max freq 4.12kHz
g_pgen_duty_cycle_div_lg : natural range 6 to 300 := 16; --for LONG pulses changes maximum g_pgen_pperiod_lg : natural range 6 to 300 := 191; --for LONG pulses changes maximum
g_pgen_duty_cycle_div_sh : natural range 2 to 300 := 2; --for SHORT pulses changes maximum g_pgen_pperiod_sh : natural range 2 to 300 := 9; --for SHORT pulses changes maximum
-- Pulse generator glitch filter length in number of clk_20_i cycles -- Pulse generator glitch filter length in number of clk_20_i cycles
g_pgen_gf_len : integer := 4; g_pgen_gf_len : integer := 4;
...@@ -282,8 +282,8 @@ package conv_common_gw_pkg is ...@@ -282,8 +282,8 @@ package conv_common_gw_pkg is
-- Maximum allowable pulse width (20 MHz clock): 2 us -- Maximum allowable pulse width (20 MHz clock): 2 us
g_pwidth : natural range 2 to 40 := 24; --DB was 20 to 40 g_pwidth : natural range 2 to 40 := 24; --DB was 20 to 40
-- Duty cycle divider: D = 1/g_duty_cycle_div -- Pulse period in unit of clock cycles
g_duty_cycle_div : natural := 5 g_pperiod : natural := 5
); );
port port
( (
...@@ -302,7 +302,10 @@ package conv_common_gw_pkg is ...@@ -302,7 +302,10 @@ package conv_common_gw_pkg is
-- Trigger input, has to be '1' to assure pulse output with delay no greater -- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays. -- than internal gate delays.
trig_a_i : in std_logic; trig_a_i : in std_logic;
trig_r_edge_p_i : in std_logic; --synced 1 cycle-long r edge output
trig_f_edge_p_i : in std_logic; --synced 1 cycle-long f edge output
-- Pulse error output, pulses high for one clock cycle when a pulse arrives -- Pulse error output, pulses high for one clock cycle when a pulse arrives
-- within a pulse period -- within a pulse period
pulse_err_p_o : out std_logic; pulse_err_p_o : out std_logic;
...@@ -714,12 +717,7 @@ end component wf_decr_counter; ...@@ -714,12 +717,7 @@ end component wf_decr_counter;
port ( port (
CONTROL: inout std_logic_vector(35 downto 0); CONTROL: inout std_logic_vector(35 downto 0);
CLK: in std_logic; CLK: in std_logic;
TRIG0: in std_logic_vector(7 downto 0); TRIG0: in std_logic_vector(7 downto 0));
TRIG1: in std_logic_vector(7 downto 0);
TRIG2: in std_logic_vector(7 downto 0);
TRIG3: in std_logic_vector(7 downto 0);
TRIG4: in std_logic_vector(7 downto 0);
TRIG5: in std_logic_vector(7 downto 0));
END component chipscope_ila; END component chipscope_ila;
......
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