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conv-common-gw
Commit 011fbe69 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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Major changes: conv_pulse_gen.vhd has been almost completely rewritten. Also top… 

Major changes: conv_pulse_gen.vhd has been almost completely rewritten. Also top file now uses pulse periods instead of duty cycles, this is to be able to cope with none round duty cycles
parent 4b29f817
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modules/conv_dyn_burst_ctrl.vhd
View file @ 011fbe69
......@@ -193,9 +193,10 @@ entity conv_dyn_burst_ctrl is
-- i.e. temp_rise >= g_max_temp.
------------------------------------------------------------------------
when PULSE_REJECT =>
if (pulse_f_edge_p_i = '1' and temp_rise <= g_max_temp) OR
temp_rise = 0 then
if pulse_f_edge_p_i = '1' and temp_rise <= g_max_temp then
nxt_state <= PULSE_REPEAT;
elsif temp_rise = 0 then
nxt_state <= IDLE;
else
nxt_state <= PULSE_REJECT;
end if;
......
modules/conv_pulse_gen.vhd
View file @ 011fbe69
......@@ -3,7 +3,7 @@
-- Pulse generator with trigger
--==============================================================================
--
-- author:
--
-- date of creation: 2013-03-01
--
......@@ -11,8 +11,9 @@
--
-- description:
-- This module generates a constant-width pulse. The width is set using the
-- g_pwidth generic, given in number of clk_i cycles. With a clk_i period of
-- 50 ns, the output pulse width is by default 50*24=1.2 us.
-- g_pwidth generic, given in number of clk_i cycles. The module in principle
-- should generate either 250ns pulses or 1.2us. With a clk_i period of
-- 50 ns, the output pulse width is by default 5 or 24clock cycles long respectively.
--
-- The module is designed to work with an external glitch filter. Enabling
-- this glitch filter will result in jitter on the leading edge of the
......@@ -24,7 +25,9 @@
-- g_pwidth. At the end of the pulse, a rejection phase is implemented in order
-- to avoid too many pulses arriving on the input. This is to safeguard the
-- blocking output stage of the CONV-TTL-BLO boards. The isolation phase limits
-- the input pulse to 1/500 duty cycle.
-- the input pulse to 1/2 cycles for 250 ns pulses and 1/8 for 1.2 us pulses.
-- The burst cntrol module placed immediately after this module, will integrate
-- pulse repetition frequency over time according to a pre-defined "thermal" model.
--
-- dependencies:
-- none
......@@ -44,14 +47,7 @@
--==============================================================================
-- last changes:
-- 01-03-2013 Theodor Stana File created.
-- 02-08-2013 Theodor Stana Implemented rejection phase.
-- 17-02-2014 Theodor Stana Moved the glitch filter to outside the
-- module.
-- 04-03-2014 Theodor Stana Added first pulse inhibit on glitch-filtered
-- side.
-- 24-07-2014 Theodor Stana Added g_with_fixed_pwidth generic and
-- subsequent logic.
-- 19-12-2016 Denia Bouhired Small modification to FSM to allow for very short 250ns pulses.
-- 02-03-2017 Denia Bouhired Almost total re-write of the code to make for a more general FSM
--==============================================================================
-- TODO: -
......@@ -66,47 +62,51 @@ entity conv_pulse_gen is
generic
(
-- This generic enables elaboration of the fixed pulse width logic
g_with_fixed_pwidth : boolean;
g_with_fixed_pwidth : boolean;
-- Pulse width, in number of clk_i cycles
-- Default pulse width (20 MHz clock): 1.2 us
-- Minimum allowable pulse width (20 MHz clock): 1 us
-- Minimum allowable pulse width (20 MHz clock): 100 ns
-- Maximum allowable pulse width (20 MHz clock): 2 us
g_pwidth : natural range 2 to 40 := 24;
g_pwidth : natural range 2 to 40 := 24;
-- Duty cycle divider: D = 1/g_duty_cycle_div
g_duty_cycle_div : natural := 5
-- Pulse period in unit of clock cycles
g_pperiod : natural := 9
);
port
(
-- Clock and active-low reset inputs
clk_i : in std_logic;
rst_n_i : in std_logic;
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Glitch filter enable input
-- '1' - Glitch filter disabled (glitch-sensitive, no output jitter)
-- '0' - Glitch filter enabled (glitch-insensitive, with output jitter)
gf_en_n_i : in std_logic;
gf_en_n_i : in std_logic;
-- Enable input, pulse generation is enabled when '1'
en_i : in std_logic;
en_i : in std_logic;
-- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays.
trig_a_i : in std_logic;
trig_a_i : in std_logic;
-- Rising and falling edges of the input trigger. Externally synchronised to the clock
trig_r_edge_p_i : in std_logic; --synced 1 cycle-long r edge output
trig_f_edge_p_i : in std_logic; --synced 1 cycle-long f edge output
-- Pulse error output, pulses high for one clock cycle when a pulse arrives
-- within a pulse period
pulse_err_p_o : out std_logic;
pulse_err_p_o : out std_logic;
-- Pulse output, active-high
-- latency:
-- glitch filter disabled: none
-- glitch filter enabled: glitch filter length + 5 clk_i cycles
pulse_o : out std_logic;
pulse_r_edge_p_o : out std_logic; --synced 1 cycle-long r edge output
pulse_f_edge_p_o : out std_logic
pulse_o : out std_logic;
-- Rising and falling edges of the output pulse, synchronised to the clock
pulse_r_edge_p_o : out std_logic; --synced 1 cycle-long r edge output
pulse_f_edge_p_o : out std_logic
);
end entity conv_pulse_gen;
......@@ -115,39 +115,35 @@ architecture behav of conv_pulse_gen is
--============================================================================
-- Type declarations
--============================================================================
--============================================================================
type t_state is (
IDLE, -- idle state, wait for pulse
GEN_GF_OFF, -- pulse generation, glitch filter off
REJ_GF_OFF, -- pulse rejection, glitch filter off
GEN_GF_ON, -- pulse generation, glitch filter on
REJ_GF_ON -- pulse rejection, glitch filter on
PRE_IDLE, -- idle state, wait for pulse
GEN_PULSE_OUTPUT, -- pulse generation
REJ_PULSE_INPUT -- pulse rejection
);
--============================================================================
-- Constant declarations
--============================================================================
-- Max value of pulse counter for pulse width and pulse rejection width.
-- glitch filter OFF:
-- generate:
-- * g_pwidth-1: counter starts from 0
-- * g_pwidth-4: three-cycle delay through synchronizer
-- * g_pwidth-5: reset signal applied in REJ_GF_OFF state
-- reject:
-- * g_duty_cycle_div*g_pwidth: D duty cycle
-- * g_duty_cycle_div*g_pwidth-5: 5-cycle delay added from the generate phase
-- glitch filter ON:
-- generate:
-- * g_pwidth-1: counter starts from 0
-- reject:
-- * g_duty_cycle_div*g_pwidth: D duty cycle
-- * g_duty_cycle_div*g_pwidth-2: need one cycle less to allow for true 1/D
-- duty cycle,
-- since the FSM needs to go through IDLE to accept a pulse
constant c_max_gen_gf_off : natural := g_pwidth-5;
constant c_max_rej_gf_off : natural := g_duty_cycle_div*g_pwidth - 6;
constant c_max_gen_gf_on : natural := g_pwidth-1;
constant c_max_rej_gf_on : natural := g_duty_cycle_div*g_pwidth - 2;
-- Max value of pulse counter for pulse width and pulse rejection width.
-- Generate time:
-- * Maximum pulse width = g_pwidth
-- * Count starts from 0 c_max_gen = pwidth - 1
-- * Allow three cycle for synchrnised rising edge pwidth-4
--
constant c_max_gen : natural := g_pwidth-1;
-- Rejection time:
-- * Maximum pulse period = g_pperiod*g_pwidth
-- * Allow one cycle to change state from REJ_PULSE_INPUT to PRE_IDLE
constant c_max_rej : natural := g_pperiod-1;
-- Rising edges result from leading edge of trigger going through a 3 stage synchrnoiser.
-- An extra 1 clock cycle delay is needed before state can be changed.
constant c_r_edge_sync_delay : natural := 4;
--============================================================================
-- Function and procedure declarations
......@@ -165,29 +161,23 @@ architecture behav of conv_pulse_gen is
--============================================================================
-- Signal declarations
--============================================================================
-- Trigger signals
signal pulse_gf_off_d0 : std_logic;
signal pulse_gf_off_d1 : std_logic;
signal pulse_gf_off_d2 : std_logic;
signal gen_edge_gf_off_n : std_logic;
signal trig_gf_on : std_logic;
signal trig_gf_on_d0 : std_logic;
signal trig_gf_on_r_edge_p : std_logic;
signal trig_gf_on_f_edge_p : std_logic;
-- Reset signal combining reset and en signals
signal gen_edge_n : std_logic;
-- Pulse output signals
signal pulse_gf_on : std_logic;
signal pulse_gf_off : std_logic;
signal pulse_gf_off_rst : std_logic;
signal pulse_gf_off_r_edge_p : std_logic;
signal pulse_gf_off_f_edge_p : std_logic;
signal pulse_out_rst_n : std_logic; -- From FSM
signal pulse_gf_on : std_logic; -- Generated from synchronous input
signal pulse_gf_off : std_logic; -- Generated from asynchronous input
signal pulse_out : std_logic; -- Selects between pulse_gf_on and pulse_gf_off
-- Pulse length counter
signal pulse_cnt : unsigned(f_log2_size(g_duty_cycle_div*g_pwidth)-1 downto 0);
signal pulse_cnt_reset : std_logic; -- From FSM
signal pulse_cnt_clr : std_logic; -- From FSM
signal pulse_cnt : unsigned(f_log2_size(g_pperiod)-1 downto 0);
-- FSM signal
-- FSM states
signal state : t_state;
signal nxt_state : t_state;
--==============================================================================
-- architecture begin
......@@ -200,98 +190,90 @@ gen_without_fixed_pwidth : if (g_with_fixed_pwidth = false) generate
end generate gen_without_fixed_pwidth;
gen_with_fixed_pwidth : if (g_with_fixed_pwidth = true) generate
--============================================================================
-- ============================================================================
-- Output logic
--============================================================================
pulse_o <= pulse_gf_off when (gf_en_n_i = '1') else
pulse_gf_on;
-- ============================================================================
-- pulse_out <= pulse_gf_off when (gf_en_n_i = '1') else
-- pulse_gf_on;
pulse_o <= pulse_out;
-- Synchronise output to get correct rising edges and falling edges output pulses
gen_edge_n <= rst_n_i and en_i;
cmp_sync_ffs : gc_sync_ffs
port map
(
clk_i => clk_i,
rst_n_i => gen_edge_n,
data_i => pulse_out,
ppulse_o => pulse_r_edge_p_o,
npulse_o => pulse_f_edge_p_o
);
--============================================================================
-- Pulse generation logic
--============================================================================
-- Generate the pulse on rising edge of trig_a_i
p_pulse_gf_off: process(pulse_gf_off_rst, trig_a_i)
p_pulse_gf_off : process(pulse_out_rst_n, trig_a_i, en_i, gf_en_n_i)
begin
if (pulse_gf_off_rst = '1') then
pulse_gf_off <= '0';
if pulse_out_rst_n = '0' then
pulse_out <= '0';
elsif rising_edge(trig_a_i) then
if (en_i = '1') and (gf_en_n_i = '1') then
pulse_gf_off <= '1';
if (en_i = '1') then --and (gf_en_n_i = '1') then
pulse_out <= '1';
end if;
end if;
end process p_pulse_gf_off;
--pulse_gf_on <= '0' when pulse_out_rst_n = '0' else trig_a_i and not gf_en_n_i;
-- and synchronize the trigger in clk_i domain
-- p_sync_pulse_gf_off: process (clk_i) is
-- begin
-- if rising_edge(clk_i) then
-- if (rst_n_i = '0') then
-- pulse_gf_off_d0 <= '0';
-- pulse_gf_off_d1 <= '0';
-- pulse_gf_off_d2 <= '0';
-- pulse_gf_off_r_edge_p <= '0';
-- elsif (en_i = '1') and (gf_en_n_i = '1') then
-- pulse_gf_off_d0 <= pulse_gf_off;
-- pulse_gf_off_d1 <= pulse_gf_off_d0;
-- pulse_gf_off_d2 <= pulse_gf_off_d1;
-- pulse_gf_off_r_edge_p <= pulse_gf_off_d1 and (not pulse_gf_off_d2);
-- end if;
-- end if;
-- end process p_sync_pulse_gf_off;
gen_edge_gf_off_n <= rst_n_i or en_i or gf_en_n_i;
-- and synchronize the trigger in clk_i domain using sync_ffs general core
cmp_gc_sync_ffs : gc_sync_ffs
generic map
(
g_sync_edge => "positive"
)
port map(
clk_i => clk_i, -- clock from the destination clock domain
rst_n_i => gen_edge_gf_off_n, -- reset is acomibnation of rst_n_i,
-- en_i and gf_en_n_i
data_i => pulse_gf_off, -- async input
npulse_o => pulse_gf_off_f_edge_p,-- negative edge detect output
ppulse_o => pulse_gf_off_r_edge_p-- positive edge detect output
);
-- Trigger signal with glitch filter ON is input signal
trig_gf_on <= '0' when rst_n_i = '0' else trig_a_i ;
-- Rising edge detector for the trigger signal when glitch filter is ON
p_trig_gf_on : process (clk_i) is
--============================================================================
-- Pulse width adjustment logic
--============================================================================
p_count_cycles: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
trig_gf_on_d0 <= '0';
trig_gf_on_r_edge_p <= '0';
if rst_n_i = '0' or pulse_cnt_reset = '1' then
pulse_cnt <= to_unsigned(c_r_edge_sync_delay, f_log2_size(g_pperiod));
elsif pulse_cnt_clr = '1' then
pulse_cnt <= (others => '0');
else
trig_gf_on_d0 <= trig_gf_on;
trig_gf_on_r_edge_p <= trig_gf_on and (not trig_gf_on_d0);
trig_gf_on_f_edge_p <= (not trig_gf_on) and trig_gf_on_d0;
end if;
pulse_cnt <= pulse_cnt+1;
end if;
end if;
end process p_trig_gf_on;
end process p_count_cycles;
pulse_r_edge_p_o <= pulse_gf_off_r_edge_p when gf_en_n_i = '1' else trig_gf_on_r_edge_p;
pulse_f_edge_p_o <= pulse_gf_off_f_edge_p when gf_en_n_i = '1' else trig_gf_on_f_edge_p;
--============================================================================
-- Pulse width adjustment logic
--============================================================================
-- Generate the FSM logic
p_pulse_width: process(clk_i)
-----------------------------------------------------------------------------
-- Finite State Machine FSM
-----------------------------------------------------------------------------
-- Process to trigger state transitions
----------------------------------------
p_fsm_transitions: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
state <= IDLE;
pulse_gf_off_rst <= '1';
pulse_gf_on <= '0';
pulse_cnt <= (others => '0');
pulse_err_p_o <= '0';
--first_p <= '1';
if rst_n_i = '0' then
state <= IDLE;
elsif (en_i = '1') then
-- State machine logic
state <= nxt_state;
end if;
end if;
end process;
-- ======================================================================================
-- Generate the FSM logic
p_fsm_states : process(state, trig_r_edge_p_i, pulse_cnt)
begin
case state is
---------------------------------------------------------------------
-- IDLE
......@@ -300,118 +282,123 @@ pulse_f_edge_p_o <= pulse_gf_off_f_edge_p when gf_en_n_i = '1' else trig_gf_on_f
-- appropriate input arrives
---------------------------------------------------------------------
when IDLE =>
pulse_cnt <= (others => '0');
pulse_gf_off_rst <= '0';
pulse_err_p_o <= '0';
if (gf_en_n_i = '1') then
if (pulse_gf_off_r_edge_p = '1') then
state <= GEN_GF_OFF;
end if;
if trig_r_edge_p_i = '1' then
nxt_state <= GEN_PULSE_OUTPUT;
else
if (trig_gf_on_r_edge_p = '1') then
state <= GEN_GF_ON;
end if;
end if;
-- Pulse error assignment
-- This has been added for special cases whre rising edge occurs
-- on state transition
if (trig_gf_on_f_edge_p = '1' ) then
pulse_err_p_o <= '1';
nxt_state <= IDLE;
end if;
when PRE_IDLE =>
if pulse_cnt >= c_r_edge_sync_delay-1 then
if trig_r_edge_p_i = '1' then
nxt_state <= GEN_PULSE_OUTPUT;
else
nxt_state <= IDLE;
end if;
else
nxt_state <= PRE_IDLE;
end if;
---------------------------------------------------------------------
-- GEN_GF_OFF
-- GEN_PULSE_OUTPUT
--------------------------c-------------------------------------------
-- Extend the generated pulse to the required pulse width.
---------------------------------------------------------------------
when GEN_GF_OFF =>
-- Pulse logic and state change
pulse_cnt <= pulse_cnt + 1;
if pulse_cnt = c_max_gen_gf_off then
state <= REJ_GF_OFF;
end if;
if c_max_gen_gf_off = 0 then
state <= REJ_GF_OFF;
pulse_gf_off_rst <= '1';
end if;
-- Pulse error assignment
pulse_err_p_o <= '0';
if (trig_gf_on_r_edge_p = '1') then
pulse_err_p_o <= '1';
when GEN_PULSE_OUTPUT =>
if pulse_cnt = c_max_gen then
nxt_state <= REJ_PULSE_INPUT;
else
nxt_state <= GEN_PULSE_OUTPUT;
end if;
---------------------------------------------------------------------
-- REJ_GF_OFF
-- REJ_PULSE_INPUT
---------------------------------------------------------------------
-- Cut and reject input pulses, to safeguard the output transformers.
---------------------------------------------------------------------
when REJ_GF_OFF =>
-- Pulse logic and state change
pulse_cnt <= pulse_cnt + 1;
if pulse_cnt = c_max_rej_gf_off then
state <= IDLE;
pulse_gf_off_rst <= '0';
else
pulse_gf_off_rst <= '1';
end if;
-- Pulse error assignment
pulse_err_p_o <= '0';
if (trig_gf_on_r_edge_p = '1') then
pulse_err_p_o <= '1';
end if;
---------------------------------------------------------------------
-- GEN_GF_ON
---------------------------------------------------------------------
-- Start generating the output pulse with the required width.
---------------------------------------------------------------------
when GEN_GF_ON =>
-- Pulse logic and state change
pulse_cnt <= pulse_cnt + 1;
pulse_gf_on <= '1';
if (pulse_cnt = c_max_gen_gf_on) then
state <= REJ_GF_ON;
when REJ_PULSE_INPUT =>
if pulse_cnt = c_max_rej then
nxt_state <= PRE_IDLE;
else
nxt_state <= REJ_PULSE_INPUT;
end if;
-- Pulse error assignment
pulse_err_p_o <= '0';
if (trig_gf_on_r_edge_p = '1') then
pulse_err_p_o <= '1';
end if;
when others =>
nxt_state <= IDLE;
end case;
end process p_fsm_states;
-- Generate the FSM logic
p_fsm_outputs : process(state, trig_r_edge_p_i, pulse_cnt)
begin
case state is
---------------------------------------------------------------------
-- REJ_GF_ON
-- IDLE
---------------------------------------------------------------------
-- Stop generating the output pulse and reject incoming pulses.
-- Clear all values and go to pulse generation state when the
-- appropriate input arrives
---------------------------------------------------------------------
when REJ_GF_ON =>
-- Pulse logic and state change
pulse_gf_on <= '0';
pulse_cnt <= pulse_cnt + 1;
if (pulse_cnt = c_max_rej_gf_on) then
state <= IDLE;
when IDLE =>
pulse_out_rst_n <= rst_n_i;
pulse_err_p_o <= '0';
pulse_cnt_reset <= '1';
pulse_cnt_clr <= '0';
when PRE_IDLE =>
pulse_out_rst_n <= rst_n_i;
if pulse_cnt < c_r_edge_sync_delay-1 then
pulse_err_p_o <= trig_r_edge_p_i;
else
pulse_err_p_o <= '0';
end if;
pulse_cnt_reset <= '0';
pulse_cnt_clr <= '0';
---------------------------------------------------------------------
-- GEN_PULSE_OUTPUT
--------------------------c-------------------------------------------
-- Extend the generated pulse to the required pulse width.
---------------------------------------------------------------------
when GEN_PULSE_OUTPUT =>
pulse_out_rst_n <= rst_n_i;
pulse_err_p_o <= trig_r_edge_p_i;
pulse_cnt_reset <= '0';
pulse_cnt_clr <= '0';
-- Pulse error assignment
pulse_err_p_o <= '0';
if (trig_gf_on_r_edge_p = '1') then
pulse_err_p_o <= '1';
---------------------------------------------------------------------
-- REJ_PULSE_INPUT
---------------------------------------------------------------------
-- Cut and reject input pulses, to safeguard the output transformers.
---------------------------------------------------------------------
when REJ_PULSE_INPUT =>
pulse_err_p_o <= trig_r_edge_p_i;
pulse_out_rst_n <= '0';
pulse_cnt_reset <= '0';
if pulse_cnt = c_max_rej then
pulse_cnt_clr <= '1';
else
pulse_cnt_clr <= '0';
end if;
when others =>
state <= IDLE;
pulse_out_rst_n <= '0';
pulse_err_p_o <= '0';
pulse_cnt_reset <= '1';
end case;
end if;
end if;
end process p_pulse_width;
end process p_fsm_outputs;
end generate gen_with_fixed_pwidth;
end architecture behav;
......
top/conv_common_gw.vhd
View file @ 011fbe69
......@@ -73,14 +73,14 @@ entity conv_common_gw is
-- Pulse width at pulse generator output (valid with fixed output pulse width)
g_pgen_pwidth_lg : natural range 2 to 40 := 24;
g_pgen_pwidth_sh : natural range 2 to 40 := 5;
-- Duty cycle divider ratio for pulse generator
-- output pulse will be limited to 1/g_pgen_duty_cycle_div
-- output pulse will be limited to period
--For continuous mode operation max freq 4.16kHz
g_pgen_duty_cycle_div_cont : natural range 2 to 200 := 200;
g_pgen_pperiod_cont : natural range 2 to 5000 := 4800;
--for LONG pulses changes maximum frequency to ~104kHz
g_pgen_duty_cycle_div_lg : natural range 6 to 300 := 8;
g_pgen_pperiod_lg : natural range 6 to 300 := 191;
--for SHORT pulses changes maximum frequency to ~2MHz
g_pgen_duty_cycle_div_sh : natural range 2 to 300 := 2;
g_pgen_pperiod_sh : natural range 2 to 300 := 9;
-- Pulse generator glitch filter length in number of clk_20_i cycles
g_pgen_gf_len : integer := 4;
......@@ -320,8 +320,7 @@ architecture arch of conv_common_gw is
signal trig_degl : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_chan : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_chan_redge_p : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_chan_ttl_redge_p : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_chan_blo_redge_p : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_chan_fedge_p : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_man : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_pgen : std_logic_vector(g_nr_chans-1 downto 0);
signal burst_en_n : std_logic;
......@@ -473,11 +472,11 @@ architecture arch of conv_common_gw is
signal CONTROL : std_logic_vector(35 downto 0);
signal CLK : std_logic;
signal TRIG0_in : std_logic_vector(7 downto 0);
signal TRIG1_in : std_logic_vector(7 downto 0);
signal TRIG2_in : std_logic_vector(7 downto 0);
signal TRIG3_in : std_logic_vector(7 downto 0);
signal TRIG4_in : std_logic_vector(7 downto 0);
signal TRIG5_in : std_logic_vector(7 downto 0);
-- signal TRIG1_in : std_logic_vector(7 downto 0);
-- signal TRIG2_in : std_logic_vector(7 downto 0);
-- signal TRIG3_in : std_logic_vector(7 downto 0);
-- signal TRIG4_in : std_logic_vector(7 downto 0);
-- signal TRIG5_in : std_logic_vector(7 downto 0);
-- signal TRIG6_in : std_logic_vector(7 downto 0);
-- signal TRIG7_in : std_logic_vector(7 downto 0);
-- signal TRIG8_in : std_logic_vector(7 downto 0);
......@@ -497,22 +496,22 @@ begin
port map (
CONTROL => CONTROL,
CLK => clk_20_i,
TRIG0 => TRIG0_in,
TRIG1 => TRIG1_in,
TRIG2 => TRIG2_in,
TRIG3 => TRIG3_in,
TRIG4 => TRIG4_in,
TRIG5 => TRIG5_in);
TRIG0 => TRIG0_in);
chipscope_icon_1 : chipscope_icon
port map ( CONTROL0 => CONTROL);
TRIG0_in(7 downto 0) <= std_logic_vector(temp_rise_c_sh(3)(7 downto 0));
TRIG1_in(7 downto 0) <= std_logic_vector(temp_rise_c_sh(3)(15 downto 8));
TRIG2_in(7 downto 0) <= std_logic_vector(temp_rise_c_sh(3)(23 downto 16));
TRIG3_in(7 downto 0) <= std_logic_vector(temp_rise_c_sh(3)(31 downto 24));
TRIG4_in(7 downto 0) <= std_logic_vector(temp_rise_c_sh(3)(39 downto 32));
TRIG5_in(5 downto 0) <= pulse_outp_err_lg_p;
TRIG0_in(0) <= pulse_outp_err_sh_p(5);
TRIG0_in(1) <= burst_outp_err_sh_p(5);
TRIG0_in(2) <= trig_pgen(5);
TRIG0_in(3) <= pulse_outp_sh(5);
TRIG0_in(4) <= pulse_outp_err_lg_p(5);
TRIG0_in(5) <= burst_outp_err_lg_p(5);
TRIG0_in(6) <= pulse_outp_lg(5);
TRIG0_in(7) <= ch_ttl_pcr_ld(5);
--============================================================================
......@@ -669,6 +668,10 @@ gen_pulse_chan_logic : for i in 0 to g_nr_chans-1 generate
trig_chan(i) <= trig_a(i) when (gf_en_n_i = '1') else
trig_degl(i);
-- The trigger to the pulse generator is either manual OR from the channel input
trig_pgen(i) <= trig_chan(i) or trig_man(i);
-- Now, sync this channel trigger signal before passing it to the counters
--
-- The pulse counter is triggered only by a pulse that actually makes it
......@@ -682,17 +685,11 @@ gen_pulse_chan_logic : for i in 0 to g_nr_chans-1 generate
(
clk_i => clk_20_i,
rst_n_i => rst_20_n,
data_i => trig_chan(i),
ppulse_o => trig_chan_redge_p(i)
data_i => trig_pgen(i),
ppulse_o => trig_chan_redge_p(i),
npulse_o => trig_chan_fedge_p(i)
);
-- AND the ttl line with the de-glitched pulse in order to determine
-- source of pulse. If ANDed signal is 1 then TTL source.
trig_chan_ttl_redge_p(i) <= trig_chan_redge_p(i) and line_front_i (i);
-- AND the blo line with the de-glitched pulse in order to determine
-- source of pulse. If ANDed signal is 1 then BLO source.
trig_chan_blo_redge_p(i) <= trig_chan_redge_p(i) and line_rear_i (i);
--------------------------------------------------------------------------------
gen_pulse_cnt : if (g_with_pulse_cnt = true) generate
......@@ -757,8 +754,6 @@ end generate gen_pulse_cnt_unused_chans;
end generate gen_pulse_cnt;
--------------------------------------------------------------------------------
-- The trigger to the pulse generator is either manual OR from the channel input
trig_pgen(i) <= trig_chan(i) or trig_man(i);
-------------------------------------------------------------------------------------------------
-- Instantiate pulse generator + burst controller block for the channel for LONG pulse operation
......@@ -772,7 +767,7 @@ end generate gen_pulse_cnt;
(
g_with_fixed_pwidth => g_pgen_fixed_width,
g_pwidth => g_pgen_pwidth_lg,
g_duty_cycle_div => g_pgen_duty_cycle_div_cont
g_pperiod => g_pgen_pperiod_cont
)
port map
(
......@@ -784,6 +779,8 @@ end generate gen_pulse_cnt;
en_i => '1',
trig_a_i => trig_pgen(i),
trig_r_edge_p_i => trig_chan_redge_p(i),
trig_f_edge_p_i => trig_chan_fedge_p(i),
pulse_err_p_o => pulse_outp_err_cont (i),
......@@ -801,7 +798,7 @@ end generate gen_pulse_cnt;
(
g_with_fixed_pwidth => g_pgen_fixed_width,
g_pwidth => g_pgen_pwidth_lg,
g_duty_cycle_div => g_pgen_duty_cycle_div_lg
g_pperiod => g_pgen_pperiod_lg
)
port map
(
......@@ -813,6 +810,8 @@ end generate gen_pulse_cnt;
en_i => '1',
trig_a_i => trig_pgen(i),
trig_r_edge_p_i => trig_chan_redge_p(i),
trig_f_edge_p_i => trig_chan_fedge_p(i),
pulse_err_p_o => pulse_outp_err_lg_p (i),
......@@ -855,7 +854,7 @@ end generate gen_pulse_cnt;
(
g_with_fixed_pwidth => g_pgen_fixed_width,
g_pwidth => g_pgen_pwidth_sh,
g_duty_cycle_div => g_pgen_duty_cycle_div_sh
g_pperiod => g_pgen_pperiod_sh
)
port map
(
......@@ -867,6 +866,8 @@ end generate gen_pulse_cnt;
en_i => '1',
trig_a_i => trig_pgen(i),
trig_r_edge_p_i => trig_chan_redge_p(i),
trig_f_edge_p_i => trig_chan_fedge_p(i),
pulse_err_p_o => pulse_outp_err_sh_p (i),
......
top/conv_common_gw_pkg.vhd
View file @ 011fbe69
......@@ -85,11 +85,11 @@ package conv_common_gw_pkg is
-- Pulse width at pulse generator output (valid with fixed output pulse width)
g_pgen_pwidth_lg : natural range 2 to 40 := 24; --**DB: was 20 to 40
g_pgen_pwidth_sh : natural range 2 to 40 := 5;
-- Duty cycle divider ratio for pulse generator
-- output pulse will be limited to 1/g_pgen_duty_cycle_div
g_pgen_duty_cycle_div_cont : natural range 2 to 200 := 200; --For continuous mode operation max freq 4.12kHz
g_pgen_duty_cycle_div_lg : natural range 6 to 300 := 16; --for LONG pulses changes maximum
g_pgen_duty_cycle_div_sh : natural range 2 to 300 := 2; --for SHORT pulses changes maximum
-- output pulse will be limited to pulse period
g_pgen_pperiod_cont : natural range 2 to 5000 := 4800; --For continuous mode operation max freq 4.12kHz
g_pgen_pperiod_lg : natural range 6 to 300 := 191; --for LONG pulses changes maximum
g_pgen_pperiod_sh : natural range 2 to 300 := 9; --for SHORT pulses changes maximum
-- Pulse generator glitch filter length in number of clk_20_i cycles
g_pgen_gf_len : integer := 4;
......@@ -282,8 +282,8 @@ package conv_common_gw_pkg is
-- Maximum allowable pulse width (20 MHz clock): 2 us
g_pwidth : natural range 2 to 40 := 24; --DB was 20 to 40
-- Duty cycle divider: D = 1/g_duty_cycle_div
g_duty_cycle_div : natural := 5
-- Pulse period in unit of clock cycles
g_pperiod : natural := 5
);
port
(
......@@ -302,7 +302,10 @@ package conv_common_gw_pkg is
-- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays.
trig_a_i : in std_logic;
trig_r_edge_p_i : in std_logic; --synced 1 cycle-long r edge output
trig_f_edge_p_i : in std_logic; --synced 1 cycle-long f edge output
-- Pulse error output, pulses high for one clock cycle when a pulse arrives
-- within a pulse period
pulse_err_p_o : out std_logic;
......@@ -714,12 +717,7 @@ end component wf_decr_counter;
port (
CONTROL: inout std_logic_vector(35 downto 0);
CLK: in std_logic;
TRIG0: in std_logic_vector(7 downto 0);
TRIG1: in std_logic_vector(7 downto 0);
TRIG2: in std_logic_vector(7 downto 0);
TRIG3: in std_logic_vector(7 downto 0);
TRIG4: in std_logic_vector(7 downto 0);
TRIG5: in std_logic_vector(7 downto 0));
TRIG0: in std_logic_vector(7 downto 0));
END component chipscope_ila;
......
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