conv_regs

Converter board registers

1. Memory map summary
2. HDL symbol
3. Register description
3.1. BIDR
3.2. SR
3.3. CR
3.4. CH1TTLPCR
3.5. CH2TTLPCR
3.6. CH3TTLPCR
3.7. CH4TTLPCR
3.8. CH5TTLPCR
3.9. CH6TTLPCR
3.10. CH1BLOPCR
3.11. CH2BLOPCR
3.12. CH3BLOPCR
3.13. CH4BLOPCR
3.14. CH5BLOPCR
3.15. CH6BLOPCR
3.16. TVLR
3.17. TVHR
3.18. TBMR
3.19. TBCYR
3.20. TBTLR
3.21. TBTHR
3.22. TBCSR
3.23. CH1LTSCYR
3.24. CH1LTSTLR
3.25. CH1LTSTHR
3.26. CH2LTSCYR
3.27. CH2LTSTLR
3.28. CH2LTSTHR
3.29. CH3LTSCYR
3.30. CH3LTSTLR
3.31. CH3LTSTHR
3.32. CH4LTSCYR
3.33. CH4LTSTLR
3.34. CH4LTSTHR
3.35. CH5LTSCYR
3.36. CH5LTSTLR
3.37. CH5LTSTHR
3.38. CH6LTSCYR
3.39. CH6LTSTLR
3.40. CH6LTSTHR
3.41. LSR
3.42. OSWR
3.43. UIDLR
3.44. UIDHR
3.45. TEMPR

1. Memory map summary

H/W Address	Type	Name	VHDL/Verilog prefix	C prefix
0x0	REG	BIDR	reg_bidr	BIDR
0x1	REG	SR	reg_sr	SR
0x2	REG	CR	reg_cr	CR
0x3	REG	CH1TTLPCR	reg_ch1ttlpcr	CH1TTLPCR
0x4	REG	CH2TTLPCR	reg_ch2ttlpcr	CH2TTLPCR
0x5	REG	CH3TTLPCR	reg_ch3ttlpcr	CH3TTLPCR
0x6	REG	CH4TTLPCR	reg_ch4ttlpcr	CH4TTLPCR
0x7	REG	CH5TTLPCR	reg_ch5ttlpcr	CH5TTLPCR
0x8	REG	CH6TTLPCR	reg_ch6ttlpcr	CH6TTLPCR
0x9	REG	CH1BLOPCR	reg_ch1blopcr	CH1BLOPCR
0xa	REG	CH2BLOPCR	reg_ch2blopcr	CH2BLOPCR
0xb	REG	CH3BLOPCR	reg_ch3blopcr	CH3BLOPCR
0xc	REG	CH4BLOPCR	reg_ch4blopcr	CH4BLOPCR
0xd	REG	CH5BLOPCR	reg_ch5blopcr	CH5BLOPCR
0xe	REG	CH6BLOPCR	reg_ch6blopcr	CH6BLOPCR
0xf	REG	TVLR	reg_tvlr	TVLR
0x10	REG	TVHR	reg_tvhr	TVHR
0x11	REG	TBMR	reg_tbmr	TBMR
0x12	REG	TBCYR	reg_tbcyr	TBCYR
0x13	REG	TBTLR	reg_tbtlr	TBTLR
0x14	REG	TBTHR	reg_tbthr	TBTHR
0x15	REG	TBCSR	reg_tbcsr	TBCSR
0x16	REG	CH1LTSCYR	reg_ch1ltscyr	CH1LTSCYR
0x17	REG	CH1LTSTLR	reg_ch1ltstlr	CH1LTSTLR
0x18	REG	CH1LTSTHR	reg_ch1ltsthr	CH1LTSTHR
0x19	REG	CH2LTSCYR	reg_ch2ltscyr	CH2LTSCYR
0x1a	REG	CH2LTSTLR	reg_ch2ltstlr	CH2LTSTLR
0x1b	REG	CH2LTSTHR	reg_ch2ltsthr	CH2LTSTHR
0x1c	REG	CH3LTSCYR	reg_ch3ltscyr	CH3LTSCYR
0x1d	REG	CH3LTSTLR	reg_ch3ltstlr	CH3LTSTLR
0x1e	REG	CH3LTSTHR	reg_ch3ltsthr	CH3LTSTHR
0x1f	REG	CH4LTSCYR	reg_ch4ltscyr	CH4LTSCYR
0x20	REG	CH4LTSTLR	reg_ch4ltstlr	CH4LTSTLR
0x21	REG	CH4LTSTHR	reg_ch4ltsthr	CH4LTSTHR
0x22	REG	CH5LTSCYR	reg_ch5ltscyr	CH5LTSCYR
0x23	REG	CH5LTSTLR	reg_ch5ltstlr	CH5LTSTLR
0x24	REG	CH5LTSTHR	reg_ch5ltsthr	CH5LTSTHR
0x25	REG	CH6LTSCYR	reg_ch6ltscyr	CH6LTSCYR
0x26	REG	CH6LTSTLR	reg_ch6ltstlr	CH6LTSTLR
0x27	REG	CH6LTSTHR	reg_ch6ltsthr	CH6LTSTHR
0x28	REG	LSR	reg_lsr	LSR
0x29	REG	OSWR	reg_oswr	OSWR
0x2a	REG	UIDLR	reg_uidlr	UIDLR
0x2b	REG	UIDHR	reg_uidhr	UIDHR
0x2c	REG	TEMPR	reg_tempr	TEMPR

2. HDL symbol

→	rst_n_i	BIDR:
→	clk_sys_i	reg_bidr_i[31:0]	⇐
⇒	wb_adr_i[5:0]
⇒	wb_dat_i[31:0]	SR:
⇐	wb_dat_o[31:0]	reg_sr_gwvers_i[7:0]	⇐
→	wb_cyc_i	reg_sr_switches_i[7:0]	⇐
⇒	wb_sel_i[3:0]	reg_sr_rtm_i[5:0]	⇐
→	wb_stb_i	reg_sr_i2c_wdto_o	→
→	wb_we_i	reg_sr_i2c_wdto_i	←
←	wb_ack_o	reg_sr_i2c_wdto_load_o	→
←	wb_stall_o	reg_sr_wrpres_i	←
		reg_sr_i2c_err_o	→
		reg_sr_i2c_err_i	←
		reg_sr_i2c_err_load_o	→
		reg_sr_pmisse_o[5:0]	⇒
		reg_sr_pmisse_i[5:0]	⇐
		reg_sr_pmisse_load_o	→

		CR:
		reg_cr_rst_unlock_o	→
		reg_cr_rst_unlock_i	←
		reg_cr_rst_unlock_load_o	→
		reg_cr_rst_o	→
		reg_cr_rst_i	←
		reg_cr_rst_load_o	→
		reg_cr_mpt_o[7:0]	⇒
		reg_cr_mpt_wr_o	→

		CH1TTLPCR:
		reg_ch1ttlpcr_o[31:0]	⇒
		reg_ch1ttlpcr_i[31:0]	⇐
		reg_ch1ttlpcr_load_o	→

		CH2TTLPCR:
		reg_ch2ttlpcr_o[31:0]	⇒
		reg_ch2ttlpcr_i[31:0]	⇐
		reg_ch2ttlpcr_load_o	→

		CH3TTLPCR:
		reg_ch3ttlpcr_o[31:0]	⇒
		reg_ch3ttlpcr_i[31:0]	⇐
		reg_ch3ttlpcr_load_o	→

		CH4TTLPCR:
		reg_ch4ttlpcr_o[31:0]	⇒
		reg_ch4ttlpcr_i[31:0]	⇐
		reg_ch4ttlpcr_load_o	→

		CH5TTLPCR:
		reg_ch5ttlpcr_o[31:0]	⇒
		reg_ch5ttlpcr_i[31:0]	⇐
		reg_ch5ttlpcr_load_o	→

		CH6TTLPCR:
		reg_ch6ttlpcr_o[31:0]	⇒
		reg_ch6ttlpcr_i[31:0]	⇐
		reg_ch6ttlpcr_load_o	→

		CH1BLOPCR:
		reg_ch1blopcr_o[31:0]	⇒
		reg_ch1blopcr_i[31:0]	⇐
		reg_ch1blopcr_load_o	→

		CH2BLOPCR:
		reg_ch2blopcr_o[31:0]	⇒
		reg_ch2blopcr_i[31:0]	⇐
		reg_ch2blopcr_load_o	→

		CH3BLOPCR:
		reg_ch3blopcr_o[31:0]	⇒
		reg_ch3blopcr_i[31:0]	⇐
		reg_ch3blopcr_load_o	→

		CH4BLOPCR:
		reg_ch4blopcr_o[31:0]	⇒
		reg_ch4blopcr_i[31:0]	⇐
		reg_ch4blopcr_load_o	→

		CH5BLOPCR:
		reg_ch5blopcr_o[31:0]	⇒
		reg_ch5blopcr_i[31:0]	⇐
		reg_ch5blopcr_load_o	→

		CH6BLOPCR:
		reg_ch6blopcr_o[31:0]	⇒
		reg_ch6blopcr_i[31:0]	⇐
		reg_ch6blopcr_load_o	→

		TVLR:
		reg_tvlr_o[31:0]	⇒
		reg_tvlr_i[31:0]	⇐
		reg_tvlr_load_o	→

		TVHR:
		reg_tvhr_o[7:0]	⇒
		reg_tvhr_i[7:0]	⇐
		reg_tvhr_load_o	→

		TBMR:
		reg_tbmr_chan_i[5:0]	⇐
		reg_tbmr_wrtag_i	←

		TBCYR:
		reg_tbcyr_i[27:0]	⇐

		TBTLR:
		reg_tbtlr_i[31:0]	⇐

		TBTHR:
		reg_tbthr_i[7:0]	⇐

		TBCSR:
		reg_tbcsr_usedw_i[6:0]	⇐
		reg_tbcsr_full_i	←
		reg_tbcsr_empty_i	←
		reg_tbcsr_clr_o	→
		reg_tbcsr_clr_i	←
		reg_tbcsr_clr_load_o	→

		CH1LTSCYR:
		reg_ch1ltscyr_i[27:0]	⇐

		CH1LTSTLR:
		reg_ch1ltstlr_i[31:0]	⇐

		CH1LTSTHR:
		reg_ch1ltsthr_tai_i[7:0]	⇐
		reg_ch1ltsthr_wrtag_i	←

		CH2LTSCYR:
		reg_ch2ltscyr_i[27:0]	⇐

		CH2LTSTLR:
		reg_ch2ltstlr_i[31:0]	⇐

		CH2LTSTHR:
		reg_ch2ltsthr_tai_i[7:0]	⇐
		reg_ch2ltsthr_wrtag_i	←

		CH3LTSCYR:
		reg_ch3ltscyr_i[27:0]	⇐

		CH3LTSTLR:
		reg_ch3ltstlr_i[31:0]	⇐

		CH3LTSTHR:
		reg_ch3ltsthr_tai_i[7:0]	⇐
		reg_ch3ltsthr_wrtag_i	←

		CH4LTSCYR:
		reg_ch4ltscyr_i[27:0]	⇐

		CH4LTSTLR:
		reg_ch4ltstlr_i[31:0]	⇐

		CH4LTSTHR:
		reg_ch4ltsthr_tai_i[7:0]	⇐
		reg_ch4ltsthr_wrtag_i	←

		CH5LTSCYR:
		reg_ch5ltscyr_i[27:0]	⇐

		CH5LTSTLR:
		reg_ch5ltstlr_i[31:0]	⇐

		CH5LTSTHR:
		reg_ch5ltsthr_tai_i[7:0]	⇐
		reg_ch5ltsthr_wrtag_i	←

		CH6LTSCYR:
		reg_ch6ltscyr_i[27:0]	⇐

		CH6LTSTLR:
		reg_ch6ltstlr_i[31:0]	⇐

		CH6LTSTHR:
		reg_ch6ltsthr_tai_i[7:0]	⇐
		reg_ch6ltsthr_wrtag_i	←

		LSR:
		reg_lsr_front_i[5:0]	⇐
		reg_lsr_frontinv_i[3:0]	⇐
		reg_lsr_rear_i[5:0]	⇐
		reg_lsr_frontfs_i[5:0]	⇐
		reg_lsr_frontinvfs_i[3:0]	⇐
		reg_lsr_rearfs_i[5:0]	⇐

		OSWR:
		reg_oswr_switches_i[31:0]	⇐

		UIDLR:
		reg_uidlr_i[31:0]	⇐

		UIDHR:
		reg_uidhr_i[31:0]	⇐

		TEMPR:
		reg_tempr_i[15:0]	⇐

3. Register description

3.1. BIDR

HW prefix:	reg_bidr
HW address:	0x0
C prefix:	BIDR
C offset:	0x0

Board ID Register

31	30	29	28	27	26	25	24
BIDR[31:24]

23	22	21	20	19	18	17	16
BIDR[23:16]

15	14	13	12	11	10	9	8
BIDR[15:8]

7	6	5	4	3	2	1	0
BIDR[7:0]

BIDR [read-only]: ID register bits

3.2. SR

HW prefix:	reg_sr
HW address:	0x1
C prefix:	SR
C offset:	0x4

Status Register

31	30	29	28	27	26	25	24
-	PMISSE[5:0]						I2C_ERR

23	22	21	20	19	18	17	16
WRPRES	I2C_WDTO	RTM[5:0]

15	14	13	12	11	10	9	8
SWITCHES[7:0]

7	6	5	4	3	2	1	0
GWVERS[7:0]

GWVERS [read-only]: Gateware version
Leftmost nibble hex value is major release decimal value
Rightmost nibble hex value is minor release decimal value
e.g.
0x11 -- v1.1
0x2e -- v2.14
SWITCHES [read-only]: Status of on-board general-purpose switches
1 -- switch is ON
0 -- switch is OFF
RTM [read-only]: RTM detection lines~\cite{rtm-det}
1 -- line active
0 -- line inactive
I2C_WDTO [read/write]: I2C communication watchdog timeout error
1 -- timeout occured
0 -- no timeout
This bit can be cleared by writing a '1' to it
WRPRES [read-only]: White Rabbit present
1 -- White Rabbit present
0 -- White Rabbit not present
I2C_ERR [read/write]: I2C communication error
1 -- attempted to address non-existing address
0 -- idle
This bit can be cleared by writing a '1' to it
PMISSE [read/write]: Pulse missed error
1 -- pulse arrived during pulse rejection phase
0 -- idle
Bit 0 -- channel 1
Bit 1 -- channel 2
etc.
Each bit can be cleared by writing a '1' to it

3.3. CR

HW prefix:	reg_cr
HW address:	0x2
C prefix:	CR
C offset:	0x8

Control Register

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	MPT[7:6]

7	6	5	4	3	2	1	0
MPT[5:0]						RST	RST_UNLOCK

RST_UNLOCK [read/write]: Reset unlock bit
1 -- Reset bit unlocked
0 -- Reset bit locked
RST [read/write]: Reset bit - active only if RST_UNLOCK is 1
1 -- initiate logic reset
0 -- no reset
MPT [write-only]: Manual Pulse Trigger
Write the following sequence to trigger a pulse:
0xde -- Byte 1 of magic sequence
0xad -- Byte 2 of magic sequence
0xbe -- Byte 3 of magic sequence
0xef -- Byte 4 of magic sequence
Number in range 1..6 -- trigger a pulse

3.4. CH1TTLPCR

HW prefix:	reg_ch1ttlpcr
HW address:	0x3
C prefix:	CH1TTLPCR
C offset:	0xc

Channel 1 Pulse Counter Register for TTL pulses

31	30	29	28	27	26	25	24
CH1TTLPCR[31:24]

23	22	21	20	19	18	17	16
CH1TTLPCR[23:16]

15	14	13	12	11	10	9	8
CH1TTLPCR[15:8]

7	6	5	4	3	2	1	0
CH1TTLPCR[7:0]

CH1TTLPCR [read/write]: TTL pulse counter value

3.5. CH2TTLPCR

HW prefix:	reg_ch2ttlpcr
HW address:	0x4
C prefix:	CH2TTLPCR
C offset:	0x10

Channel 2 Pulse Counter Register for TTL pulses

31	30	29	28	27	26	25	24
CH2TTLPCR[31:24]

23	22	21	20	19	18	17	16
CH2TTLPCR[23:16]

15	14	13	12	11	10	9	8
CH2TTLPCR[15:8]

7	6	5	4	3	2	1	0
CH2TTLPCR[7:0]

CH2TTLPCR [read/write]: TTL pulse counter value

3.6. CH3TTLPCR

HW prefix:	reg_ch3ttlpcr
HW address:	0x5
C prefix:	CH3TTLPCR
C offset:	0x14

Channel 3 Pulse Counter Register for TTL pulses

31	30	29	28	27	26	25	24
CH3TTLPCR[31:24]

23	22	21	20	19	18	17	16
CH3TTLPCR[23:16]

15	14	13	12	11	10	9	8
CH3TTLPCR[15:8]

7	6	5	4	3	2	1	0
CH3TTLPCR[7:0]

CH3TTLPCR [read/write]: TTL pulse counter value

3.7. CH4TTLPCR

HW prefix:	reg_ch4ttlpcr
HW address:	0x6
C prefix:	CH4TTLPCR
C offset:	0x18

Channel 4 Pulse Counter Register for TTL pulses

31	30	29	28	27	26	25	24
CH4TTLPCR[31:24]

23	22	21	20	19	18	17	16
CH4TTLPCR[23:16]

15	14	13	12	11	10	9	8
CH4TTLPCR[15:8]

7	6	5	4	3	2	1	0
CH4TTLPCR[7:0]

CH4TTLPCR [read/write]: TTL pulse counter value

3.8. CH5TTLPCR

HW prefix:	reg_ch5ttlpcr
HW address:	0x7
C prefix:	CH5TTLPCR
C offset:	0x1c

Channel 5 Pulse Counter Register for TTL pulses

31	30	29	28	27	26	25	24
CH5TTLPCR[31:24]

23	22	21	20	19	18	17	16
CH5TTLPCR[23:16]

15	14	13	12	11	10	9	8
CH5TTLPCR[15:8]

7	6	5	4	3	2	1	0
CH5TTLPCR[7:0]

CH5TTLPCR [read/write]: TTL pulse counter value

3.9. CH6TTLPCR

HW prefix:	reg_ch6ttlpcr
HW address:	0x8
C prefix:	CH6TTLPCR
C offset:	0x20

Channel 6 Pulse Counter Register for TTL pulses

31	30	29	28	27	26	25	24
CH6TTLPCR[31:24]

23	22	21	20	19	18	17	16
CH6TTLPCR[23:16]

15	14	13	12	11	10	9	8
CH6TTLPCR[15:8]

7	6	5	4	3	2	1	0
CH6TTLPCR[7:0]

CH6TTLPCR [read/write]: TTL pulse counter value

3.10. CH1BLOPCR

HW prefix:	reg_ch1blopcr
HW address:	0x9
C prefix:	CH1BLOPCR
C offset:	0x24

Channel 1 Pulse Counter Register for BLO pulses

31	30	29	28	27	26	25	24
CH1BLOPCR[31:24]

23	22	21	20	19	18	17	16
CH1BLOPCR[23:16]

15	14	13	12	11	10	9	8
CH1BLOPCR[15:8]

7	6	5	4	3	2	1	0
CH1BLOPCR[7:0]

CH1BLOPCR [read/write]: BLO pulse counter value

3.11. CH2BLOPCR

HW prefix:	reg_ch2blopcr
HW address:	0xa
C prefix:	CH2BLOPCR
C offset:	0x28

Channel 2 Pulse Counter Register for BLO pulses

31	30	29	28	27	26	25	24
CH2BLOPCR[31:24]

23	22	21	20	19	18	17	16
CH2BLOPCR[23:16]

15	14	13	12	11	10	9	8
CH2BLOPCR[15:8]

7	6	5	4	3	2	1	0
CH2BLOPCR[7:0]

CH2BLOPCR [read/write]: BLO pulse counter value

3.12. CH3BLOPCR

HW prefix:	reg_ch3blopcr
HW address:	0xb
C prefix:	CH3BLOPCR
C offset:	0x2c

Channel 3 Pulse Counter Register for BLO pulses

31	30	29	28	27	26	25	24
CH3BLOPCR[31:24]

23	22	21	20	19	18	17	16
CH3BLOPCR[23:16]

15	14	13	12	11	10	9	8
CH3BLOPCR[15:8]

7	6	5	4	3	2	1	0
CH3BLOPCR[7:0]

CH3BLOPCR [read/write]: BLO pulse counter value

3.13. CH4BLOPCR

HW prefix:	reg_ch4blopcr
HW address:	0xc
C prefix:	CH4BLOPCR
C offset:	0x30

Channel 4 Pulse Counter Register for BLO pulses

31	30	29	28	27	26	25	24
CH4BLOPCR[31:24]

23	22	21	20	19	18	17	16
CH4BLOPCR[23:16]

15	14	13	12	11	10	9	8
CH4BLOPCR[15:8]

7	6	5	4	3	2	1	0
CH4BLOPCR[7:0]

CH4BLOPCR [read/write]: BLO pulse counter value

3.14. CH5BLOPCR

HW prefix:	reg_ch5blopcr
HW address:	0xd
C prefix:	CH5BLOPCR
C offset:	0x34

Channel 5 Pulse Counter Register for BLO pulses

31	30	29	28	27	26	25	24
CH5BLOPCR[31:24]

23	22	21	20	19	18	17	16
CH5BLOPCR[23:16]

15	14	13	12	11	10	9	8
CH5BLOPCR[15:8]

7	6	5	4	3	2	1	0
CH5BLOPCR[7:0]

CH5BLOPCR [read/write]: BLO pulse counter value

3.15. CH6BLOPCR

HW prefix:	reg_ch6blopcr
HW address:	0xe
C prefix:	CH6BLOPCR
C offset:	0x38

Channel 6 Pulse Counter Register for BLO pulses

31	30	29	28	27	26	25	24
CH6BLOPCR[31:24]

23	22	21	20	19	18	17	16
CH6BLOPCR[23:16]

15	14	13	12	11	10	9	8
CH6BLOPCR[15:8]

7	6	5	4	3	2	1	0
CH6BLOPCR[7:0]

CH6BLOPCR [read/write]: BLO pulse counter value

3.16. TVLR

HW prefix:	reg_tvlr
HW address:	0xf
C prefix:	TVLR
C offset:	0x3c

Time Value Low Register

31	30	29	28	27	26	25	24
TVLR[31:24]

23	22	21	20	19	18	17	16
TVLR[23:16]

15	14	13	12	11	10	9	8
TVLR[15:8]

7	6	5	4	3	2	1	0
TVLR[7:0]

TVLR [read/write]: TAI seconds counter bits 31..0
Writing this field resets the internal cycles counter.

3.17. TVHR

HW prefix:	reg_tvhr
HW address:	0x10
C prefix:	TVHR
C offset:	0x40

Time Value High Register

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-

7	6	5	4	3	2	1	0
TVHR[7:0]

TVHR [read/write]: TAI seconds counter bits 39..32
Writing this field resets the internal cycles counter.

3.18. TBMR

HW prefix:	reg_tbmr
HW address:	0x11
C prefix:	TBMR
C offset:	0x44

Tag Buffer Meta Register

31	30	29	28	27	26	25	24
WRTAG	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-

7	6	5	4	3	2	1	0
-	-	CHAN[5:0]

CHAN [read-only]: Channel mask
Mask for the channel(s) that triggered time-tag storage:
bit 0 -- channel 1
bit 1 -- channel 2
...
bit 5 -- channel 6
WRTAG [read-only]: White Rabbit present
1 - Current time tag generated with White Rabbit
0 - Current time tag generated with internal counter

3.19. TBCYR

HW prefix:	reg_tbcyr
HW address:	0x12
C prefix:	TBCYR
C offset:	0x48

Tag Buffer Cycles Register

31	30	29	28	27	26	25	24
-	-	-	-	TBCYR[27:24]

23	22	21	20	19	18	17	16
TBCYR[23:16]

15	14	13	12	11	10	9	8
TBCYR[15:8]

7	6	5	4	3	2	1	0
TBCYR[7:0]

TBCYR [read-only]: Cycles counter
Value of the 8-ns cycles counter when time tag was taken.

3.20. TBTLR

HW prefix:	reg_tbtlr
HW address:	0x13
C prefix:	TBTLR
C offset:	0x4c

Tag Buffer TAI Low Register

31	30	29	28	27	26	25	24
TBTLR[31:24]

23	22	21	20	19	18	17	16
TBTLR[23:16]

15	14	13	12	11	10	9	8
TBTLR[15:8]

7	6	5	4	3	2	1	0
TBTLR[7:0]

TBTLR [read-only]: Lower part of TAI seconds counter
Value of the TAI seconds counter bits 31..0 when time tag was taken.

3.21. TBTHR

HW prefix:	reg_tbthr
HW address:	0x14
C prefix:	TBTHR
C offset:	0x50

Tag Buffer TAI High Register

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-

7	6	5	4	3	2	1	0
TBTHR[7:0]

TBTHR [read-only]: Upper part of TAI seconds counter
Value of the TAI seconds counter bits 39..32 when time tag was taken.

3.22. TBCSR

HW prefix:	reg_tbcsr
HW address:	0x15
C prefix:	TBCSR
C offset:	0x54

Tag Buffer Control and Status Register

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	CLR	EMPTY	FULL

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-

7	6	5	4	3	2	1	0
-	USEDW[6:0]

USEDW [read-only]: Buffer counter
Number of samples in the ring buffer
FULL [read-only]: Buffer full
1 -- buffer full
0 -- buffer is not full
EMPTY [read-only]: Buffer empty
1 -- buffer empty
0 -- buffer is not empty
CLR [read/write]: Clear tag buffer
1 -- clear
0 -- no effect

3.23. CH1LTSCYR

HW prefix:	reg_ch1ltscyr
HW address:	0x16
C prefix:	CH1LTSCYR
C offset:	0x58

Channel 1 Latest Timestamp Cycles Register

31	30	29	28	27	26	25	24
-	-	-	-	CH1LTSCYR[27:24]

23	22	21	20	19	18	17	16
CH1LTSCYR[23:16]

15	14	13	12	11	10	9	8
CH1LTSCYR[15:8]

7	6	5	4	3	2	1	0
CH1LTSCYR[7:0]

CH1LTSCYR [read-only]: Cycles counter
Value of the 8-ns cycles counter when time tag was taken.

3.24. CH1LTSTLR

HW prefix:	reg_ch1ltstlr
HW address:	0x17
C prefix:	CH1LTSTLR
C offset:	0x5c

Channel 1 Latest Timestamp TAI Low Register

31	30	29	28	27	26	25	24
CH1LTSTLR[31:24]

23	22	21	20	19	18	17	16
CH1LTSTLR[23:16]

15	14	13	12	11	10	9	8
CH1LTSTLR[15:8]

7	6	5	4	3	2	1	0
CH1LTSTLR[7:0]

CH1LTSTLR [read-only]: Lower part of TAI seconds counter
Value of the TAI seconds counter bits 31..0 when time tag was taken.

3.25. CH1LTSTHR

HW prefix:	reg_ch1ltsthr
HW address:	0x18
C prefix:	CH1LTSTHR
C offset:	0x60

Channel 1 Latest Timestamp TAI High Register

31	30	29	28	27	26	25	24
WRTAG	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-

7	6	5	4	3	2	1	0
TAI[7:0]

TAI [read-only]: Upper part of TAI seconds counter
Value of the TAI seconds counter bits 39..32 when time tag was taken.
WRTAG [read-only]: White Rabbit present
1 - Current time tag generated with White Rabbit
0 - Current time tag generated with internal counter

3.26. CH2LTSCYR

HW prefix:	reg_ch2ltscyr
HW address:	0x19
C prefix:	CH2LTSCYR
C offset:	0x64

Channel 2 Latest Timestamp Cycles Register

31	30	29	28	27	26	25	24
-	-	-	-	CH2LTSCYR[27:24]

23	22	21	20	19	18	17	16
CH2LTSCYR[23:16]

15	14	13	12	11	10	9	8
CH2LTSCYR[15:8]

7	6	5	4	3	2	1	0
CH2LTSCYR[7:0]

CH2LTSCYR [read-only]: Cycles counter
Value of the 8-ns cycles counter when time tag was taken.

3.27. CH2LTSTLR

HW prefix:	reg_ch2ltstlr
HW address:	0x1a
C prefix:	CH2LTSTLR
C offset:	0x68

Channel 2 Latest Timestamp TAI Low Register

31	30	29	28	27	26	25	24
CH2LTSTLR[31:24]

23	22	21	20	19	18	17	16
CH2LTSTLR[23:16]

15	14	13	12	11	10	9	8
CH2LTSTLR[15:8]

7	6	5	4	3	2	1	0
CH2LTSTLR[7:0]

CH2LTSTLR [read-only]: Lower part of TAI seconds counter
Value of the TAI seconds counter bits 31..0 when time tag was taken.

3.28. CH2LTSTHR

HW prefix:	reg_ch2ltsthr
HW address:	0x1b
C prefix:	CH2LTSTHR
C offset:	0x6c

Channel 2 Latest Timestamp TAI High Register

31	30	29	28	27	26	25	24
WRTAG	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-

7	6	5	4	3	2	1	0
TAI[7:0]

TAI [read-only]: Upper part of TAI seconds counter
Value of the TAI seconds counter bits 39..32 when time tag was taken.
WRTAG [read-only]: White Rabbit present
1 - Current time tag generated with White Rabbit
0 - Current time tag generated with internal counter

3.29. CH3LTSCYR

HW prefix:	reg_ch3ltscyr
HW address:	0x1c
C prefix:	CH3LTSCYR
C offset:	0x70

Channel 3 Latest Timestamp Cycles Register

31	30	29	28	27	26	25	24
-	-	-	-	CH3LTSCYR[27:24]

23	22	21	20	19	18	17	16
CH3LTSCYR[23:16]

15	14	13	12	11	10	9	8
CH3LTSCYR[15:8]

7	6	5	4	3	2	1	0
CH3LTSCYR[7:0]

CH3LTSCYR [read-only]: Cycles counter
Value of the 8-ns cycles counter when time tag was taken.

3.30. CH3LTSTLR

HW prefix:	reg_ch3ltstlr
HW address:	0x1d
C prefix:	CH3LTSTLR
C offset:	0x74

Channel 3 Latest Timestamp TAI Low Register

31	30	29	28	27	26	25	24
CH3LTSTLR[31:24]

23	22	21	20	19	18	17	16
CH3LTSTLR[23:16]

15	14	13	12	11	10	9	8
CH3LTSTLR[15:8]

7	6	5	4	3	2	1	0
CH3LTSTLR[7:0]

CH3LTSTLR [read-only]: Lower part of TAI seconds counter
Value of the TAI seconds counter bits 31..0 when time tag was taken.

3.31. CH3LTSTHR

HW prefix:	reg_ch3ltsthr
HW address:	0x1e
C prefix:	CH3LTSTHR
C offset:	0x78

Channel 3 Latest Timestamp TAI High Register

31	30	29	28	27	26	25	24
WRTAG	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-

7	6	5	4	3	2	1	0
TAI[7:0]

TAI [read-only]: Upper part of TAI seconds counter
Value of the TAI seconds counter bits 39..32 when time tag was taken.
WRTAG [read-only]: White Rabbit present
1 - Current time tag generated with White Rabbit
0 - Current time tag generated with internal counter

3.32. CH4LTSCYR

HW prefix:	reg_ch4ltscyr
HW address:	0x1f
C prefix:	CH4LTSCYR
C offset:	0x7c

Channel 4 Latest Timestamp Cycles Register

31	30	29	28	27	26	25	24
-	-	-	-	CH4LTSCYR[27:24]

23	22	21	20	19	18	17	16
CH4LTSCYR[23:16]

15	14	13	12	11	10	9	8
CH4LTSCYR[15:8]

7	6	5	4	3	2	1	0
CH4LTSCYR[7:0]

CH4LTSCYR [read-only]: Cycles counter
Value of the 8-ns cycles counter when time tag was taken.

3.33. CH4LTSTLR

HW prefix:	reg_ch4ltstlr
HW address:	0x20
C prefix:	CH4LTSTLR
C offset:	0x80

Channel 4 Latest Timestamp TAI Low Register

31	30	29	28	27	26	25	24
CH4LTSTLR[31:24]

23	22	21	20	19	18	17	16
CH4LTSTLR[23:16]

15	14	13	12	11	10	9	8
CH4LTSTLR[15:8]

7	6	5	4	3	2	1	0
CH4LTSTLR[7:0]

CH4LTSTLR [read-only]: Lower part of TAI seconds counter
Value of the TAI seconds counter bits 31..0 when time tag was taken.

3.34. CH4LTSTHR

HW prefix:	reg_ch4ltsthr
HW address:	0x21
C prefix:	CH4LTSTHR
C offset:	0x84

Channel 4 Latest Timestamp TAI High Register

31	30	29	28	27	26	25	24
WRTAG	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-

7	6	5	4	3	2	1	0
TAI[7:0]

TAI [read-only]: Upper part of TAI seconds counter
Value of the TAI seconds counter bits 39..32 when time tag was taken.
WRTAG [read-only]: White Rabbit present
1 - Current time tag generated with White Rabbit
0 - Current time tag generated with internal counter

3.35. CH5LTSCYR

HW prefix:	reg_ch5ltscyr
HW address:	0x22
C prefix:	CH5LTSCYR
C offset:	0x88

Channel 5 Latest Timestamp Cycles Register

31	30	29	28	27	26	25	24
-	-	-	-	CH5LTSCYR[27:24]

23	22	21	20	19	18	17	16
CH5LTSCYR[23:16]

15	14	13	12	11	10	9	8
CH5LTSCYR[15:8]

7	6	5	4	3	2	1	0
CH5LTSCYR[7:0]

CH5LTSCYR [read-only]: Cycles counter
Value of the 8-ns cycles counter when time tag was taken.

3.36. CH5LTSTLR

HW prefix:	reg_ch5ltstlr
HW address:	0x23
C prefix:	CH5LTSTLR
C offset:	0x8c

Channel 5 Latest Timestamp TAI Low Register

31	30	29	28	27	26	25	24
CH5LTSTLR[31:24]

23	22	21	20	19	18	17	16
CH5LTSTLR[23:16]

15	14	13	12	11	10	9	8
CH5LTSTLR[15:8]

7	6	5	4	3	2	1	0
CH5LTSTLR[7:0]

CH5LTSTLR [read-only]: Lower part of TAI seconds counter
Value of the TAI seconds counter bits 31..0 when time tag was taken.

3.37. CH5LTSTHR

HW prefix:	reg_ch5ltsthr
HW address:	0x24
C prefix:	CH5LTSTHR
C offset:	0x90

Channel 5 Latest Timestamp TAI High Register

31	30	29	28	27	26	25	24
WRTAG	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-

7	6	5	4	3	2	1	0
TAI[7:0]

TAI [read-only]: Upper part of TAI seconds counter
Value of the TAI seconds counter bits 39..32 when time tag was taken.
WRTAG [read-only]: White Rabbit present
1 - Current time tag generated with White Rabbit
0 - Current time tag generated with internal counter

3.38. CH6LTSCYR

HW prefix:	reg_ch6ltscyr
HW address:	0x25
C prefix:	CH6LTSCYR
C offset:	0x94

Channel 6 Latest Timestamp Cycles Register

31	30	29	28	27	26	25	24
-	-	-	-	CH6LTSCYR[27:24]

23	22	21	20	19	18	17	16
CH6LTSCYR[23:16]

15	14	13	12	11	10	9	8
CH6LTSCYR[15:8]

7	6	5	4	3	2	1	0
CH6LTSCYR[7:0]

CH6LTSCYR [read-only]: Cycles counter
Value of the 8-ns cycles counter when time tag was taken.

3.39. CH6LTSTLR

HW prefix:	reg_ch6ltstlr
HW address:	0x26
C prefix:	CH6LTSTLR
C offset:	0x98

Channel 6 Latest Timestamp TAI Low Register

31	30	29	28	27	26	25	24
CH6LTSTLR[31:24]

23	22	21	20	19	18	17	16
CH6LTSTLR[23:16]

15	14	13	12	11	10	9	8
CH6LTSTLR[15:8]

7	6	5	4	3	2	1	0
CH6LTSTLR[7:0]

CH6LTSTLR [read-only]: Lower part of TAI seconds counter
Value of the TAI seconds counter bits 31..0 when time tag was taken.

3.40. CH6LTSTHR

HW prefix:	reg_ch6ltsthr
HW address:	0x27
C prefix:	CH6LTSTHR
C offset:	0x9c

Channel 6 Latest Timestamp TAI High Register

31	30	29	28	27	26	25	24
WRTAG	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-

7	6	5	4	3	2	1	0
TAI[7:0]

TAI [read-only]: Upper part of TAI seconds counter
Value of the TAI seconds counter bits 39..32 when time tag was taken.
WRTAG [read-only]: White Rabbit present
1 - Current time tag generated with White Rabbit
0 - Current time tag generated with internal counter

3.41. LSR

HW prefix:	reg_lsr
HW address:	0x28
C prefix:	LSR
C offset:	0xa0

Line Status Register

31	30	29	28	27	26	25	24
REARFS[5:0]						FRONTINVFS[3:2]

23	22	21	20	19	18	17	16
FRONTINVFS[1:0]		FRONTFS[5:0]

15	14	13	12	11	10	9	8
REAR[5:0]						FRONTINV[3:2]

7	6	5	4	3	2	1	0
FRONTINV[1:0]		FRONT[5:0]

FRONT [read-only]: Front panel channel input state
Line state at board input
Bit 0 -- channel 1
Bit 1 -- channel 2
etc.
FRONTINV [read-only]: Front panel INV-TTL input state
Line state at board input
Bit 0 -- channel 1
Bit 1 -- channel 2
etc.
REAR [read-only]: Rear panel input state
Line state at board input
Bit 0 -- channel 1
Bit 1 -- channel 2
etc.
FRONTFS [read-only]: Front panel input failsafe state
High if line is in failsafe mode (e.g., no cable plugged in)
Bit 0 -- channel 1
Bit 1 -- channel 2
etc.
FRONTINVFS [read-only]: Front panel inverter input failsafe state
High if line is in failsafe mode (e.g., no cable plugged in)
Bit 0 -- channel 1
Bit 1 -- channel 2
etc.
REARFS [read-only]: Rear panel input failsafe state
High if line is in failsafe mode (e.g., no cable plugged in)
Bit 0 -- channel 1
Bit 1 -- channel 2
etc.

3.42. OSWR

HW prefix:	reg_oswr
HW address:	0x29
C prefix:	OSWR
C offset:	0xa4

Other Switch Register

31	30	29	28	27	26	25	24
SWITCHES[31:24]

23	22	21	20	19	18	17	16
SWITCHES[23:16]

15	14	13	12	11	10	9	8
SWITCHES[15:8]

7	6	5	4	3	2	1	0
SWITCHES[7:0]

SWITCHES [read-only]: Switch state
1 -- switch is ON
0 -- switch is OFF

3.43. UIDLR

HW prefix:	reg_uidlr
HW address:	0x2a
C prefix:	UIDLR
C offset:	0xa8

32 LS bits of 1-wire thermometer ID

31	30	29	28	27	26	25	24
UIDLR[31:24]

23	22	21	20	19	18	17	16
UIDLR[23:16]

15	14	13	12	11	10	9	8
UIDLR[15:8]

7	6	5	4	3	2	1	0
UIDLR[7:0]

UIDLR [read-only]: LS bits of 1-wire DS18B20U thermometer ID

3.44. UIDHR

HW prefix:	reg_uidhr
HW address:	0x2b
C prefix:	UIDHR
C offset:	0xac

32 MS bits of 1-wire thermometer ID

31	30	29	28	27	26	25	24
UIDHR[31:24]

23	22	21	20	19	18	17	16
UIDHR[23:16]

15	14	13	12	11	10	9	8
UIDHR[15:8]

7	6	5	4	3	2	1	0
UIDHR[7:0]

UIDHR [read-only]: MS bits of 1-wire DS18B20U thermometer ID

3.45. TEMPR

HW prefix:	reg_tempr
HW address:	0x2c
C prefix:	TEMPR
C offset:	0xb0

Raw temperature data from the one wire DS18B20U. The register is 2-bytes long; it translates to oC as follows: temp = ((byte1 << 8) | byte0) / 16.0

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
TEMPR[15:8]

7	6	5	4	3	2	1	0
TEMPR[7:0]

TEMPR [read-only]: TEMP
Current on-board temperature

conv_regs

Converter board registers

Contents: