# conv_regs

### Converter board registers

### Contents:

1. Memory map summary
2. HDL symbol
3. Register description
3.1. BIDR
3.2. SR
3.3. ERR
3.4. CR
3.5. CH1FPPCR
3.6. CH2FPPCR
3.7. CH3FPPCR
3.8. CH4FPPCR
3.9. CH5FPPCR
3.10. CH6FPPCR
3.11. CH1RPPCR
3.12. CH2RPPCR
3.13. CH3RPPCR
3.14. CH4RPPCR
3.15. CH5RPPCR
3.16. CH6RPPCR
3.17. TVLR
3.18. TVHR
3.19. TBMR
3.20. TBCYR
3.21. TBTLR
3.22. TBTHR
3.23. TBCSR
3.24. CH1LTSCYR
3.25. CH1LTSTLR
3.26. CH1LTSTHR
3.27. CH2LTSCYR
3.28. CH2LTSTLR
3.29. CH2LTSTHR
3.30. CH3LTSCYR
3.31. CH3LTSTLR
3.32. CH3LTSTHR
3.33. CH4LTSCYR
3.34. CH4LTSTLR
3.35. CH4LTSTHR
3.36. CH5LTSCYR
3.37. CH5LTSTLR
3.38. CH5LTSTHR
3.39. CH6LTSCYR
3.40. CH6LTSTLR
3.41. CH6LTSTHR
3.42. LSR
3.43. OSWR
3.44. UIDLR
3.45. UIDHR
3.46. TEMPR

### 1. Memory map summary

H/W Address | Type | Name | VHDL/Verilog prefix | C prefix
--- | --- | --- | --- | ---
0x0 | REG | BIDR | reg_bidr | BIDR
0x1 | REG | SR | reg_sr | SR
0x2 | REG | ERR | reg_err | ERR
0x3 | REG | CR | reg_cr | CR
0x4 | REG | CH1FPPCR | reg_ch1fppcr | CH1FPPCR
0x5 | REG | CH2FPPCR | reg_ch2fppcr | CH2FPPCR
0x6 | REG | CH3FPPCR | reg_ch3fppcr | CH3FPPCR
0x7 | REG | CH4FPPCR | reg_ch4fppcr | CH4FPPCR
0x8 | REG | CH5FPPCR | reg_ch5fppcr | CH5FPPCR
0x9 | REG | CH6FPPCR | reg_ch6fppcr | CH6FPPCR
0xa | REG | CH1RPPCR | reg_ch1rppcr | CH1RPPCR
0xb | REG | CH2RPPCR | reg_ch2rppcr | CH2RPPCR
0xc | REG | CH3RPPCR | reg_ch3rppcr | CH3RPPCR
0xd | REG | CH4RPPCR | reg_ch4rppcr | CH4RPPCR
0xe | REG | CH5RPPCR | reg_ch5rppcr | CH5RPPCR
0xf | REG | CH6RPPCR | reg_ch6rppcr | CH6RPPCR
0x10 | REG | TVLR | reg_tvlr | TVLR
0x11 | REG | TVHR | reg_tvhr | TVHR
0x12 | REG | TBMR | reg_tbmr | TBMR
0x13 | REG | TBCYR | reg_tbcyr | TBCYR
0x14 | REG | TBTLR | reg_tbtlr | TBTLR
0x15 | REG | TBTHR | reg_tbthr | TBTHR
0x16 | REG | TBCSR | reg_tbcsr | TBCSR
0x17 | REG | CH1LTSCYR | reg_ch1ltscyr | CH1LTSCYR
0x18 | REG | CH1LTSTLR | reg_ch1ltstlr | CH1LTSTLR
0x19 | REG | CH1LTSTHR | reg_ch1ltsthr | CH1LTSTHR
0x1a | REG | CH2LTSCYR | reg_ch2ltscyr | CH2LTSCYR
0x1b | REG | CH2LTSTLR | reg_ch2ltstlr | CH2LTSTLR
0x1c | REG | CH2LTSTHR | reg_ch2ltsthr | CH2LTSTHR
0x1d | REG | CH3LTSCYR | reg_ch3ltscyr | CH3LTSCYR
0x1e | REG | CH3LTSTLR | reg_ch3ltstlr | CH3LTSTLR
0x1f | REG | CH3LTSTHR | reg_ch3ltsthr | CH3LTSTHR
0x20 | REG | CH4LTSCYR | reg_ch4ltscyr | CH4LTSCYR
0x21 | REG | CH4LTSTLR | reg_ch4ltstlr | CH4LTSTLR
0x22 | REG | CH4LTSTHR | reg_ch4ltsthr | CH4LTSTHR
0x23 | REG | CH5LTSCYR | reg_ch5ltscyr | CH5LTSCYR
0x24 | REG | CH5LTSTLR | reg_ch5ltstlr | CH5LTSTLR
0x25 | REG | CH5LTSTHR | reg_ch5ltsthr | CH5LTSTHR
0x26 | REG | CH6LTSCYR | reg_ch6ltscyr | CH6LTSCYR
0x27 | REG | CH6LTSTLR | reg_ch6ltstlr | CH6LTSTLR
0x28 | REG | CH6LTSTHR | reg_ch6ltsthr | CH6LTSTHR
0x29 | REG | LSR | reg_lsr | LSR
0x2a | REG | OSWR | reg_oswr | OSWR
0x2b | REG | UIDLR | reg_uidlr | UIDLR
0x2c | REG | UIDHR | reg_uidhr | UIDHR
0x2d | REG | TEMPR | reg_tempr | TEMPR

### 2. HDL symbol

→ | rst_n_i |  | BIDR: |
→ | clk_sys_i |  | reg_bidr_i[31:0] | ⇐
⇒ | wb_adr_i[5:0] |  |  |
⇒ | wb_dat_i[31:0] |  | SR: |
⇐ | wb_dat_o[31:0] |  | reg_sr_gwvers_i[7:0] | ⇐
→ | wb_cyc_i |  | reg_sr_switches_i[7:0] | ⇐
⇒ | wb_sel_i[3:0] |  | reg_sr_rtm_i[5:0] | ⇐
→ | wb_stb_i |  | reg_sr_hwvers_i[5:0] | ⇐
→ | wb_we_i |  | reg_sr_wrpres_i | ←
← | wb_ack_o |  |  |
← | wb_stall_o |  | ERR: |
|  |  | reg_err_i2c_wdto_o | →
|  |  | reg_err_i2c_wdto_i | ←
|  |  | reg_err_i2c_wdto_load_o | →
|  |  | reg_err_i2c_err_o | →
|  |  | reg_err_i2c_err_i | ←
|  |  | reg_err_i2c_err_load_o | →
|  |  | reg_err_flim_pmisse_o[5:0] | ⇒
|  |  | reg_err_flim_pmisse_i[5:0] | ⇐
|  |  | reg_err_flim_pmisse_load_o | →
|  |  | reg_err_fwdg_pmisse_o[5:0] | ⇒
|  |  | reg_err_fwdg_pmisse_i[5:0] | ⇐
|  |  | reg_err_fwdg_pmisse_load_o | →
|  |  | CR: |
|  |  | reg_cr_rst_unlock_o | →
|  |  | reg_cr_rst_unlock_i | ←
|  |  | reg_cr_rst_unlock_load_o | →
|  |  | reg_cr_rst_o | →
|  |  | reg_cr_rst_i | ←
|  |  | reg_cr_rst_load_o | →
|  |  | reg_cr_mpt_o[7:0] | ⇒
|  |  | reg_cr_mpt_wr_o | →
|  |  | CH1FPPCR: |
|  |  | reg_ch1fppcr_o[31:0] | ⇒
|  |  | reg_ch1fppcr_i[31:0] | ⇐
|  |  | reg_ch1fppcr_load_o | →
|  |  | CH2FPPCR: |
|  |  | reg_ch2fppcr_o[31:0] | ⇒
|  |  | reg_ch2fppcr_i[31:0] | ⇐
|  |  | reg_ch2fppcr_load_o | →
|  |  | CH3FPPCR: |
|  |  | reg_ch3fppcr_o[31:0] | ⇒
|  |  | reg_ch3fppcr_i[31:0] | ⇐
|  |  | reg_ch3fppcr_load_o | →
|  |  | CH4FPPCR: |
|  |  | reg_ch4fppcr_o[31:0] | ⇒
|  |  | reg_ch4fppcr_i[31:0] | ⇐
|  |  | reg_ch4fppcr_load_o | →
|  |  | CH5FPPCR: |
|  |  | reg_ch5fppcr_o[31:0] | ⇒
|  |  | reg_ch5fppcr_i[31:0] | ⇐
|  |  | reg_ch5fppcr_load_o | →
|  |  | CH6FPPCR: |
|  |  | reg_ch6fppcr_o[31:0] | ⇒
|  |  | reg_ch6fppcr_i[31:0] | ⇐
|  |  | reg_ch6fppcr_load_o | →
|  |  | CH1RPPCR: |
|  |  | reg_ch1rppcr_o[31:0] | ⇒
|  |  | reg_ch1rppcr_i[31:0] | ⇐
|  |  | reg_ch1rppcr_load_o | →
|  |  | CH2RPPCR: |
|  |  | reg_ch2rppcr_o[31:0] | ⇒
|  |  | reg_ch2rppcr_i[31:0] | ⇐
|  |  | reg_ch2rppcr_load_o | →
|  |  | CH3RPPCR: |
|  |  | reg_ch3rppcr_o[31:0] | ⇒
|  |  | reg_ch3rppcr_i[31:0] | ⇐
|  |  | reg_ch3rppcr_load_o | →
|  |  | CH4RPPCR: |
|  |  | reg_ch4rppcr_o[31:0] | ⇒
|  |  | reg_ch4rppcr_i[31:0] | ⇐
|  |  | reg_ch4rppcr_load_o | →
|  |  | CH5RPPCR: |
|  |  | reg_ch5rppcr_o[31:0] | ⇒
|  |  | reg_ch5rppcr_i[31:0] | ⇐
|  |  | reg_ch5rppcr_load_o | →
|  |  | CH6RPPCR: |
|  |  | reg_ch6rppcr_o[31:0] | ⇒
|  |  | reg_ch6rppcr_i[31:0] | ⇐
|  |  | reg_ch6rppcr_load_o | →
|  |  | TVLR: |
|  |  | reg_tvlr_o[31:0] | ⇒
|  |  | reg_tvlr_i[31:0] | ⇐
|  |  | reg_tvlr_load_o | →
|  |  | TVHR: |
|  |  | reg_tvhr_o[7:0] | ⇒
|  |  | reg_tvhr_i[7:0] | ⇐
|  |  | reg_tvhr_load_o | →
|  |  | TBMR: |
|  |  | reg_tbmr_chan_i[5:0] | ⇐
|  |  | reg_tb_rd_req_p_o | →
|  |  | reg_tbmr_wrtag_i | ←
|  |  | TBCYR: |
|  |  | reg_tbcyr_i[27:0] | ⇐
|  |  | TBTLR: |
|  |  | reg_tbtlr_i[31:0] | ⇐
|  |  | TBTHR: |
|  |  | reg_tbthr_i[7:0] | ⇐
|  |  | TBCSR: |
|  |  | reg_tbcsr_usedw_i[6:0] | ⇐
|  |  | reg_tbcsr_full_i | ←
|  |  | reg_tbcsr_empty_i | ←
|  |  | reg_tbcsr_clr_o | →
|  |  | reg_tbcsr_clr_i | ←
|  |  | reg_tbcsr_clr_load_o | →
|  |  | CH1LTSCYR: |
|  |  | reg_ch1ltscyr_i[27:0] | ⇐
|  |  | CH1LTSTLR: |
|  |  | reg_ch1ltstlr_i[31:0] | ⇐
|  |  | CH1LTSTHR: |
|  |  | reg_ch1ltsthr_tai_i[7:0] | ⇐
|  |  | reg_ch1ltsthr_wrtag_i | ←
|  |  | CH2LTSCYR: |
|  |  | reg_ch2ltscyr_i[27:0] | ⇐
|  |  | CH2LTSTLR: |
|  |  | reg_ch2ltstlr_i[31:0] | ⇐
|  |  | CH2LTSTHR: |
|  |  | reg_ch2ltsthr_tai_i[7:0] | ⇐
|  |  | reg_ch2ltsthr_wrtag_i | ←
|  |  | CH3LTSCYR: |
|  |  | reg_ch3ltscyr_i[27:0] | ⇐
|  |  | CH3LTSTLR: |
|  |  | reg_ch3ltstlr_i[31:0] | ⇐
|  |  | CH3LTSTHR: |
|  |  | reg_ch3ltsthr_tai_i[7:0] | ⇐
|  |  | reg_ch3ltsthr_wrtag_i | ←
|  |  | CH4LTSCYR: |
|  |  | reg_ch4ltscyr_i[27:0] | ⇐
|  |  | CH4LTSTLR: |
|  |  | reg_ch4ltstlr_i[31:0] | ⇐
|  |  | CH4LTSTHR: |
|  |  | reg_ch4ltsthr_tai_i[7:0] | ⇐
|  |  | reg_ch4ltsthr_wrtag_i | ←
|  |  | CH5LTSCYR: |
|  |  | reg_ch5ltscyr_i[27:0] | ⇐
|  |  | CH5LTSTLR: |
|  |  | reg_ch5ltstlr_i[31:0] | ⇐
|  |  | CH5LTSTHR: |
|  |  | reg_ch5ltsthr_tai_i[7:0] | ⇐
|  |  | reg_ch5ltsthr_wrtag_i | ←
|  |  | CH6LTSCYR: |
|  |  | reg_ch6ltscyr_i[27:0] | ⇐
|  |  | CH6LTSTLR: |
|  |  | reg_ch6ltstlr_i[31:0] | ⇐
|  |  | CH6LTSTHR: |
|  |  | reg_ch6ltsthr_tai_i[7:0] | ⇐
|  |  | reg_ch6ltsthr_wrtag_i | ←
|  |  | LSR: |
|  |  | reg_lsr_front_i[5:0] | ⇐
|  |  | reg_lsr_frontinv_i[3:0] | ⇐
|  |  | reg_lsr_rear_i[5:0] | ⇐
|  |  | reg_lsr_frontfs_i[5:0] | ⇐
|  |  | reg_lsr_frontinvfs_i[3:0] | ⇐
|  |  | reg_lsr_rearfs_i[5:0] | ⇐
|  |  | OSWR: |
|  |  | reg_oswr_switches_i[31:0] | ⇐
|  |  | UIDLR: |
|  |  | reg_uidlr_i[31:0] | ⇐
|  |  | UIDHR: |
|  |  | reg_uidhr_i[31:0] | ⇐
|  |  | TEMPR: |
|  |  | reg_tempr_i[15:0] | ⇐

### 3. Register description

### 3.1. BIDR

HW prefix: | reg_bidr
HW address: | 0x0
C prefix: | BIDR
C offset: | 0x0

Board ID Register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
BIDR[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
BIDR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
BIDR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
BIDR[7:0] |  |  |  |  |  |  |

- BIDR [read-only]: ID register bits

### 3.2. SR

HW prefix: | reg_sr
HW address: | 0x1
C prefix: | SR
C offset: | 0x4

Status Register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | WRPRES | HWVERS[5:2] |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
HWVERS[1:0] | RTM[5:0] |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
SWITCHES[7:0] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
GWVERS[7:0] |  |  |  |  |  |  |

- GWVERS [read-only]: Gateware version
  Leftmost nibble hex value is major release decimal value
  Rightmost nibble hex value is minor release decimal value
  e.g.
  0x11 -- v1.1
  0x2e -- v2.14
- SWITCHES [read-only]: Status of on-board general-purpose switches
  Eg: SW1.1-- SR.SWITCHES[0]
  SW1.2-- SR.SWITCHES[1]
  SW2.1-- SR.SWITCHES[4]
  SW2.4-- SR.SWITCHES[7]
  1 -- switch is ON
  0 -- switch is OFF
- RTM [read-only]: RTM detection lines cite{rtm-det}
  1 bit per RTM output channel
  1 -- line active
  0 -- line inactive
- HWVERS [read-only]: Hardware version
  PCB version - Hardwired on the board
  Only meaningful for HW v4.0 and over
  Earlier versions show 0. The register
  uses 4 bits for the version number and
  2 bits for the execution.
  e.g.
  0x010001 -- hw v4.1
  0x010111 -- hw v5.3
  0x00-- hw v3 and earlier
- WRPRES [read-only]: White Rabbit present
  1 -- White Rabbit present
  0 -- White Rabbit not present

### 3.3. ERR

HW prefix: | reg_err
HW address: | 0x2
C prefix: | ERR
C offset: | 0x8

Error Register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | FWDG_PMISSE[5:0] |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
FLIM_PMISSE[5:0] | I2C_ERR | I2C_WDTO |  |  |  |  |

- I2C_WDTO [read/write]: I2C communication watchdog timeout error
  1 -- timeout occured
  0 -- no timeout
  This bit can be cleared by writing a '1' to it
- I2C_ERR [read/write]: I2C communication error
  1 -- attempted to address non-existing address
  0 -- idle
  This bit can be cleared by writing a '1' to it
- FLIM_PMISSE [read/write]: Frequency error
  1 -- Input above maximum supported frequency
  0 -- idle
  Bit 0 -- channel 1
  Bit 1 -- channel 2
  etc.
  Each bit can be cleared by writing a '1' to it
- FWDG_PMISSE [read/write]: Frequency watchdog error
  1 -- Pulse over maximum pulse count for given frequency'
  0 -- idle
  Bit 0 -- channel 1
  Bit 1 -- channel 2
  etc.
  Each bit can be cleared by writing a '1' to it

### 3.4. CR

HW prefix: | reg_cr
HW address: | 0x3
C prefix: | CR
C offset: | 0xc

Control Register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | MPT[7:6] |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
MPT[5:0] | RST | RST_UNLOCK |  |  |  |  |

- RST_UNLOCK [read/write]: Reset unlock bit
  1 -- Reset bit unlocked
  0 -- Reset bit locked
- RST [read/write]: Reset bit - active only if RST_UNLOCK is 1
  1 -- initiate logic reset
  0 -- no reset
- MPT [write-only]: Manual Pulse Trigger
  Write the following sequence to trigger a pulse:
  0xde -- Byte 1 of magic sequence
  0xad -- Byte 2 of magic sequence
  0xbe -- Byte 3 of magic sequence
  0xef -- Byte 4 of magic sequence
  Number in range 1..6 -- trigger a pulse

### 3.5. CH1FPPCR

HW prefix: | reg_ch1fppcr
HW address: | 0x4
C prefix: | CH1FPPCR
C offset: | 0x10

Channel 1 Pulse Counter Register for front panel pulses

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH1FPPCR[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH1FPPCR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH1FPPCR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH1FPPCR[7:0] |  |  |  |  |  |  |

- CH1FPPCR [read/write]: Value of front panel pulse counter

### 3.6. CH2FPPCR

HW prefix: | reg_ch2fppcr
HW address: | 0x5
C prefix: | CH2FPPCR
C offset: | 0x14

Channel 2 Pulse Counter Register for front panel pulses

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH2FPPCR[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH2FPPCR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH2FPPCR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH2FPPCR[7:0] |  |  |  |  |  |  |

- CH2FPPCR [read/write]: Value of front panel pulse counter

### 3.7. CH3FPPCR

HW prefix: | reg_ch3fppcr
HW address: | 0x6
C prefix: | CH3FPPCR
C offset: | 0x18

Channel 3 Pulse Counter Register for front panel pulses

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH3FPPCR[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH3FPPCR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH3FPPCR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH3FPPCR[7:0] |  |  |  |  |  |  |

- CH3FPPCR [read/write]: Value of front panel pulse counter

### 3.8. CH4FPPCR

HW prefix: | reg_ch4fppcr
HW address: | 0x7
C prefix: | CH4FPPCR
C offset: | 0x1c

Channel 4 Pulse Counter Register for front panel pulses

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH4FPPCR[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH4FPPCR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH4FPPCR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH4FPPCR[7:0] |  |  |  |  |  |  |

- CH4FPPCR [read/write]: Value of front panel pulse counter

### 3.9. CH5FPPCR

HW prefix: | reg_ch5fppcr
HW address: | 0x8
C prefix: | CH5FPPCR
C offset: | 0x20

Channel 5 Pulse Counter Register for front panel pulses

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH5FPPCR[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH5FPPCR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH5FPPCR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH5FPPCR[7:0] |  |  |  |  |  |  |

- CH5FPPCR [read/write]: Value of front panel pulse counter

### 3.10. CH6FPPCR

HW prefix: | reg_ch6fppcr
HW address: | 0x9
C prefix: | CH6FPPCR
C offset: | 0x24

Channel 6 Pulse Counter Register for front panel pulses

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH6FPPCR[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH6FPPCR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH6FPPCR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH6FPPCR[7:0] |  |  |  |  |  |  |

- CH6FPPCR [read/write]: Value of front panel pulse counter

### 3.11. CH1RPPCR

HW prefix: | reg_ch1rppcr
HW address: | 0xa
C prefix: | CH1RPPCR
C offset: | 0x28

Channel 1 Pulse Counter Register for rear panel pulses

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH1RPPCR[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH1RPPCR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH1RPPCR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH1RPPCR[7:0] |  |  |  |  |  |  |

- CH1RPPCR [read/write]: Rear panel pulse counter value

### 3.12. CH2RPPCR

HW prefix: | reg_ch2rppcr
HW address: | 0xb
C prefix: | CH2RPPCR
C offset: | 0x2c

Channel 2 Pulse Counter Register for rear panel pulses

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH2RPPCR[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH2RPPCR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH2RPPCR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH2RPPCR[7:0] |  |  |  |  |  |  |

- CH2RPPCR [read/write]: Rear panel pulse counter value

### 3.13. CH3RPPCR

HW prefix: | reg_ch3rppcr
HW address: | 0xc
C prefix: | CH3RPPCR
C offset: | 0x30

Channel 3 Pulse Counter Register for rear panel pulses

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH3RPPCR[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH3RPPCR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH3RPPCR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH3RPPCR[7:0] |  |  |  |  |  |  |

- CH3RPPCR [read/write]: Rear panel pulse counter value

### 3.14. CH4RPPCR

HW prefix: | reg_ch4rppcr
HW address: | 0xd
C prefix: | CH4RPPCR
C offset: | 0x34

Channel 4 Pulse Counter Register for rear panel pulses

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH4RPPCR[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH4RPPCR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH4RPPCR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH4RPPCR[7:0] |  |  |  |  |  |  |

- CH4RPPCR [read/write]: Rear panel pulse counter value

### 3.15. CH5RPPCR

HW prefix: | reg_ch5rppcr
HW address: | 0xe
C prefix: | CH5RPPCR
C offset: | 0x38

Channel 5 Pulse Counter Register for rear panel pulses

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH5RPPCR[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH5RPPCR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH5RPPCR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH5RPPCR[7:0] |  |  |  |  |  |  |

- CH5RPPCR [read/write]: Rear panel pulse counter value

### 3.16. CH6RPPCR

HW prefix: | reg_ch6rppcr
HW address: | 0xf
C prefix: | CH6RPPCR
C offset: | 0x3c

Channel 6 Pulse Counter Register for rear panel pulses

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH6RPPCR[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH6RPPCR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH6RPPCR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH6RPPCR[7:0] |  |  |  |  |  |  |

- CH6RPPCR [read/write]: Rear panel pulse counter value

### 3.17. TVLR

HW prefix: | reg_tvlr
HW address: | 0x10
C prefix: | TVLR
C offset: | 0x40

Time Value Low Register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TVLR[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
TVLR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TVLR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TVLR[7:0] |  |  |  |  |  |  |

- TVLR [read/write]: TAI seconds counter bits 31..0
  Writing this field resets the internal cycles counter.

### 3.18. TVHR

HW prefix: | reg_tvhr
HW address: | 0x11
C prefix: | TVHR
C offset: | 0x44

Time Value High Register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TVHR[7:0] |  |  |  |  |  |  |

- TVHR [read/write]: TAI seconds counter bits 39..32
  Writing this field resets the internal cycles counter.

### 3.19. TBMR

HW prefix: | reg_tbmr
HW address: | 0x12
C prefix: | TBMR
C offset: | 0x48

Tag Buffer Meta Register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
WRTAG | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | CHAN[5:0] |  |  |  |  |

- CHAN [read-only]: Channel mask
  Mask for the channel(s) that triggered time-tag storage:
  bit 0 -- channel 1
  bit 1 -- channel 2
  ...
  bit 5 -- channel 6
- WRTAG [read-only]: White Rabbit present
  1 - Current time tag generated with White Rabbit
  0 - Current time tag generated with internal counter

### 3.20. TBCYR

HW prefix: | reg_tbcyr
HW address: | 0x13
C prefix: | TBCYR
C offset: | 0x4c

Tag Buffer Cycles Register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | TBCYR[27:24] |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
TBCYR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TBCYR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TBCYR[7:0] |  |  |  |  |  |  |

- TBCYR [read-only]: Cycles counter
  Value of the 8-ns cycles counter when time tag was taken.

### 3.21. TBTLR

HW prefix: | reg_tbtlr
HW address: | 0x14
C prefix: | TBTLR
C offset: | 0x50

Tag Buffer TAI Low Register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TBTLR[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
TBTLR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TBTLR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TBTLR[7:0] |  |  |  |  |  |  |

- TBTLR [read-only]: Lower part of TAI seconds counter
  Value of the TAI seconds counter bits 31..0 when time tag was taken.

### 3.22. TBTHR

HW prefix: | reg_tbthr
HW address: | 0x15
C prefix: | TBTHR
C offset: | 0x54

Tag Buffer TAI High Register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TBTHR[7:0] |  |  |  |  |  |  |

- TBTHR [read-only]: Upper part of TAI seconds counter
  Value of the TAI seconds counter bits 39..32 when time tag was taken.

### 3.23. TBCSR

HW prefix: | reg_tbcsr
HW address: | 0x16
C prefix: | TBCSR
C offset: | 0x58

Tag Buffer Control and Status Register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | CLR | EMPTY | FULL

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | USEDW[6:0] |  |  |  |  |  |

- USEDW [read-only]: Buffer counter
  Number of samples in the ring buffer
- FULL [read-only]: Buffer full
  1 -- buffer full
  0 -- buffer is not full
- EMPTY [read-only]: Buffer empty
  1 -- buffer empty
  0 -- buffer is not empty
- CLR [read/write]: Clear tag buffer
  1 -- clear
  0 -- no effect

### 3.24. CH1LTSCYR

HW prefix: | reg_ch1ltscyr
HW address: | 0x17
C prefix: | CH1LTSCYR
C offset: | 0x5c

Channel 1 Latest Timestamp Cycles Register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | CH1LTSCYR[27:24] |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH1LTSCYR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH1LTSCYR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH1LTSCYR[7:0] |  |  |  |  |  |  |

- CH1LTSCYR [read-only]: Cycles counter
  Value of the 8-ns cycles counter when time tag was taken.

### 3.25. CH1LTSTLR

HW prefix: | reg_ch1ltstlr
HW address: | 0x18
C prefix: | CH1LTSTLR
C offset: | 0x60

Channel 1 Latest Timestamp TAI Low Register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH1LTSTLR[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH1LTSTLR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH1LTSTLR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH1LTSTLR[7:0] |  |  |  |  |  |  |

- CH1LTSTLR [read-only]: Lower part of TAI seconds counter
  Value of the TAI seconds counter bits 31..0 when time tag was taken.

### 3.26. CH1LTSTHR

HW prefix: | reg_ch1ltsthr
HW address: | 0x19
C prefix: | CH1LTSTHR
C offset: | 0x64

Channel 1 Latest Timestamp TAI High Register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
WRTAG | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TAI[7:0] |  |  |  |  |  |  |

- TAI [read-only]: Upper part of TAI seconds counter
  Value of the TAI seconds counter bits 39..32 when time tag was taken.
- WRTAG [read-only]: White Rabbit present
  1 - Current time tag generated with White Rabbit
  0 - Current time tag generated with internal counter

### 3.27. CH2LTSCYR

HW prefix: | reg_ch2ltscyr
HW address: | 0x1a
C prefix: | CH2LTSCYR
C offset: | 0x68

Channel 2 Latest Timestamp Cycles Register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | CH2LTSCYR[27:24] |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH2LTSCYR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH2LTSCYR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH2LTSCYR[7:0] |  |  |  |  |  |  |

- CH2LTSCYR [read-only]: Cycles counter
  Value of the 8-ns cycles counter when time tag was taken.

### 3.28. CH2LTSTLR

HW prefix: | reg_ch2ltstlr
HW address: | 0x1b
C prefix: | CH2LTSTLR
C offset: | 0x6c

Channel 2 Latest Timestamp TAI Low Register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH2LTSTLR[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH2LTSTLR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH2LTSTLR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH2LTSTLR[7:0] |  |  |  |  |  |  |

- CH2LTSTLR [read-only]: Lower part of TAI seconds counter
  Value of the TAI seconds counter bits 31..0 when time tag was taken.

### 3.29. CH2LTSTHR

HW prefix: | reg_ch2ltsthr
HW address: | 0x1c
C prefix: | CH2LTSTHR
C offset: | 0x70

Channel 2 Latest Timestamp TAI High Register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
WRTAG | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TAI[7:0] |  |  |  |  |  |  |

- TAI [read-only]: Upper part of TAI seconds counter
  Value of the TAI seconds counter bits 39..32 when time tag was taken.
- WRTAG [read-only]: White Rabbit present
  1 - Current time tag generated with White Rabbit
  0 - Current time tag generated with internal counter

### 3.30. CH3LTSCYR

HW prefix: | reg_ch3ltscyr
HW address: | 0x1d
C prefix: | CH3LTSCYR
C offset: | 0x74

Channel 3 Latest Timestamp Cycles Register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | CH3LTSCYR[27:24] |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH3LTSCYR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH3LTSCYR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH3LTSCYR[7:0] |  |  |  |  |  |  |

- CH3LTSCYR [read-only]: Cycles counter
  Value of the 8-ns cycles counter when time tag was taken.

### 3.31. CH3LTSTLR

HW prefix: | reg_ch3ltstlr
HW address: | 0x1e
C prefix: | CH3LTSTLR
C offset: | 0x78

Channel 3 Latest Timestamp TAI Low Register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH3LTSTLR[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH3LTSTLR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH3LTSTLR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH3LTSTLR[7:0] |  |  |  |  |  |  |

- CH3LTSTLR [read-only]: Lower part of TAI seconds counter
  Value of the TAI seconds counter bits 31..0 when time tag was taken.

### 3.32. CH3LTSTHR

HW prefix: | reg_ch3ltsthr
HW address: | 0x1f
C prefix: | CH3LTSTHR
C offset: | 0x7c

Channel 3 Latest Timestamp TAI High Register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
WRTAG | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TAI[7:0] |  |  |  |  |  |  |

- TAI [read-only]: Upper part of TAI seconds counter
  Value of the TAI seconds counter bits 39..32 when time tag was taken.
- WRTAG [read-only]: White Rabbit present
  1 - Current time tag generated with White Rabbit
  0 - Current time tag generated with internal counter

### 3.33. CH4LTSCYR

HW prefix: | reg_ch4ltscyr
HW address: | 0x20
C prefix: | CH4LTSCYR
C offset: | 0x80

Channel 4 Latest Timestamp Cycles Register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | CH4LTSCYR[27:24] |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH4LTSCYR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH4LTSCYR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH4LTSCYR[7:0] |  |  |  |  |  |  |

- CH4LTSCYR [read-only]: Cycles counter
  Value of the 8-ns cycles counter when time tag was taken.

### 3.34. CH4LTSTLR

HW prefix: | reg_ch4ltstlr
HW address: | 0x21
C prefix: | CH4LTSTLR
C offset: | 0x84

Channel 4 Latest Timestamp TAI Low Register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH4LTSTLR[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH4LTSTLR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH4LTSTLR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH4LTSTLR[7:0] |  |  |  |  |  |  |

- CH4LTSTLR [read-only]: Lower part of TAI seconds counter
  Value of the TAI seconds counter bits 31..0 when time tag was taken.

### 3.35. CH4LTSTHR

HW prefix: | reg_ch4ltsthr
HW address: | 0x22
C prefix: | CH4LTSTHR
C offset: | 0x88

Channel 4 Latest Timestamp TAI High Register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
WRTAG | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TAI[7:0] |  |  |  |  |  |  |

- TAI [read-only]: Upper part of TAI seconds counter
  Value of the TAI seconds counter bits 39..32 when time tag was taken.
- WRTAG [read-only]: White Rabbit present
  1 - Current time tag generated with White Rabbit
  0 - Current time tag generated with internal counter

### 3.36. CH5LTSCYR

HW prefix: | reg_ch5ltscyr
HW address: | 0x23
C prefix: | CH5LTSCYR
C offset: | 0x8c

Channel 5 Latest Timestamp Cycles Register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | CH5LTSCYR[27:24] |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH5LTSCYR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH5LTSCYR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH5LTSCYR[7:0] |  |  |  |  |  |  |

- CH5LTSCYR [read-only]: Cycles counter
  Value of the 8-ns cycles counter when time tag was taken.

### 3.37. CH5LTSTLR

HW prefix: | reg_ch5ltstlr
HW address: | 0x24
C prefix: | CH5LTSTLR
C offset: | 0x90

Channel 5 Latest Timestamp TAI Low Register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH5LTSTLR[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH5LTSTLR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH5LTSTLR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH5LTSTLR[7:0] |  |  |  |  |  |  |

- CH5LTSTLR [read-only]: Lower part of TAI seconds counter
  Value of the TAI seconds counter bits 31..0 when time tag was taken.

### 3.38. CH5LTSTHR

HW prefix: | reg_ch5ltsthr
HW address: | 0x25
C prefix: | CH5LTSTHR
C offset: | 0x94

Channel 5 Latest Timestamp TAI High Register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
WRTAG | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TAI[7:0] |  |  |  |  |  |  |

- TAI [read-only]: Upper part of TAI seconds counter
  Value of the TAI seconds counter bits 39..32 when time tag was taken.
- WRTAG [read-only]: White Rabbit present
  1 - Current time tag generated with White Rabbit
  0 - Current time tag generated with internal counter

### 3.39. CH6LTSCYR

HW prefix: | reg_ch6ltscyr
HW address: | 0x26
C prefix: | CH6LTSCYR
C offset: | 0x98

Channel 6 Latest Timestamp Cycles Register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | CH6LTSCYR[27:24] |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH6LTSCYR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH6LTSCYR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH6LTSCYR[7:0] |  |  |  |  |  |  |

- CH6LTSCYR [read-only]: Cycles counter
  Value of the 8-ns cycles counter when time tag was taken.

### 3.40. CH6LTSTLR

HW prefix: | reg_ch6ltstlr
HW address: | 0x27
C prefix: | CH6LTSTLR
C offset: | 0x9c

Channel 6 Latest Timestamp TAI Low Register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH6LTSTLR[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH6LTSTLR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH6LTSTLR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH6LTSTLR[7:0] |  |  |  |  |  |  |

- CH6LTSTLR [read-only]: Lower part of TAI seconds counter
  Value of the TAI seconds counter bits 31..0 when time tag was taken.

### 3.41. CH6LTSTHR

HW prefix: | reg_ch6ltsthr
HW address: | 0x28
C prefix: | CH6LTSTHR
C offset: | 0xa0

Channel 6 Latest Timestamp TAI High Register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
WRTAG | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TAI[7:0] |  |  |  |  |  |  |

- TAI [read-only]: Upper part of TAI seconds counter
  Value of the TAI seconds counter bits 39..32 when time tag was taken.
- WRTAG [read-only]: White Rabbit present
  1 - Current time tag generated with White Rabbit
  0 - Current time tag generated with internal counter

### 3.42. LSR

HW prefix: | reg_lsr
HW address: | 0x29
C prefix: | LSR
C offset: | 0xa4

Line Status Register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
REARFS[5:0] | FRONTINVFS[3:2] |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
FRONTINVFS[1:0] | FRONTFS[5:0] |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
REAR[5:0] | FRONTINV[3:2] |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
FRONTINV[1:0] | FRONT[5:0] |  |  |  |  |  |

- FRONT [read-only]: Front panel channel input state
  Line state at board input
  Bit 0 -- channel 1
  Bit 1 -- channel 2
  etc.
- FRONTINV [read-only]: Front panel INV-TTL input state
  Line state at board input
  Bit 0 -- channel 1
  Bit 1 -- channel 2
  etc.
- REAR [read-only]: Rear panel input state
  Line state at board input
  Bit 0 -- channel 1
  Bit 1 -- channel 2
  etc.
- FRONTFS [read-only]: Front panel input failsafe state
  High if line is in failsafe mode (e.g., no cable plugged in)
  Bit 0 -- channel 1
  Bit 1 -- channel 2
  etc.
- FRONTINVFS [read-only]: Front panel inverter input failsafe state
  High if line is in failsafe mode (e.g., no cable plugged in)
  Bit 0 -- channel 1
  Bit 1 -- channel 2
  etc.
- REARFS [read-only]: Rear panel input failsafe state
  High if line is in failsafe mode (e.g., no cable plugged in)
  Bit 0 -- channel 1
  Bit 1 -- channel 2
  etc.

### 3.43. OSWR

HW prefix: | reg_oswr
HW address: | 0x2a
C prefix: | OSWR
C offset: | 0xa8

Other Switch Register

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
SWITCHES[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
SWITCHES[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
SWITCHES[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SWITCHES[7:0] |  |  |  |  |  |  |

- SWITCHES [read-only]: Switch state
  1 -- switch is ON
  0 -- switch is OFF

### 3.44. UIDLR

HW prefix: | reg_uidlr
HW address: | 0x2b
C prefix: | UIDLR
C offset: | 0xac

32 LS bits of 1-wire thermometer ID

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
UIDLR[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
UIDLR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
UIDLR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
UIDLR[7:0] |  |  |  |  |  |  |

- UIDLR [read-only]: LS bits of 1-wire DS18B20U thermometer ID

### 3.45. UIDHR

HW prefix: | reg_uidhr
HW address: | 0x2c
C prefix: | UIDHR
C offset: | 0xb0

32 MS bits of 1-wire thermometer ID

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
UIDHR[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
UIDHR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
UIDHR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
UIDHR[7:0] |  |  |  |  |  |  |

- UIDHR [read-only]: MS bits of 1-wire DS18B20U thermometer ID

### 3.46. TEMPR

HW prefix: | reg_tempr
HW address: | 0x2d
C prefix: | TEMPR
C offset: | 0xb4

Raw temperature data from the one wire DS18B20U. The register is 2-bytes long; it translates to oC as follows: temp = ((byte1 << 8) | byte0) / 16.0

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TEMPR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TEMPR[7:0] |  |  |  |  |  |  |

- TEMPR [read-only]: TEMP
  Current on-board temperature