pax_global_header 0000666 0000000 0000000 00000000064 12375155472 0014525 g ustar 00root root 0000000 0000000 52 comment=8e4921b9be26327b1138c5ec9cd50b8a11b69d89
conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/ 0000775 0000000 0000000 00000000000 12375155472 0021326 5 ustar 00root root 0000000 0000000 conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/.gitmodules 0000664 0000000 0000000 00000000167 12375155472 0023507 0 ustar 00root root 0000000 0000000 [submodule "ip_cores/general-cores"]
path = ip_cores/general-cores
url = git@ohwr.org:hdl-core-lib/general-cores.git
conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/Manifest.py 0000664 0000000 0000000 00000000047 12375155472 0023447 0 ustar 00root root 0000000 0000000 modules = {
"local" : [ "top" ]
}
conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/README 0000664 0000000 0000000 00000000065 12375155472 0022207 0 ustar 00root root 0000000 0000000 Generic common gateware for converter board projects
conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/doc/ 0000775 0000000 0000000 00000000000 12375155472 0022073 5 ustar 00root root 0000000 0000000 conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/doc/Makefile 0000664 0000000 0000000 00000000602 12375155472 0023531 0 ustar 00root root 0000000 0000000 FILE=conv-common-gw
all:
$(MAKE) -C fig
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
bibtex $(FILE).aux
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
evince $(FILE).pdf &
clean:
$(MAKE) -C fig clean
rm -rf *.aux *.dvi *.log $(FILE).pdf *.lof *.lot *.out *.toc *.bbl *.blg *.gz
conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/doc/README.txt 0000664 0000000 0000000 00000000205 12375155472 0023566 0 ustar 00root root 0000000 0000000 Type 'make' to create your .pdf documentation file.
You need Inkscape to make the documentation files:
sudo apt-get install inkscape conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/doc/cern-title.tex 0000664 0000000 0000000 00000001275 12375155472 0024670 0 ustar 00root root 0000000 0000000 \begin{titlepage}
\vspace*{3cm}
%---------------------------------------------------------------
% name
%---------------------------------------------------------------
\noindent{\LARGE \textbf{Converter board common gateware}}
\noindent \rule{\textwidth}{.1cm}
\hfill August 12, 2014
\vspace*{3cm}
\begin{figure}[h]
\includegraphics[height=3cm]{fig/cern-logo}
\hfill
\includegraphics[height=3cm]{fig/ohwr-logo}
\end{figure}
\vfill
%---------------------------------------------------------------
% name
%---------------------------------------------------------------
\noindent {\Large \textbf{Theodor-Adrian Stana (CERN/BE-CO-HT)}}
\noindent \rule{\textwidth}{.05cm}
\end{titlepage}
conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/doc/conv-common-gw.bib 0000664 0000000 0000000 00000004125 12375155472 0025421 0 ustar 00root root 0000000 0000000 @misc{coding-guidelines,
author = "Patrick Loschmidt and Nata{\v s}a Simani\'c and C\'esar Prados and Pablo Alvarez and Javier Serrano",
title = {{Guidelines for VHDL Coding}},
month = 04,
year = 2011,
note = {\url{http://www.ohwr.org/documents/24}}
}
@misc{level-conversion,
title = {{Level Conversion Circuits}},
note = {\url{http://www.ohwr.org/projects/level-conversion/wiki}}
}
@misc{conv-common-gw-git,
title = {{Repository for converter board common gateware}},
note = {\url{http://www.ohwr.org/projects/conv-common-gw/repository}}
}
@misc{board-id,
title = {{Board IDs for level conversion circuits}},
note = {\url{http://www.ohwr.org/projects/conv-common-gw/wiki/Board-id}}
}
@misc{conv-ttl-blo-ohwr,
title = {{Conv TTL Blocking Project Page on OHWR}},
howpublished = {\url{http://www.ohwr.org/projects/conv-ttl-blo}}
}
@misc{conv-ttl-rs485-ohwr,
title = {{Conv TTL Blocking Project Page on OHWR}},
howpublished = {\url{http://www.ohwr.org/projects/conv-ttl-rs485}}
}
@misc{sdb,
title = {{SDB specification v1.1}},
howpublished = {\url{http://www.ohwr.org/documents/256}}
}
@misc{gencores-ohwr,
title = {{Platform-independent Core Collection webage on Open Hardware Repository}},
howpublished = {\url{http://www.ohwr.org/projects/general-cores/wiki}}
}
@misc{rtm-det,
title = {{Rear Transition Module detection}},
howpublished = {\url{http://www.ohwr.org/projects/conv-ttl-blo/wiki/RTM_board_detection}}
}
@misc{blocking,
author = "C. Gil Soriano",
title = {{Standard Blocking Output Signal Definition for CTDAH board}},
month = sep,
year = 2011,
note = {\url{http://www.ohwr.org/documents/109}}
}
@misc{ug380,
title = {{UG380 - Spartan-6 Configuration Guide}},
author = {Xilinx},
month = jan,
year = {2013},
note = {v2.5},
howpublished = {\url{http://www.xilinx.com/support/documentation/user_guides/ug380.pdf}}
}
@misc{onewire-core,
author = {Iztok Jeras},
title = {{sockit\_owm, 1-wire (onewire) master}},
year = 2011,
note = {\url{http://opencores.org/websvn,filedetails?repname=sockit_owm&path=%2Fsockit_owm%2Ftrunk%2Fdoc%2Fsockit_owr.pdf}}
}
conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/doc/conv-common-gw.tex 0000664 0000000 0000000 00000066376 12375155472 0025505 0 ustar 00root root 0000000 0000000 %==============================================================================
% Document header
%==============================================================================
\documentclass[a4paper,11pt]{article}
% Color package
\usepackage[usenames,dvipsnames,table]{xcolor}
% Hyperrefs
\usepackage[
colorlinks = true,
linkcolor = black,
citecolor = black,
urlcolor = blue,
]{hyperref}
% Longtable
\usepackage{longtable}
% Graphics, multirow
\usepackage{graphicx}
\usepackage{multirow}
% Appendix package
\usepackage[toc,page]{appendix}
\usepackage{fancyhdr}
\setlength{\headheight}{15.2pt}
\pagestyle{fancy}
\fancyhead[L]{\nouppercase{\leftmark}}
\fancyhead[R]{}
\renewcommand{\footrulewidth}{0.4pt}
% Row number command
\newcounter{rownr}
\newcommand{\rownumber}{\stepcounter{rownr}\arabic{rownr}}
%==============================================================================
% Start of document
%==============================================================================
\begin{document}
%------------------------------------------------------------------------------
% Title
%------------------------------------------------------------------------------
\include{cern-title}
%------------------------------------------------------------------------------
% Revision history
%------------------------------------------------------------------------------
\pagebreak
\addcontentsline{toc}{section}{Revision history}
\section*{Revision history}
\centerline
{
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l c p{.6\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Date}} & \multicolumn{1}{c}{\textbf{Version}} & \multicolumn{1}{c}{\textbf{Change}} \\
\hline
05-08-2014 & 0.1 & First draft \\
12-08-2014 & 1.0 & First release \\
\hline
\end{tabular}
}
%------------------------------------------------------------------------------
% List of figs, tables
%------------------------------------------------------------------------------
\pagebreak
\pdfbookmark[1]{\contentsname}{toc}
\tableofcontents
\listoffigures
\listoftables
%------------------------------------------------------------------------------
% List of abbreviations
%------------------------------------------------------------------------------
\pagebreak
\section*{List of Abbreviations}
\begin{tabular}{l l}
CR & Control Register \\
FPGA & Field-Programmable Gate Array \\
LSR & Line Status Register \\
MSWR & Multicast Switch Register \\
SR & Status Register \\
\end{tabular}
\addcontentsline{toc}{section}{List of abbreviations}
%==============================================================================
% SEC: Intro
%==============================================================================
\pagebreak
\section{Introduction}
\label{sec:intro}
This document presents the common gateware for converter board projects~\cite{level-conversion}.
This gateware, mainly written in VHDL, is a grouping of modules common to all converter board projects.
A synthesized version thereof is intended to be downloaded to the FPGA on the converter board.
No specific FPGA is assumed for the converter boards, therefore the VHDL code is as generic as possible.
However, some details about the way that the boards are designed in the Hardware \& Timing section at CERN
are assumed, and these details are described throughout the document.
The document will start with a summary of the VHDL entity's ports, continue with presenting
a top-level diagram of the gateware, followed by a high-level description of each module in the gateware.
More involved details can be obtained by consulting the code itself, which can be freely obtained (including
the \textit{general-cores}) submodule from the \textit{git} repository~\cite{conv-common-gw-git} using the
following commands:
\begin{small}
\begin{verbatim}
git clone git://ohwr.org/level-conversion/conv-common-gw.git
git submodule init
git submodule update
\end{verbatim}
\end{small}
%==============================================================================
% SEC: Instantiation
%==============================================================================
\pagebreak
\section{Instantiation}
\label{sec:instantiation}
To use the common gateware, the designer should instantiate the module \textit{conv\_common\_gw},
which is part of the repository and contains all sub-modules required to implement
the pulse repetition functionality.
A corresponding VHDL component declaration can be found in the associated package file
(\textit{conv\_common\_gw\_pkg.vhd}), which needs to be imported into the file of the
instantiating module.
Port names follow the OHWR coding style guide~\cite{coding-guidelines}. Except for few cases,
the module uses active-high ports, any adaptations to active-low logic must be made in external logic.
Since there are a lot of ports in the component, listing them all here would be a waste of space.
The reader is referred to the package file or the source file directly, where each port declaration
is commented. Projects where this gateware is already used (e.g., CONV-TTL-RS485~\cite{conv-ttl-rs485-ohwr}) can also be a
good source of reference.
The module's generics are listed here for quick reference (Table~\ref{tbl:generics}).
\begin{table}[h]
\caption{\label{tbl:generics} Generics of \textit{conv\_common\_gw}}
\rowcolors{2}{white}{gray!25}
\centerline{
\begin{tabular}{p{.3\textwidth} p{.7\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Name}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
g\_nr\_chans & Number of pulse repetition channels \newline
Max. 6 channels allowed \\
g\_board\_id & Board ID, per the converter board ID page~\cite{board-id} \newline
Connects to BID register \\
g\_gwvers & Current gateware version \newline
Connects to GWVERS field in SR \\
g\_pgen\_fixed\_width & Pulse generator with fixed width at output \newline
\textit{true} -- fixed-width output pulse and pulse rejection after pulse is generated \newline
\textit{false} -- pulse generator is simple pass-through \\
g\_pgen\_pwidth & No effect if \textit{g\_pgen\_fixed\_width} is \textit{false} \newline
Pulse width at generator output \newline
Value in number of \textit{clk\_20\_i} cycles \newline
Default: 24 (1.2~${\mu}s$~\cite{blocking}) \newline
Constrained between 20 and 40 \textit{clk\_20\_i} cycles \newline
(1--2~${\mu}s$~\cite{blocking}) \\
g\_pgen\_duty\_cycle\_div & No effect if \textit{g\_pgen\_fixed\_width} is \textit{false} \newline
Divider ratio of pulse rejection mechanism \newline
Output max. freq. 1/g\_pgen\_duty\_cycle\_div \\
g\_pgen\_gf\_len & Pulse generation mechanism glitch filter length in number of \textit{clk\_20\_i} cycles \\
g\_bicolor\_led\_columns & Number of columns for bicolor LED controller \\
g\_bicolor\_led\_lines & Number of lines for bicolor LED controller \\
\hline
\end{tabular}
}
\end{table}
%==============================================================================
% SEC: Top-level diagram
%==============================================================================
\pagebreak
\section{Overview}
\label{sec:overview}
The common gateware comprises various modules, as shown in Figure~\ref{fig:block-diagram}.
The channel logic, presented in Section~\ref{sec:chan-logic}, is multiplied \textit{g\_nr\_chans} times.
Its status and select functionality can be controlled via the controller board
registers (Section~\ref{subsec:conv-regs}), which are part of a Wishbone memory-mapped
peripheral. This peripheral, along with the rest of the memory-mapped peripherals on converter boards,
is accessible through an I$^2$C interface, and an I$^2$C to Wishbone bridge performs
the conversion between the two interfaces.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/block-diagram}}
\caption{\label{fig:block-diagram} Block diagram of common gateware}
\end{figure}
\textcolor{red}{\textbf{SWITCHES CONVENTION}}
%==============================================================================
% SEC: Clocking
%==============================================================================
\pagebreak
\section{Clocks}
\label{sec:clocks}
There are two clock signals input to the FPGA (Figure~\ref{fig:clocks}).
The first is a 20~MHz signal from a VCXO. The second clock signal with a frequency
of 125~MHz is generated on-board via a Texas Instruments PLL IC from a 25~MHz VCXO.
Two DACs are provided on-board for controlling the two VCXOs. The DACs can be
controlled via SPI, and if White Rabbit is available, the White Rabbit PTP Core (WRPC)
can control these DACs to discipline these clocks.
Table~\ref{tbl:clocks} lists the clock domains used in the gateware.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/clocks}}
\caption{FPGA clock inputs}
\label{fig:clocks}
\end{figure}
\begin{table}[h]
\caption{\label{tbl:clocks} Clock domains}
\rowcolors{2}{white}{gray!25}
\centerline
{
\begin{tabular}{c c p{.6\textwidth}}
\hline
\textbf{Clock domain} & \textbf{Frequency} & \multicolumn{1}{c}{\textbf{Comments}} \\
\hline
\textit{clk\_20\_i} & 20~MHz & Clock input to most of the sequential logic \\
% \textit{clk\_125} & 125~MHz & Time-tagging logic and WR reference clock \\
\hline
\end{tabular}
}
\end{table}
%==============================================================================
% SEC: Reset
%==============================================================================
\pagebreak
\section{Reset}
\label{sec:reset}
An internal reset generator (\textit{conv\_reset\_gen}) is used to supply a reset pulse to the sequential
modules of the \textit{conv\_common\_gw}, so that they start up in a known state.
This reset pulse occurs either when the FPGA finishes configuration and goes into user mode, or when
an external reset is received via the control register (CR) in the converter board registers component.
To be able to issue an external reset, the reset bit in the CR must be unlocked via the reset
unlock bit.
The \textit{conv\_reset\_gen} component is clocked from \textit{clk\_20\_i}, so the reset
it generates is in the 20~MHz clock domain. This is also the reset that is present at the
\textit{rst\_n\_o} pin.
%A reset synchronized to the 125~MHz clock domain is generated
%inside \textit{conv\_common\_gw}, but this is not provided at the output.
Note that the VHDL of this module is Xilinx and XST-specific and porting to a different
FPGA architecture or synthesis tool is not guaranteed to provide the same results.
The \textit{conv\_reset\_gen} module has an initial value set for the counter signal after
power-up, which is guaranteed by XST to be set after the FPGA's GSR signal is de-asserted.
By default, the reset time is set to 100~ms.
%==============================================================================
% SEC: Channel logic
%==============================================================================
\pagebreak
\section{Channel logic}
\label{sec:chan-logic}
The channel logic is presented in Figure~\ref{fig:chan-logic}. The central part
thereof is a pulse generator which can be configured for pass-through mode, or
fixed-width pulse generation with subsequent pulse rejection after a pulse has
been generated. The generator is triggered by the pulse input, which can be fed
directly to the generator's input, or optionally glitch filtered, by a switch
on the converter board. The output of this pulse generator triggers lighting a pulse LED,
apart from driving the pulse output of the module.
\begin{figure}[b]
\centerline{\includegraphics[width=\textwidth]{fig/chan-logic}}
\caption{\label{fig:chan-logic} Channel logic diagram}
\end{figure}
%------------------------------------------------------------------------------
\subsection{Output enable}
\label{subsec:oen}
%------------------------------------------------------------------------------
Converter board outputs have to be enabled prior to being used. Within the
\textit{conv\_common\_gw}, there are four output enables. Apart from the global
channel output enable, there are dedicated output enables for potential front
and rear panel connections (see the converter board's specific user guide for information
on front and rear panels).
To make sure that pulses are output only when the FPGA can handle them, the global
output enable is set only after the reset period is finished. The rest of the
output enables are set one clock cycle later. This in combination with the
rest of the circuitry outside the FPGA makes sure no glitches or erroneous pulses
are output during the internal reset period.
An example connection of the output enables on the CONV-TTL-RS485~\cite{conv-ttl-rs485-ohwr} is shown in
Figure~\ref{fig:outp-enable}.
\begin{figure}
\centerline{\includegraphics[width=\textwidth]{fig/outp-enable}}
\caption{\label{fig:outp-enable} Output enable example}
\end{figure}
%------------------------------------------------------------------------------
\subsection{Glitch filter}
\label{subsec:glitch-filt}
%------------------------------------------------------------------------------
The glitch filter input (\textit{gf\_en\_n\_i}) is intended to be enabled via one
of the general-purpose switches on the converter board when the environment where
the board is placed is hazardouse and can potentially create harmful glitches on the
line. It is active-low, therefore a '0' on the pin enables the glitch filter.
The length of the glitch filter can be selected at top-level via the generic
\textit{g\_pgen\_glitch\_filt\_len}, which is in measures of \textit{clk\_20\_i} cycles.
For information on the module's implementation, consult its documentation in the
\textit{ip\_cores/general-cores/doc/} folder.
%------------------------------------------------------------------------------
\subsection{Pulse generator}
\label{subsec:pulse-gen}
%------------------------------------------------------------------------------
Figure~\ref{fig:pulse-gen} shows the implementation of the pulse generator (\textit{conv\_pulse\_gen})
block. When \textit{g\_pgen\_fixed\_width} is \textit{false},
the pulse generator is a simple pass-through. This is usable in converter boards
such as the CONV-TTL-RS485~\cite{conv-ttl-rs485-ohwr}, where the RS-485 outputs are not sensitive to the
duty cycle of the outputs pulses, and which can also be used to distribute
timing information.
When an output stage is sensitive to the pulse duty cycle, such as in the TTL to
blocking converter (CONV-TTL-BLO~\cite{conv-ttl-blo-ohwr}), the \textit{g\_pgen\_fixed\_width}
generic can be set to \textit{true} and this will synthesize a pulse generator
which outputs a pulse with a fixed width (\textit{g\_pgen\_pwidth}) and fixed
duty cycle (1/\textit{g\_pgen\_duty\_cycle\_div}).
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/pulse-gen}}
\caption{\label{fig:pulse-gen} Pulse generator block}
\end{figure}
In this latter case, a finite-state machine (FSM) handles pulse generation and rejection.
Its general operation is shown in
The operation of the pulse generator depends on whether the glitch filter is enabled.
If it is, then the pulse is assumed to be synchronized externally to the \textit{conv\_pulse\_gen}
block and it trigger input triggers the FSM directly. Alternatively, if the glitch filter
is disabled, the trigger input starts the pulse (to avoid glitches on the leading edge)
and then the pulse is synchronized and the FSM triggered to generate the fixed-width pulse.
After the pulse width has been reached, the FSM resets the input flip-flop and goes into the
rejection state.
\begin{figure}
\centerline{\includegraphics[width=\textwidth]{fig/pulse-gen-operation}}
\caption{\label{fig:pulse-gen-operation} Pulse generator operation with \textit{g\_pgen\_fixed\_width = true}}
\end{figure}
%------------------------------------------------------------------------------
\subsection{Pulse LED control}
\label{subsec:pulse-led}
%------------------------------------------------------------------------------
A rising edge on the \textit{pulse\_o} signal from the \textit{conv\_pulse\_gen}
block generates a 26-ms active-high pulse signal on the \textit{led\_pulse\_o} port of
\textit{conv\_common\_gw}. This port should be connected to the channel's pulse LED output.
%==============================================================================
% SEC: Memory-mapped peripherals
%==============================================================================
\pagebreak
\section{Memory-mapped peripherals}
\label{sec:memmapped-periphs}
Various memory-mapped peripherals are implemented within \textit{conv\_common\_gw},
as seen below. They are interfaced to a Wishbone interconnect, which is SDB-enabled~\cite{sdb},
granted to the \textit{xwb\_sdb\_crossbar} module used to connect the slaves to the
master.
%==============================================================================
\subsection{I$^2$C to Wishbone bridge}
\label{subsec:i2c-bridge}
%==============================================================================
The Wishbone master in the interconnect is an I$^2$C to Wishbone bridge (\textit{wb\_i2c\_bridge} from
the \textit{general-cores} library~\cite{gencores-ohwr}), which implements the protocol
defined together with ELMA for communication via the serial lines on the VME P1 connector.
Details about this protocol, as well as implementation details for \textit{wb\_i2c\_bridge} can be
found in the module's documentation under the \textit{general-cores/doc/} folder.
Upon instantiating the \textit{wb\_i2c\_bridge} inside \textit{conv\_common\_gw}, the
module's watchdog timeout generic (\textit{g\_fsm\_wdt}) is set such that the watchdog
times out in 24~ms. This value is explained in comments inside the code, as well as
in the appendix to the \textit{wb\_i2c\_bridge} module's documentation.
When an I$^2$C transfer takes place according to the defined protocol, the \textit{led\_i2c\_o}
output strobes four times. This output should be connected to a bicolor LED of choice
for signaling communication.
%==============================================================================
\subsection{Converter board registers}
\label{subsec:conv-regs}
%==============================================================================
The \textit{conv\_regs} module contains various Wishbone-addressable registers that contain status information,
as well as select control functionality. It is the module which constrains \textit{conv\_common\_gw}
to a maximum of six pulse repetition channels, due to need of compatibility with previously-released
implementations of the \textit{conv\_regs} memory map.
Some of the bits in the converter board registers are set from inside the \textit{conv\_common\_gw}
module, but some are status bits that should be connected to external logic. Most of the bits implemented
as part of \textit{conv\_regs} are intended to be active-high logic, so adaptations for this should be made
in logic external to the \textit{conv\_common\_gw} when an external connection is needed.
The inputs that connect to bits in the status register are shown in Table~\ref{tbl:conv-regs-ext-inputs}.
Should some of these inputs not be used, such as for example the failsafe lines in the case of CONV-TTL-BLO~\cite{conv-ttl-blo-ohwr},
the corresponding lines should be connected to all-zeroes.
The \textit{g\_board\_id} and \textit{g\_gwvers} generics connect to registers in
\textit{conv\_regs} as shown in Figure~\ref{fig:bidr-gwvers}.
\begin{table}[h]
\caption{\label{tbl:conv-regs-ext-inputs} Active-high inputs to converter board registers from external logic}
\rowcolors{2}{white}{gray!25}
\centerline {
\begin{tabular}{l l p{.45\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Input port}} & \multicolumn{1}{c}{\textbf{Register}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
sw\_gp\_i & SR.SWITCHES & General-purpose switch status \\
rtmm\_i & SR.RTM[2:0] & RTM Motherboard detection lines \\
rtmp\_i & SR.RTM[5:3] & RTM Piggyback detection lines \\
line\_front\_i & LSR.FRONT & State of front-panel channel lines at FPGA input \\
line\_inv\_i & LSR.FRONTINV & State of front-panel general-purpose inverter channels at FPGA input \\
line\_rear\_i & LSR.REAR & State of rear-panel channel lines at FPGA input \\
line\_rear\_fs\_i & LSR.REARFS & State of fail-safe rear-panel inputs (whether a cable is plugged in or not) \\
sw\_multicast\_i & MSWR & Multicast switches, connected to Multicast Switch Register \\
\hline
\end{tabular}
}
\end{table}
\begin{figure}[h]
\centerline{\includegraphics[width=.7\textwidth]{fig/bidr-gwvers}}
\caption{\label{fig:bidr-gwvers} BIDR and SR.GWVERS connections}
\end{figure}
Some bits or fields inside \textit{conv\_regs} are generated based on the settings of
\textit{g\_with\_*} generics. Should such a generic set to \textit{false}, the corresponding
bits or fields in \textit{conv\_regs} are set to a 'safe' value of '0'. Consult the code
for details on how this is done and which are the fields concerned.
Note that the logic allows less than 6 pulse repetition channels, but not more.
If \textit{g\_nr\_chans < 6}, then the rest of the bits are automatically set to '0',
as in the case a \textit{g\_with\_*} generic is \textit{false}. If \textit{g\_nr\_chans > 6}
a synthesis error will be thrown.
%==============================================================================
\subsection{MultiBoot}
\label{subsec:multiboot}
%==============================================================================
The \textit{xwb\_xil\_multiboot} module from the \textit{general-cores} library~\cite{gencores-ohwr}
is used to provide MultiBoot functionality via I$^2$C. To find out more about the
module and how to use it, consult its documentation under the \textit{general-cores/doc/} folder.
%==============================================================================
% Appendices
%==============================================================================
\pagebreak
\begin{appendices}
%==============================================================================
% APP: Memmap
%==============================================================================
\section{Memory map}
\label{app:memmap}
Table~\ref{tbl:memmap} shows the maximum memory map obtainable with the \textit{conv\_common\_gw}
module. This is obtained when the \textit{g\_nr\_chans} generic is set to the maximum value of
\textit{6}. Should less channels be desired, the higher-numbered registers for the channels
(e.g., CH5PCR and CH6PCR for \textit{g\_nr\_chans = 4}) can be considered as \textit{Reserved}
(read out as 0).
The following sections list the memory map of each peripheral.
\begin{table}[h]
\caption{\textit{conv\_common\_gw} memory map}
\label{tbl:memmap}
\centerline
{
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l l l p{.4\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Peripheral}} & \multicolumn{2}{c}{\textbf{Address range}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
Board registers & 0x000 & 0x0ff & Coverter board registers \\
MultiBoot & 0x100 & 0x110 & MultiBoot module \\
One-wire master & 0x200 & 0x2ff & One-wire master for DS18B20 thermometer module \\
SDB descriptor & 0xf00 & 0xfff & SDB descriptor (see~\cite{sdb}) \\
\hline
\end{tabular}
}
\end{table}
%%------------------------------------------------------------------------------
%% SUBSEC: conv-regs
%%------------------------------------------------------------------------------
\include{conv-regs}
%\include{tmp}
%------------------------------------------------------------------------------
% SUBSEC: MultiBoot
%------------------------------------------------------------------------------
\include{multiboot-regs}
%------------------------------------------------------------------------------
% SUBSEC: Thermo
%------------------------------------------------------------------------------
\subsection{Thermometer module}
\label{app:memmap-thermo}
\indent Base address: 0x080
\vspace*{11pt}
\centerline
{
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l l l p{.5\textwidth}}
\hline
\textbf{Offset} & \textbf{Default} & \textbf{Name} & \textbf{Description} \\
\hline
0x00 & 0x00000000 & OWCSR & One-Wire Control and Status Register \\
0x04 & 0x00000004 & OWCDR & One-Wire Clock Divider Registers \\
\hline
\end{tabular}
}
\vspace*{11pt}
For details on the bits of the thermometer module access registers, see the
OneWire Master module's documentation~\cite{onewire-core}.
Note that the OWCDR should be set accordingly for proper functioning of the
one-wire timings. The value for the current version of the gateware is
\verb-OWCDR = 0x00130063-.
%==============================================================================
% APP: Changing the code for more than six pulse repetition channels
%==============================================================================
\pagebreak
\section{Gateware for pulse converters with more than six conversion channels}
\label{app:more-than-six-chans}
This appendix offers guidelines on how to use or change \textit{conv\_common\_gw}
should a pulse repeater with more than six channels be eventually implemented.
Note that none of the guidelines here have been tested, since no board exists
with more than six channels at the time of writing of this document.
The first option is obviously instantiating more than one \textit{conv\_common\_gw}
component, each with its appropriate \textit{g\_nr\_chans} and making the appropriate connections
to the FPGA outputs. Note that each \textit{conv\_common\_gw} will
come with its own \textit{conv\_regs}, MultiBoot and one-wire master peripherals.
In this case, since it is expected that there is only one flash and thermometer
chip on-board, connect only the outputs of one of the \textit{conv\_common\_gw} modules
to the top-level module outputs, as shown in Figure~\ref{fig:more-than-six-chans}.
The synthesis tool should be smart enough to optimize away the unused modules.
\begin{figure}[h]
\centerline{\includegraphics[width=1.1\textwidth]{fig/more-than-six-chans}}
\caption{\label{fig:more-than-six-chans} Connect the outputs of only one \textit{conv\_common\_gw} module at the top-level}
\end{figure}
\pagebreak
The second, non-encouraged option, is to change the \textit{conv\_common\_gw} code.
Note that this will:
\begin{enumerate}
\item Involve changing the memory map and \textit{conv\_regs} component,
which will
\item Make the \textit{conv\_common\_gw} module incompatible with the
version described in this document
\end{enumerate}
If this option is chosen, the reader should start by changing the
\textit{c\_max\_nr\_chans} generic in the package file (\textit{conv\_common\_gw\_pkg.vhd}).
Then, a new memory map should be chosen and the \textit{conv\_regs} component
adapted as appropriate.
%==============================================================================
\end{appendices}
%==============================================================================
%==============================================================================
% Bibliography
%==============================================================================
\pagebreak
\bibliographystyle{ieeetr}
\bibliography{conv-common-gw}
\addcontentsline{toc}{section}{References}
\end{document}
conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/doc/conv-regs.tex 0000664 0000000 0000000 00000146416 12375155472 0024534 0 ustar 00root root 0000000 0000000 \subsection{Converter board registers}
\label{app:conv-regs}
Base address: 0x000
{
\rowcolors{2}{white}{gray!25}
\begin{longtable}{l l l p{.5\textwidth}}
\hline
\textbf{Offset} & \textbf{Reset} & \textbf{Name}
& \textbf{Description} \\
\hline
\endfirsthead
\hline
\textbf{Offset} & \textbf{Reset} & \textbf{Name}
& \textbf{Description} \\
\hline
\endhead
\hline
\endfoot
0x0 & \textit{g\_board\_id} & BIDR & Board ID Register\\
0x4 & (1) & SR & Status Register\\
0x8 & 0x00000000 & CR & Control Register\\
0xc & 0x00000000 & CH1PCR & Channel 1 Pulse Counter Register\\
0x10 & 0x00000000 & CH2PCR & Channel 2 Pulse Counter Register\\
0x14 & 0x00000000 & CH3PCR & Channel 3 Pulse Counter Register\\
0x18 & 0x00000000 & CH4PCR & Channel 4 Pulse Counter Register\\
0x1c & 0x00000000 & CH5PCR & Channel 5 Pulse Counter Register\\
0x20 & 0x00000000 & CH6PCR & Channel 6 Pulse Counter Register\\
0x24 & 0x00000000 & TVLR & Time Value Low Register\\
0x28 & 0x00000000 & TVHR & Time Value High Register\\
0x2c & 0x00000000 & TBMR & Tag Buffer Meta Register\\
0x30 & 0x00000000 & TBCYR & Tag Buffer Cycles Register\\
0x34 & 0x00000000 & TBTLR & Tag Buffer TAI Low Register\\
0x38 & 0x00000000 & TBTHR & Tag Buffer TAI High Register\\
0x3c & 0x00020000 & TBCSR & Tag Buffer Control and Status Register\\
0x40 & 0x00000000 & CH1LTSCYR & Channel 1 Latest Timestamp Cycles Register\\
0x44 & 0x00000000 & CH1LTSTLR & Channel 1 Latest Timestamp TAI Low Register\\
0x48 & 0x00000000 & CH1LTSTHR & Channel 1 Latest Timestamp TAI High Register\\
0x4c & 0x00000000 & CH2LTSCYR & Channel 2 Latest Timestamp Cycles Register\\
0x50 & 0x00000000 & CH2LTSTLR & Channel 2 Latest Timestamp TAI Low Register\\
0x54 & 0x00000000 & CH2LTSTHR & Channel 2 Latest Timestamp TAI High Register\\
0x58 & 0x00000000 & CH3LTSCYR & Channel 3 Latest Timestamp Cycles Register\\
0x5c & 0x00000000 & CH3LTSTLR & Channel 3 Latest Timestamp TAI Low Register\\
0x60 & 0x00000000 & CH3LTSTHR & Channel 3 Latest Timestamp TAI High Register\\
0x64 & 0x00000000 & CH4LTSCYR & Channel 4 Latest Timestamp Cycles Register\\
0x68 & 0x00000000 & CH4LTSTLR & Channel 4 Latest Timestamp TAI Low Register\\
0x6c & 0x00000000 & CH4LTSTHR & Channel 4 Latest Timestamp TAI High Register\\
0x70 & 0x00000000 & CH5LTSCYR & Channel 5 Latest Timestamp Cycles Register\\
0x74 & 0x00000000 & CH5LTSTLR & Channel 5 Latest Timestamp TAI Low Register\\
0x78 & 0x00000000 & CH5LTSTHR & Channel 5 Latest Timestamp TAI High Register\\
0x7c & 0x00000000 & CH6LTSCYR & Channel 6 Latest Timestamp Cycles Register\\
0x80 & 0x00000000 & CH6LTSTLR & Channel 6 Latest Timestamp TAI Low Register\\
0x84 & 0x00000000 & CH6LTSTHR & Channel 6 Latest Timestamp TAI High Register\\
0x88 & (2) & LSR & Line Status Register\\
0x8c & 0x00000000 & MSWR & Multicast Switch Register\\
\end{longtable}
}
\noindent Note (1): The reset value of the SR cannot be specified, since it is based on the
gateware version, the state of the on-board switches and whether an RTM is plugged in or not.
\noindent Note (2): The reset value of the LSR cannot be specified, since it depends on whether a cable
is plugged into the channel or not.
\vspace{11pt}
\subsubsection{BIDR -- Board ID Register}
\label{app:conv-regs-bidr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BIDR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BIDR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BIDR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BIDR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
BIDR
} [\emph{read-only}]: ID register bits
\\
Reset value: \textit{g\_board\_id}
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{SR -- Status Register}
\label{app:conv-regs-sr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & \multicolumn{6}{|c|}{\cellcolor{gray!25}PMISSE[5:0]} & \multicolumn{1}{|c|}{\cellcolor{gray!25}I2C\_ERR}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c|}{\cellcolor{gray!25}WRPRES} & \multicolumn{1}{|c|}{\cellcolor{gray!25}I2C\_WDTO} & \multicolumn{6}{|c|}{\cellcolor{gray!25}RTM[5:0]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}SWITCHES[7:0]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}GWVERS[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
GWVERS
} [\emph{read-only}]: Gateware version
\\
Leftmost nibble hex value is major release decimal value \\ Rightmost nibble hex value is minor release decimal value \\ e.g. \\ 0x11 -- v1.1 \\ 0x2e -- v2.14
\end{small}
\item \begin{small}
{\bf
SWITCHES
} [\emph{read-only}]: Status of on-board general-purpose switches
\\
1 -- switch is ON \\ 0 -- switch is OFF
\end{small}
\item \begin{small}
{\bf
RTM
} [\emph{read-only}]: RTM detection lines~\cite{rtm-det}
\\
1 -- line active \\ 0 -- line inactive
\end{small}
\item \begin{small}
{\bf
I2C\_WDTO
} [\emph{read/write}]: I2C communication watchdog timeout error
\\
1 -- timeout occured \\ 0 -- no timeout \\ This bit can be cleared by writing a '1' to it
\end{small}
\item \begin{small}
{\bf
WRPRES
} [\emph{read-only}]: White Rabbit present
\\
1 -- White Rabbit present \\ 0 -- White Rabbit not present
\end{small}
\item \begin{small}
{\bf
I2C\_ERR
} [\emph{read/write}]: I2C communication error
\\
1 -- attempted to address non-existing address \\ 0 -- idle \\ This bit can be cleared by writing a '1' to it
\end{small}
\item \begin{small}
{\bf
PMISSE
} [\emph{read/write}]: Pulse missed error
\\
1 -- pulse arrived during pulse rejection phase \\ 0 -- idle \\ Bit 0 -- channel 1 \\ Bit 1 -- channel 2 \\ etc. \\ Each bit can be cleared by writing a '1' to it
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CR -- Control Register}
\label{app:conv-regs-cr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & \multicolumn{2}{|c|}{\cellcolor{gray!25}MPT[7:6]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{6}{|c|}{\cellcolor{gray!25}MPT[5:0]} & \multicolumn{1}{|c|}{\cellcolor{gray!25}RST} & \multicolumn{1}{|c|}{\cellcolor{gray!25}RST\_UNLOCK}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
RST\_UNLOCK
} [\emph{read/write}]: Reset unlock bit
\\
1 -- Reset bit unlocked \\ 0 -- Reset bit locked
\end{small}
\item \begin{small}
{\bf
RST
} [\emph{read/write}]: Reset bit
\\
1 -- initiate logic reset \\ 0 -- no reset
\end{small}
\item \begin{small}
{\bf
MPT
} [\emph{write-only}]: Manual Pulse Trigger
\\
Write the following sequence to trigger a pulse: \\ 0xde -- Byte 1 of magic sequence \\ 0xad -- Byte 2 of magic sequence \\ 0xbe -- Byte 3 of magic sequence \\ 0xef -- Byte 4 of magic sequence \\ Number in range 1..6 -- trigger a pulse
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH1PCR -- Channel 1 Pulse Counter Register}
\label{app:conv-regs-ch1pcr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1PCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1PCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1PCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1PCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH1PCR
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH2PCR -- Channel 2 Pulse Counter Register}
\label{app:conv-regs-ch2pcr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2PCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2PCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2PCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2PCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH2PCR
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH3PCR -- Channel 3 Pulse Counter Register}
\label{app:conv-regs-ch3pcr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3PCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3PCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3PCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3PCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH3PCR
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH4PCR -- Channel 4 Pulse Counter Register}
\label{app:conv-regs-ch4pcr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4PCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4PCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4PCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4PCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH4PCR
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH5PCR -- Channel 5 Pulse Counter Register}
\label{app:conv-regs-ch5pcr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5PCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5PCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5PCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5PCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH5PCR
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH6PCR -- Channel 6 Pulse Counter Register}
\label{app:conv-regs-ch6pcr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6PCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6PCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6PCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6PCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH6PCR
} [\emph{read/write}]: Pulse counter value
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{TVLR -- Time Value Low Register}
\label{app:conv-regs-tvlr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TVLR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TVLR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TVLR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TVLR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TVLR
} [\emph{read/write}]: TAI seconds counter bits 31..0
\\
Writing this field resets the internal cycles counter.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{TVHR -- Time Value High Register}
\label{app:conv-regs-tvhr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TVHR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TVHR
} [\emph{read/write}]: TAI seconds counter bits 39..32
\\
Writing this field resets the internal cycles counter.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{TBMR -- Tag Buffer Meta Register}
\label{app:conv-regs-tbmr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c|}{\cellcolor{gray!25}WRTAG} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{1}{|c}{-} & - & \multicolumn{6}{|c|}{\cellcolor{gray!25}CHAN[5:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CHAN
} [\emph{read-only}]: Channel mask
\\
Mask for the channel(s) that triggered time-tag storage: \\ bit 0 -- channel 1 \\ bit 1 -- channel 2 \\ ... \\ bit 5 -- channel 6
\end{small}
\item \begin{small}
{\bf
WRTAG
} [\emph{read-only}]: White Rabbit present
\\
1 - Current time tag generated with White Rabbit \\ 0 - Current time tag generated with internal counter
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\item \begin{small}
\textbf{A read from this register advances the buffer read pointer, if the ring buffer is not empty}
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{TBCYR -- Tag Buffer Cycles Register}
\label{app:conv-regs-tbcyr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}TBCYR[27:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TBCYR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TBCYR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TBCYR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TBCYR
} [\emph{read-only}]: Cycles counter
\\
Value of the 8-ns cycles counter when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{TBTLR -- Tag Buffer TAI Low Register}
\label{app:conv-regs-tbtlr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TBTLR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TBTLR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TBTLR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TBTLR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TBTLR
} [\emph{read-only}]: Lower part of TAI seconds counter
\\
Value of the TAI seconds counter bits 31..0 when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\pagebreak
\vspace{11pt}
\subsubsection{TBTHR -- Tag Buffer TAI High Register}
\label{app:conv-regs-tbthr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TBTHR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TBTHR
} [\emph{read-only}]: Upper part of TAI seconds counter
\\
Value of the TAI seconds counter bits 39..32 when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{TBCSR -- Tag Buffer Control and Status Register}
\label{app:conv-regs-tbcsr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}CLR} & \multicolumn{1}{|c|}{\cellcolor{gray!25}EMPTY} & \multicolumn{1}{|c|}{\cellcolor{gray!25}FULL}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{1}{|c}{-} & \multicolumn{7}{|c|}{\cellcolor{gray!25}USEDW[6:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
USEDW
} [\emph{read-only}]: Buffer counter
\\
Number of samples in the ring buffer
\end{small}
\item \begin{small}
{\bf
FULL
} [\emph{read-only}]: Buffer full
\\
1 -- buffer full \\ 0 -- buffer is not full
\end{small}
\item \begin{small}
{\bf
EMPTY
} [\emph{read-only}]: Buffer empty
\\
1 -- buffer empty\\ 0 -- buffer is not empty
\end{small}
\item \begin{small}
{\bf
CLR
} [\emph{read/write}]: Clear tag buffer
\\
1 -- clear\\ 0 -- no effect
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH1LTSCYR -- Channel 1 Latest Timestamp Cycles Register}
\label{app:conv-regs-ch1ltscyr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}CH1LTSCYR[27:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1LTSCYR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1LTSCYR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1LTSCYR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH1LTSCYR
} [\emph{write-only}]: Cycles counter
\\
Value of the 8-ns cycles counter when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH1LTSTLR -- Channel 1 Latest Timestamp TAI Low Register}
\label{app:conv-regs-ch1ltstlr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1LTSTLR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1LTSTLR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1LTSTLR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1LTSTLR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH1LTSTLR
} [\emph{read-only}]: Lower part of TAI seconds counter
\\
Value of the TAI seconds counter bits 31..0 when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\pagebreak
\subsubsection{CH1LTSTHR -- Channel 1 Latest Timestamp TAI High Register}
\label{app:conv-regs-ch1ltsthr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c|}{\cellcolor{gray!25}WRTAG} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TAI
} [\emph{read-only}]: Upper part of TAI seconds counter
\\
Value of the TAI seconds counter bits 39..32 when time tag was taken.
\end{small}
\item \begin{small}
{\bf
WRTAG
} [\emph{read-only}]: White Rabbit present
\\
1 - Current time tag generated with White Rabbit \\ 0 - Current time tag generated with internal counter
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH2LTSCYR -- Channel 2 Latest Timestamp Cycles Register}
\label{app:conv-regs-ch2ltscyr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}CH2LTSCYR[27:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2LTSCYR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2LTSCYR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2LTSCYR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH2LTSCYR
} [\emph{write-only}]: Cycles counter
\\
Value of the 8-ns cycles counter when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH2LTSTLR -- Channel 2 Latest Timestamp TAI Low Register}
\label{app:conv-regs-ch2ltstlr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2LTSTLR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2LTSTLR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2LTSTLR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2LTSTLR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH2LTSTLR
} [\emph{read-only}]: Lower part of TAI seconds counter
\\
Value of the TAI seconds counter bits 31..0 when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH2LTSTHR -- Channel 2 Latest Timestamp TAI High Register}
\label{app:conv-regs-ch2ltsthr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c|}{\cellcolor{gray!25}WRTAG} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TAI
} [\emph{read-only}]: Upper part of TAI seconds counter
\\
Value of the TAI seconds counter bits 39..32 when time tag was taken.
\end{small}
\item \begin{small}
{\bf
WRTAG
} [\emph{read-only}]: White Rabbit present
\\
1 - Current time tag generated with White Rabbit \\ 0 - Current time tag generated with internal counter
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH3LTSCYR -- Channel 3 Latest Timestamp Cycles Register}
\label{app:conv-regs-ch3ltscyr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}CH3LTSCYR[27:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3LTSCYR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3LTSCYR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3LTSCYR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH3LTSCYR
} [\emph{write-only}]: Cycles counter
\\
Value of the 8-ns cycles counter when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH3LTSTLR -- Channel 3 Latest Timestamp TAI Low Register}
\label{app:conv-regs-ch3ltstlr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3LTSTLR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3LTSTLR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3LTSTLR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3LTSTLR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH3LTSTLR
} [\emph{read-only}]: Lower part of TAI seconds counter
\\
Value of the TAI seconds counter bits 31..0 when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\pagebreak
\subsubsection{CH3LTSTHR -- Channel 3 Latest Timestamp TAI High Register}
\label{app:conv-regs-ch3ltsthr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c|}{\cellcolor{gray!25}WRTAG} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TAI
} [\emph{read-only}]: Upper part of TAI seconds counter
\\
Value of the TAI seconds counter bits 39..32 when time tag was taken.
\end{small}
\item \begin{small}
{\bf
WRTAG
} [\emph{read-only}]: White Rabbit present
\\
1 - Current time tag generated with White Rabbit \\ 0 - Current time tag generated with internal counter
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH4LTSCYR -- Channel 4 Latest Timestamp Cycles Register}
\label{app:conv-regs-ch4ltscyr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}TAI[27:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TAI
} [\emph{write-only}]: Cycles counter
\\
Value of the 8-ns cycles counter when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH4LTSTLR -- Channel 4 Latest Timestamp TAI Low Register}
\label{app:conv-regs-ch4ltstlr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4LTSTLR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4LTSTLR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4LTSTLR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4LTSTLR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH4LTSTLR
} [\emph{read-only}]: Lower part of TAI seconds counter
\\
Value of the TAI seconds counter bits 31..0 when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH4LTSTHR -- Channel 4 Latest Timestamp TAI High Register}
\label{app:conv-regs-ch4ltsthr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c|}{\cellcolor{gray!25}WRTAG} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TAI
} [\emph{read-only}]: Upper part of TAI seconds counter
\\
Value of the TAI seconds counter bits 39..32 when time tag was taken.
\end{small}
\item \begin{small}
{\bf
WRTAG
} [\emph{read-only}]: White Rabbit present
\\
1 - Current time tag generated with White Rabbit \\ 0 - Current time tag generated with internal counter
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH5LTSCYR -- Channel 5 Latest Timestamp Cycles Register}
\label{app:conv-regs-ch5ltscyr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}CH5LTSCYR[27:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5LTSCYR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5LTSCYR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5LTSCYR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH5LTSCYR
} [\emph{write-only}]: Cycles counter
\\
Value of the 8-ns cycles counter when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH5LTSTLR -- Channel 5 Latest Timestamp TAI Low Register}
\label{app:conv-regs-ch5ltstlr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5LTSTLR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5LTSTLR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5LTSTLR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5LTSTLR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH5LTSTLR
} [\emph{read-only}]: Lower part of TAI seconds counter
\\
Value of the TAI seconds counter bits 31..0 when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\pagebreak
\subsubsection{CH5LTSTHR -- Channel 5 Latest Timestamp TAI High Register}
\label{app:conv-regs-ch5ltsthr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c|}{\cellcolor{gray!25}WRTAG} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TAI
} [\emph{read-only}]: Upper part of TAI seconds counter
\\
Value of the TAI seconds counter bits 39..32 when time tag was taken.
\end{small}
\item \begin{small}
{\bf
WRTAG
} [\emph{read-only}]: White Rabbit present
\\
1 - Current time tag generated with White Rabbit \\ 0 - Current time tag generated with internal counter
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH6LTSCYR -- Channel 6 Latest Timestamp Cycles Register}
\label{app:conv-regs-ch6ltscyr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}CH6LTSCYR[27:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6LTSCYR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6LTSCYR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6LTSCYR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH6LTSCYR
} [\emph{write-only}]: Cycles counter
\\
Value of the 8-ns cycles counter when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH6LTSTLR -- Channel 6 Latest Timestamp TAI Low Register}
\label{app:conv-regs-ch6ltstlr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6LTSTLR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6LTSTLR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6LTSTLR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6LTSTLR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH6LTSTLR
} [\emph{read-only}]: Lower part of TAI seconds counter
\\
Value of the TAI seconds counter bits 31..0 when time tag was taken.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{CH6LTSTHR -- Channel 6 Latest Timestamp TAI High Register}
\label{app:conv-regs-ch6ltsthr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c|}{\cellcolor{gray!25}WRTAG} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TAI
} [\emph{read-only}]: Upper part of TAI seconds counter
\\
Value of the TAI seconds counter bits 39..32 when time tag was taken.
\end{small}
\item \begin{small}
{\bf
WRTAG
} [\emph{read-only}]: White Rabbit present
\\
1 - Current time tag generated with White Rabbit \\ 0 - Current time tag generated with internal counter
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{LSR -- Line Status Register}
\label{app:conv-regs-lsr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & \multicolumn{6}{|c|}{\cellcolor{gray!25}REARFS[5:0]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{6}{|c|}{\cellcolor{gray!25}REAR[5:0]} & \multicolumn{2}{|c|}{\cellcolor{gray!25}FRONTINV[3:2]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{2}{|c|}{\cellcolor{gray!25}FRONTINV[1:0]} & \multicolumn{6}{|c|}{\cellcolor{gray!25}FRONT[5:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
FRONT
} [\emph{read-only}]: Front panel channel input state
\\
Line state at board input\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
\end{small}
\item \begin{small}
{\bf
FRONTINV
} [\emph{read-only}]: Front panel INV-TTL input state
\\
Line state at board input\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
\end{small}
\item \begin{small}
{\bf
REAR
} [\emph{read-only}]: Rear panel input state
\\
Line state at board input\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
\end{small}
\item \begin{small}
{\bf
REARFS
} [\emph{read-only}]: Input failsafe state
\\
High if line is in failsafe mode (no cable plugged in)\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\pagebreak
\subsubsection{MSWR -- Multicast Switch Register}
\label{app:conv-regs-mswr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}SWITCHES[3:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
SWITCHES
} [\emph{read-only}]: Multicast address (from switch)
\\
1 -- switch is ON \\ 0 -- switch is OFF
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/doc/fig/ 0000775 0000000 0000000 00000000000 12375155472 0022640 5 ustar 00root root 0000000 0000000 conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/doc/fig/Makefile 0000664 0000000 0000000 00000000172 12375155472 0024300 0 ustar 00root root 0000000 0000000 SRC = $(wildcard *.svg)
OBJS = $(SRC:.svg=.pdf)
all: $(OBJS)
%.pdf : %.svg
inkscape -f $< -A $@
clean :
rm -f *.pdf
conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/doc/fig/bidr-gwvers.svg 0000664 0000000 0000000 00000012461 12375155472 0025620 0 ustar 00root root 0000000 0000000
conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/doc/fig/block-diagram.svg 0000664 0000000 0000000 00000111130 12375155472 0026052 0 ustar 00root root 0000000 0000000
conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/doc/fig/cern-logo.svg 0000664 0000000 0000000 00000012001 12375155472 0025240 0 ustar 00root root 0000000 0000000
conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/doc/fig/chan-logic-next-ver.svg 0000664 0000000 0000000 00000041612 12375155472 0027137 0 ustar 00root root 0000000 0000000
conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/doc/fig/chan-logic.svg 0000664 0000000 0000000 00000026621 12375155472 0025374 0 ustar 00root root 0000000 0000000
conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/doc/fig/clocks.svg 0000664 0000000 0000000 00004523461 12375155472 0024656 0 ustar 00root root 0000000 0000000
conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/doc/fig/more-than-six-chans.svg 0000664 0000000 0000000 00000035021 12375155472 0027147 0 ustar 00root root 0000000 0000000
conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/doc/fig/ohwr-logo.svg 0000664 0000000 0000000 00000145745 12375155472 0025316 0 ustar 00root root 0000000 0000000
conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/doc/fig/outp-enable.svg 0000664 0000000 0000000 00000046375 12375155472 0025613 0 ustar 00root root 0000000 0000000
conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/doc/fig/pulse-gen-operation.svg 0000664 0000000 0000000 00000022540 12375155472 0027261 0 ustar 00root root 0000000 0000000
conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/doc/fig/pulse-gen.svg 0000664 0000000 0000000 00000132047 12375155472 0025267 0 ustar 00root root 0000000 0000000
conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/doc/multiboot-regs.tex 0000664 0000000 0000000 00000022134 12375155472 0025573 0 ustar 00root root 0000000 0000000 \subsection{MultiBoot controller}
\label{app:multiboot-regs}
Base address: 0x100
{
\rowcolors{2}{white}{gray!25}
\begin{longtable}{l l l p{.5\textwidth}}
\hline
\textbf{Offset} & \textbf{Reset} & \textbf{Name}
& \textbf{Description} \\
\hline
\endfirsthead
\hline
\hline
\endhead
\hline
\endfoot
0x0 & 0x00000000 & CR & Control Register\\
0x4 & 0x00000000 & SR & Status Register\\
0x8 & 0x00000000 & GBBAR & Golden Bitstream Base Address Register\\
0xc & 0x00000000 & MBBAR & MultiBoot Bitstream Base Address Register\\
0x10 & 0x10000000 & FAR & Flash Access Register\\
\end{longtable}
}
\vspace{11pt}
\subsubsection{CR -- Control Register}
\label{app:multiboot-regs-cr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}IPROG} & \multicolumn{1}{|c|}{\cellcolor{gray!25}IPROG\_UNLOCK}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{1}{|c}{-} & \multicolumn{1}{|c|}{\cellcolor{gray!25}RDCFGREG} & \multicolumn{6}{|c|}{\cellcolor{gray!25}CFGREGADR[5:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CFGREGADR
} [\emph{read/write}]: Configuration register address
\\
Address of FPGA configuration register to read.
\end{small}
\item \begin{small}
{\bf
RDCFGREG
} [\emph{write-only}]: Read FPGA configuration register
\\
1 -- Start FPGA configuration register sequence. \\ 0 -- No effect.
\end{small}
\item \begin{small}
{\bf
IPROG\_UNLOCK
} [\emph{read/write}]: Unlock bit for the IPROG command
\\
1 -- Unlock IPROG bit. \\ 0 -- No effect.
\end{small}
\item \begin{small}
{\bf
IPROG
} [\emph{read/write}]: Start IPROG sequence
\\
1 -- Start IPROG configuration sequence \\ 0 -- No effect \\ This bit needs to be unlocked by writing the IPROG\_UNLOCK bit first. \\ A write to this bit with IPROG\_UNLOCK cleared has no effect.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{SR -- Status Register}
\label{app:multiboot-regs-sr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}WDTO} & \multicolumn{1}{|c|}{\cellcolor{gray!25}IMGVALID}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CFGREGIMG[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CFGREGIMG[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CFGREGIMG
} [\emph{read-only}]: Configuration register image
\\
Image of the FPGA configuration register at address CFGREGADR (see Configuration Registers section in Xilinx UG380~\cite{ug380}); validated by IMGVALID bit
\end{small}
\item \begin{small}
{\bf
IMGVALID
} [\emph{read-only}]: Configuration register image valid
\\
1 -- CFGREGIMG valid \\ 0 -- CFGREGIMG not valid;
\end{small}
\item \begin{small}
{\bf
WDTO
} [\emph{read/write}]: MultiBoot FSM stalled at one point and was reset by FSM watchdog
\\
1 -- FSM watchdog fired \\ 0 -- FSM watchdog has not fired
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{GBBAR -- Golden Bitstream Base Address Register}
\label{app:multiboot-regs-gbbar}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
BITS
} [\emph{read/write}]: Bits of GBBAR register
\\
31..24 -- Read or fast-read OPCODE of the flash chip (obtain it from the flash chip datasheet) \\ 23..0 -- Golden bitstream address in flash
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{MBBAR -- MultiBoot Bitstream Base Address Register}
\label{app:multiboot-regs-mbbar}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
BITS
} [\emph{read/write}]: Bits of MBBAR register
\\
31..24 -- Read or fast-read OPCODE of the flash chip (obtain it from the flash chip datasheet) \\ 23..0 -- MultiBoot bitstream start address in flash
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{FAR -- Flash Access Register}
\label{app:multiboot-regs-far}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}READY} & \multicolumn{1}{|c|}{\cellcolor{gray!25}CS} & \multicolumn{1}{|c|}{\cellcolor{gray!25}XFER} & \multicolumn{2}{|c|}{\cellcolor{gray!25}NBYTES[1:0]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}DATA[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}DATA[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}DATA[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
DATA
} [\emph{read/write}]: Flash data field
\\
23..16 -- DATA[2]; after an SPI transfer, this register contains the value of data byte 2 read from the flash \\ 15..8 -- DATA[1]; after an SPI transfer, this register contains the value of data byte 1 read from the flash \\ 7..0 -- DATA[0]; after an SPI transfer, this register contains the value of data byte 0 read from the flash
\end{small}
\item \begin{small}
{\bf
NBYTES
} [\emph{read/write}]: Number of DATA fields to send and receive in one transfer:
\\
0x0 -- Send 1 byte (DATA[0]) \\ 0x1 -- Send 2 bytes (DATA[0], DATA[1]) \\ 0x2 -- Send 3 bytes (DATA[0], DATA[1], DATA[2])
\end{small}
\item \begin{small}
{\bf
XFER
} [\emph{write-only}]: Start transfer to and from flash
\\
1 -- Start transfer \\ 0 -- Idle
\end{small}
\item \begin{small}
{\bf
CS
} [\emph{read/write}]: Chip select bit
\\
1 - Flash chip selected (CS pin low) \\ 0 - Flash chip not selected (CS pin is high)
\end{small}
\item \begin{small}
{\bf
READY
} [\emph{read-only}]: Flash access ready
\\
1 - Flash access completed \\ 0 - Flash access in progress
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/ip_cores/ 0000775 0000000 0000000 00000000000 12375155472 0023131 5 ustar 00root root 0000000 0000000 conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/ip_cores/general-cores/ 0000775 0000000 0000000 00000000000 12375155472 0025657 5 ustar 00root root 0000000 0000000 conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/modules/ 0000775 0000000 0000000 00000000000 12375155472 0022776 5 ustar 00root root 0000000 0000000 conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/modules/Manifest.py 0000664 0000000 0000000 00000000265 12375155472 0025121 0 ustar 00root root 0000000 0000000 files = [
"conv_regs.vhd",
"conv_pulse_gen.vhd",
"conv_man_trig.vhd",
"conv_ring_buf.vhd",
"conv_pulse_timetag.vhd",
"conv_reset_gen.vhd"
];
conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/modules/README 0000664 0000000 0000000 00000003025 12375155472 0023656 0 ustar 00root root 0000000 0000000 conv_regs.wb
============
If you change the FIFO width in the top-level conv_ttl_blo.vhd, you need to
also change the width of the USEDW field.
conv_regs.vhd
=============
You need to make some changes to this file after EVERY RUN of wbgen2:
1. Add the following output port declaration after the reg_tbmr_wrtag_i port:
-- Tag buffer read request, asserted when reading from TBMR
reg_tb_rd_req_p_o : out std_logic;
2. Assign the port FOUR TIMES in the register bank process:
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
-- [...]
reg_tb_rd_req_p_o <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
-- [...]
reg_tb_rd_req_p_o <= '0';
ack_in_progress <= '0';
else
-- [...]
reg_tb_rd_req_p_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(3 downto 0) is
[...]
when "1011" =>
if (wb_we_i = '1') then
end if;
reg_tb_rd_req_p_o <= '1';
rddata_reg(5 downto 0) <= reg_tbmr_chan_i;
rddata_reg(31) <= reg_tbmr_wrtag_i;
[...]
conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/modules/conv_man_trig.vhd 0000664 0000000 0000000 00000016571 12375155472 0026340 0 ustar 00root root 0000000 0000000 --==============================================================================
-- CERN (BE-CO-HT)
-- Pulse trigger for pulse converter boards
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2014-01-28
--
-- version: 1.0
--
-- description:
-- This module generates a pulse for the conv_pulse_gen module for manually
-- triggering a debug pulse on a channel output. It works in conjunction
-- with the converter board registers component (conv_regs), from where it
-- obtains the value of the MPT (manual pulse trigger) field in the control
-- register.
--
-- To manually trigger a pulse, a magic sequence of numbers (0xde, 0xad, 0xbe,
-- 0xef) should first be sent to the MPT field, followed by the channel number
-- to send the pulse on. When the channel number is sent, a single pulse is
-- generated by the conv_pulse_gen component at the output.
--
-- The conv_man_trig module checks to see whether the proper magic sequence
-- is written the the MPT field using a simple FSM. The FSM advances when
-- the MPT field is written, if the MPT field corresponds to the proper byte
-- in the magic sequence. If at any time during the magic sequence the value
-- of the MPT field does not correspond to the expected value, the FSM returns
-- to IDLE.
--
-- After the magic sequence is received, the FSM waits for the channel number
-- to be written to the MPT. If a valid channel number is input, a pulse is
-- generated on this channel. The check of whether a valid number is input is
-- based on the g_nr_ttl_chan generic. Should an invalid channel number be
-- input, no error is reported and no pulse is generated.
--
-- The output trigger pulse is extended within the last state of the FSM, to
-- account for when the glitch filter of the conv_pulse_gen component is on.
-- To extend the pulse by an appropriate number of clock cycles, the length
-- of the conv_pulse_gen glitch filter should be input via the g_gf_len.
--
-- dependencies:
-- genram_pkg : git://ohwr.org/hdl-core-lib/general-cores.git
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2014-01-28 Theodor Stana File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.genram_pkg.all;
entity conv_man_trig is
generic
(
-- Number of conversion channels
g_nr_chan : positive := 6;
-- Length of pulse in clk_i cycles generated at trig_o output
g_pwidth : positive := 1
);
port
(
-- Clock, active-low inputs
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Control inputs from conv_regs
reg_ld_i : in std_logic;
reg_i : in std_logic_vector(7 downto 0);
-- Trigger output, g_pwidth long
trig_o : out std_logic_vector(g_nr_chan downto 1)
);
end entity conv_man_trig;
architecture behav of conv_man_trig is
--============================================================================
-- Type declarations
--============================================================================
-- Type for the "password" array
type t_pass_arr is array(integer range <>) of std_logic_vector(7 downto 0);
-- FSM type
type t_state is
(
IDLE,
PASS1,
PASS2,
PASS3,
GET_CHAN,
GEN
);
--============================================================================
-- Constant declarations
--============================================================================
constant c_pass_arr : t_pass_arr(0 to 3) := (x"de", x"ad", x"be", x"ef");
--============================================================================
-- Function and procedures declaration
--============================================================================
procedure f_change_state (
signal ld : in std_logic;
signal pass : in std_logic_vector(7 downto 0);
constant idx : in integer;
signal state : out t_state;
constant nstate : in t_state
) is
begin
if (ld = '1') then
if (pass = c_pass_arr(idx)) then
state <= nstate;
else
state <= IDLE;
end if;
end if;
end procedure f_change_state;
--============================================================================
-- Signal declarations
--============================================================================
-- Signal for the current state of the FSM
signal state : t_state;
-- Counter to create a pulse with width g_pwidth
signal cnt : unsigned(f_log2_size(g_pwidth)-1 downto 0);
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- FSM logic
--============================================================================
p_fsm : process (clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
state <= IDLE;
cnt <= (others => '0');
trig_o <= (others => '0');
else
case state is
when IDLE =>
trig_o <= (others => '0');
f_change_state(reg_ld_i, reg_i, 0, state, PASS1);
when PASS1 =>
f_change_state(reg_ld_i, reg_i, 1, state, PASS2);
when PASS2 =>
f_change_state(reg_ld_i, reg_i, 2, state, PASS3);
when PASS3 =>
f_change_state(reg_ld_i, reg_i, 3, state, GET_CHAN);
when GET_CHAN =>
if (reg_ld_i = '1') then
for i in 1 to g_nr_chan loop
if (i = to_integer(unsigned(reg_i))) then
trig_o(i) <= '1';
end if;
end loop;
cnt <= (others => '0');
state <= GEN;
end if;
when GEN =>
cnt <= cnt + 1;
if (cnt = g_pwidth-1) then
state <= IDLE;
end if;
when others =>
state <= IDLE;
end case;
end if;
end if;
end process p_fsm;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/modules/conv_pulse_gen.vhd 0000664 0000000 0000000 00000034534 12375155472 0026520 0 ustar 00root root 0000000 0000000 --==============================================================================
-- CERN (BE-CO-HT)
-- Pulse generator with trigger
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-03-01
--
-- version: 2.0
--
-- description:
-- This module generates a constant-width pulse. The width is set using the
-- g_pwidth generic, given in number of clk_i cycles. With a clk_i period of
-- 50 ns, the output pulse width is by default 50*24=1.2 us.
--
-- The module is designed to work with an external glitch filter. Enabling
-- this glitch filter will result in jitter on the leading edge of the
-- output pulse signal. This jitter can be avoided by bypassing the glitch
-- filter; this is done via the gf_en_n_i input.
--
-- Regardless of whether the glitch filter is enabled, the input trigger signal
-- is extended or cut to g_pwidth, if it is shorter or respectively longer than
-- g_pwidth. At the end of the pulse, a rejection phase is implemented in order
-- to avoid too many pulses arriving on the input. This is to safeguard the
-- blocking output stage of the CONV-TTL-BLO boards. The isolation phase limits
-- the input pulse to 1/500 duty cycle.
--
-- dependencies:
-- none
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 01-03-2013 Theodor Stana File created.
-- 02-08-2013 Theodor Stana Implemented rejection phase.
-- 17-02-2014 Theodor Stana Moved the glitch filter to outside the
-- module.
-- 04-03-2014 Theodor Stana Added first pulse inhibit on glitch-filtered
-- side.
-- 24-07-2014 Theodor Stana Added g_with_fixed_pwidth generic and
-- subsequent logic.
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity conv_pulse_gen is
generic
(
-- This generic enables elaboration of the fixed pulse width logic
g_with_fixed_pwidth : boolean;
-- Pulse width, in number of clk_i cycles
-- Default pulse width (20 MHz clock): 1.2 us
-- Minimum allowable pulse width (20 MHz clock): 1 us
-- Maximum allowable pulse width (20 MHz clock): 2 us
g_pwidth : natural range 20 to 40 := 24;
-- Duty cycle divider: D = 1/g_duty_cycle_div
g_duty_cycle_div : natural := 5
);
port
(
-- Clock and active-low reset inputs
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Glitch filter enable input
-- '1' - Glitch filter disabled (glitch-sensitive, no output jitter)
-- '0' - Glitch filter enabled (glitch-insensitive, with output jitter)
gf_en_n_i : in std_logic;
-- Enable input, pulse generation is enabled when '1'
en_i : in std_logic;
-- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays.
trig_a_i : in std_logic;
-- Pulse error output, pulses high for one clock cycle when a pulse arrives
-- within a pulse period
pulse_err_p_o : out std_logic;
-- Pulse output, active-high
-- latency:
-- glitch filter disabled: none
-- glitch filter enabled: glitch filter length + 5 clk_i cycles
pulse_o : out std_logic
);
end entity conv_pulse_gen;
architecture behav of conv_pulse_gen is
--============================================================================
-- Type declarations
--============================================================================
type t_state is (
IDLE, -- idle state, wait for pulse
GEN_GF_OFF, -- pulse generation, glitch filter off
REJ_GF_OFF, -- pulse rejection, glitch filter off
GEN_GF_ON, -- pulse generation, glitch filter on
REJ_GF_ON -- pulse rejection, glitch filter on
);
--============================================================================
-- Constant declarations
--============================================================================
-- Max value of pulse counter for pulse width and pulse rejection width.
-- glitch filter OFF:
-- generate:
-- * g_pwidth-1: counter starts from 0
-- * g_pwidth-4: three-cycle delay through synchronizer
-- * g_pwidth-5: reset signal applied in REJ_GF_OFF state
-- reject:
-- * g_duty_cycle_div*g_pwidth: D duty cycle
-- * g_duty_cycle_div*g_pwidth-5: 5-cycle delay added from the generate phase
-- glitch filter ON:
-- generate:
-- * g_pwidth-1: counter starts from 0
-- reject:
-- * g_duty_cycle_div*g_pwidth: D duty cycle
-- * g_duty_cycle_div*g_pwidth-2: need one cycle less to allow for true 1/D
-- duty cycle,
-- since the FSM needs to go through IDLE to accept a pulse
constant c_max_gen_gf_off : natural := g_pwidth-5;
constant c_max_rej_gf_off : natural := g_duty_cycle_div*g_pwidth - 5;
constant c_max_gen_gf_on : natural := g_pwidth-1;
constant c_max_rej_gf_on : natural := g_duty_cycle_div*g_pwidth - 2;
--============================================================================
-- Function and procedure declarations
--============================================================================
function f_log2_size (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 64 bits
if (2**I >= A) then
return(I);
end if;
end loop;
return(63);
end function f_log2_size;
--============================================================================
-- Signal declarations
--============================================================================
-- Trigger signals
signal pulse_gf_off_d0 : std_logic;
signal pulse_gf_off_d1 : std_logic;
signal pulse_gf_off_d2 : std_logic;
signal trig_gf_on : std_logic;
signal trig_gf_on_d0 : std_logic;
signal trig_gf_on_r_edge_p : std_logic;
-- Pulse output signals
signal pulse_gf_on : std_logic;
signal pulse_gf_off : std_logic;
signal pulse_gf_off_rst : std_logic;
signal pulse_gf_off_r_edge_p : std_logic;
-- Pulse length counter
signal pulse_cnt : unsigned(f_log2_size(g_duty_cycle_div*g_pwidth)-1 downto 0);
-- FSM signal
signal state : t_state;
--==============================================================================
-- architecture begin
--==============================================================================
begin
gen_without_fixed_pwidth : if (g_with_fixed_pwidth = false) generate
pulse_o <= trig_a_i;
pulse_err_p_o <= '0';
end generate gen_without_fixed_pwidth;
gen_with_fixed_pwidth : if (g_with_fixed_pwidth = true) generate
--============================================================================
-- Output logic
--============================================================================
pulse_o <= pulse_gf_off when (gf_en_n_i = '1') else
pulse_gf_on;
--============================================================================
-- Pulse generation logic
--============================================================================
-- Generate the pulse on rising edge of trig_a_i
p_pulse_gf_off: process(pulse_gf_off_rst, trig_a_i)
begin
if (pulse_gf_off_rst = '1') then
pulse_gf_off <= '0';
elsif rising_edge(trig_a_i) then
if (en_i = '1') and (gf_en_n_i = '1') then
pulse_gf_off <= '1';
end if;
end if;
end process p_pulse_gf_off;
-- and synchronize the trigger in clk_i domain
p_sync_pulse_gf_off: process (clk_i) is
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
pulse_gf_off_d0 <= '0';
pulse_gf_off_d1 <= '0';
pulse_gf_off_d2 <= '0';
pulse_gf_off_r_edge_p <= '0';
elsif (en_i = '1') and (gf_en_n_i = '1') then
pulse_gf_off_d0 <= pulse_gf_off;
pulse_gf_off_d1 <= pulse_gf_off_d0;
pulse_gf_off_d2 <= pulse_gf_off_d1;
pulse_gf_off_r_edge_p <= pulse_gf_off_d1 and (not pulse_gf_off_d2);
end if;
end if;
end process p_sync_pulse_gf_off;
-- Trigger signal with glitch filter ON is input signal
trig_gf_on <= trig_a_i;
-- Rising edge detector for the trigger signal when glitch filter is ON
p_trig_gf_on : process (clk_i) is
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
trig_gf_on_d0 <= '0';
trig_gf_on_r_edge_p <= '0';
else
trig_gf_on_d0 <= trig_gf_on;
trig_gf_on_r_edge_p <= trig_gf_on and (not trig_gf_on_d0);
end if;
end if;
end process p_trig_gf_on;
--============================================================================
-- Pulse width adjustment logic
--============================================================================
-- Generate the FSM logic
p_pulse_width: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
state <= IDLE;
pulse_gf_off_rst <= '1';
pulse_gf_on <= '0';
pulse_cnt <= (others => '0');
pulse_err_p_o <= '0';
elsif (en_i = '1') then
-- State machine logic
case state is
---------------------------------------------------------------------
-- IDLE
---------------------------------------------------------------------
-- Clear all values and go to pulse generation state when the
-- appropriate input arrives
---------------------------------------------------------------------
when IDLE =>
pulse_cnt <= (others => '0');
pulse_gf_off_rst <= '0';
pulse_err_p_o <= '0';
if (gf_en_n_i = '1') then
if (pulse_gf_off_r_edge_p = '1') then
state <= GEN_GF_OFF;
end if;
else
if (trig_gf_on_r_edge_p = '1') then
state <= GEN_GF_ON;
end if;
end if;
---------------------------------------------------------------------
-- GEN_GF_OFF
---------------------------------------------------------------------
-- Extend the generated pulse to the required pulse width.
---------------------------------------------------------------------
when GEN_GF_OFF =>
-- Pulse logic and state change
pulse_cnt <= pulse_cnt + 1;
if (pulse_cnt = c_max_gen_gf_off) then
state <= REJ_GF_OFF;
end if;
-- Pulse error assignment
pulse_err_p_o <= '0';
if (trig_gf_on_r_edge_p = '1') then
pulse_err_p_o <= '1';
end if;
---------------------------------------------------------------------
-- REJ_GF_OFF
---------------------------------------------------------------------
-- Cut and reject input pulses, to safeguard the output transformers.
---------------------------------------------------------------------
when REJ_GF_OFF =>
-- Pulse logic and state change
pulse_gf_off_rst <= '1';
pulse_cnt <= pulse_cnt + 1;
if (pulse_cnt = c_max_rej_gf_off) then
state <= IDLE;
end if;
-- Pulse error assignment
pulse_err_p_o <= '0';
if (trig_gf_on_r_edge_p = '1') then
pulse_err_p_o <= '1';
end if;
---------------------------------------------------------------------
-- GEN_GF_ON
---------------------------------------------------------------------
-- Start generating the output pulse with the required width.
---------------------------------------------------------------------
when GEN_GF_ON =>
-- Pulse logic and state change
pulse_cnt <= pulse_cnt + 1;
pulse_gf_on <= '1';
if (pulse_cnt = c_max_gen_gf_on) then
state <= REJ_GF_ON;
end if;
-- Pulse error assignment
pulse_err_p_o <= '0';
if (trig_gf_on_r_edge_p = '1') then
pulse_err_p_o <= '1';
end if;
---------------------------------------------------------------------
-- REJ_GF_ON
---------------------------------------------------------------------
-- Stop generating the output pulse and reject incoming pulses.
---------------------------------------------------------------------
when REJ_GF_ON =>
-- Pulse logic and state change
pulse_gf_on <= '0';
pulse_cnt <= pulse_cnt + 1;
if (pulse_cnt = c_max_rej_gf_on) then
state <= IDLE;
end if;
-- Pulse error assignment
pulse_err_p_o <= '0';
if (trig_gf_on_r_edge_p = '1') then
pulse_err_p_o <= '1';
end if;
when others =>
state <= IDLE;
end case;
end if;
end if;
end process p_pulse_width;
end generate gen_with_fixed_pwidth;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/modules/conv_pulse_timetag.vhd 0000664 0000000 0000000 00000017215 12375155472 0027376 0 ustar 00root root 0000000 0000000 --==============================================================================
-- CERN (BE-CO-HT)
-- Pulse time-tagging core
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2014-02-04
--
-- version: 1.0
--
-- description:
-- This module contains the internal timetag counter, counting on an 8 ns
-- clock. When a pulse arrives on the input, it triggers the writing of a
-- timetag to a FIFO memory external to the module.
--
-- dependencies:
-- gencores_pkg : git://ohwr.org/hdl-core-lib/general-cores.git
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2014-02-04 Theodor Stana File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
entity conv_pulse_timetag is
generic
(
-- Frequency in Hz of the clk_i signal
g_clk_rate : positive := 125000000;
-- Number of repetition channels
g_nr_chan : positive := 6
);
port
(
-- Clock and active-low reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Asynchronous pulse input
pulse_a_i : in std_logic_vector(g_nr_chan-1 downto 0);
-- Time inputs from White Rabbit
wr_tm_cycles_i : in std_logic_vector(27 downto 0);
wr_tm_tai_i : in std_logic_vector(39 downto 0);
wr_tm_valid_i : in std_logic;
-- Timing inputs from Wishbone-mapped registers
wb_tm_tai_l_i : in std_logic_vector(31 downto 0);
wb_tm_tai_l_ld_i : in std_logic;
wb_tm_tai_h_i : in std_logic_vector( 7 downto 0);
wb_tm_tai_h_ld_i : in std_logic;
-- Timing outputs
tm_cycles_o : out std_logic_vector(27 downto 0);
tm_tai_o : out std_logic_vector(39 downto 0);
tm_wrpres_o : out std_logic;
chan_p_o : out std_logic_vector(g_nr_chan-1 downto 0);
-- Ring buffer I/O
buf_wr_req_p_o : out std_logic
);
end entity conv_pulse_timetag;
architecture behav of conv_pulse_timetag is
--============================================================================
-- Signal declarations
--============================================================================
signal cycles_cnt : unsigned(27 downto 0);
signal cycles_tick : std_logic;
signal tai_cnt : unsigned(39 downto 0);
signal tai_l_ld : std_logic;
signal tai_h_ld : std_logic;
signal pulse_redge_p : std_logic_vector(g_nr_chan-1 downto 0);
signal pulse_redge_p_d0 : std_logic_vector(g_nr_chan-1 downto 0);
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Time counter logic
--============================================================================
-- The Wishbone bus may be in a different clock domain than the time tag core,
-- so first we need to synchronize the LD signals
cmp_sync_l_ld : gc_sync_ffs
port map
(
clk_i => clk_i,
rst_n_i => rst_n_i,
data_i => wb_tm_tai_l_ld_i,
ppulse_o => tai_l_ld
);
cmp_sync_h_ld : gc_sync_ffs
port map
(
clk_i => clk_i,
rst_n_i => rst_n_i,
data_i => wb_tm_tai_h_ld_i,
ppulse_o => tai_h_ld
);
-- Generate the counters
p_cycle_cnt : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
cycles_cnt <= (others => '0');
cycles_tick <= '0';
else
cycles_cnt <= cycles_cnt + 1;
cycles_tick <= '0';
-- TAI counter loaded from Wishbone
if tai_l_ld = '1' or tai_h_ld = '1' then
cycles_cnt <= (others => '0');
-- Tick and reset on second
elsif cycles_cnt = g_clk_rate-1 then
cycles_cnt <= (others => '0');
cycles_tick <= '1';
end if;
end if;
end if;
end process p_cycle_cnt;
p_tai_cnt : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
tai_cnt <= (others => '0');
-- Load from Wishbone
elsif tai_l_ld = '1' then
tai_cnt(31 downto 0) <= unsigned(wb_tm_tai_l_i);
elsif tai_h_ld = '1' then
tai_cnt(39 downto 32) <= unsigned(wb_tm_tai_h_i);
-- Increment on cycles second tick
elsif cycles_tick = '1' then
tai_cnt <= tai_cnt + 1;
end if;
end if;
end process p_tai_cnt;
--============================================================================
-- Control logic for the FIFO
--============================================================================
-- First, synchronize the pulse inputs in the clk_i domain
gen_sync_chains : for i in 0 to g_nr_chan-1 generate
cmp_pulse_sync : gc_sync_ffs
generic map
(
g_sync_edge => "positive"
)
port map
(
clk_i => clk_i,
rst_n_i => '1',
data_i => pulse_a_i(i),
ppulse_o => pulse_redge_p(i)
);
end generate gen_sync_chains;
-- Set the control signals to the ring buffer on the rising edge of any
-- pulse channel
p_buf_ctrl : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
buf_wr_req_p_o <= '0';
else
buf_wr_req_p_o <= '0';
if not (pulse_redge_p = (pulse_redge_p'range => '0')) then
buf_wr_req_p_o <= '1';
end if;
end if;
end if;
end process p_buf_ctrl;
-- And delay the pulse rising edge for sampling (this is due to the delayed
-- setting of the write signal to the FIFO)
p_dly_pulse : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
pulse_redge_p_d0 <= (others => '0');
else
pulse_redge_p_d0 <= pulse_redge_p;
end if;
end if;
end process p_dly_pulse;
--============================================================================
-- Output logic
--============================================================================
-- Multiplex the timing outputs between WR and internal counters
tm_cycles_o <= wr_tm_cycles_i when wr_tm_valid_i = '1' else
std_logic_vector(cycles_cnt);
tm_tai_o <= wr_tm_tai_i when wr_tm_valid_i = '1' else
std_logic_vector(tai_cnt);
tm_wrpres_o <= wr_tm_valid_i;
chan_p_o <= pulse_redge_p_d0;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/modules/conv_regs.vhd 0000664 0000000 0000000 00000115112 12375155472 0025467 0 ustar 00root root 0000000 0000000 ---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Converter board registers
---------------------------------------------------------------------------------------
-- File : conv_regs.vhd
-- Author : auto-generated by wbgen2 from conv_regs.wb
-- Created : Mon Aug 18 15:56:43 2014
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity conv_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(5 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'ID register bits' in reg: 'BIDR'
reg_bidr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Gateware version' in reg: 'SR'
reg_sr_gwvers_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'Status of on-board general-purpose switches' in reg: 'SR'
reg_sr_switches_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM detection lines~\cite{rtm-det}' in reg: 'SR'
reg_sr_rtm_i : in std_logic_vector(5 downto 0);
-- Ports for BIT field: 'I2C communication watchdog timeout error' in reg: 'SR'
reg_sr_i2c_wdto_o : out std_logic;
reg_sr_i2c_wdto_i : in std_logic;
reg_sr_i2c_wdto_load_o : out std_logic;
-- Port for BIT field: 'White Rabbit present' in reg: 'SR'
reg_sr_wrpres_i : in std_logic;
-- Ports for BIT field: 'I2C communication error' in reg: 'SR'
reg_sr_i2c_err_o : out std_logic;
reg_sr_i2c_err_i : in std_logic;
reg_sr_i2c_err_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse missed error' in reg: 'SR'
reg_sr_pmisse_o : out std_logic_vector(5 downto 0);
reg_sr_pmisse_i : in std_logic_vector(5 downto 0);
reg_sr_pmisse_load_o : out std_logic;
-- Ports for BIT field: 'Reset unlock bit' in reg: 'CR'
reg_cr_rst_unlock_o : out std_logic;
reg_cr_rst_unlock_i : in std_logic;
reg_cr_rst_unlock_load_o : out std_logic;
-- Ports for BIT field: 'Reset bit' in reg: 'CR'
reg_cr_rst_o : out std_logic;
reg_cr_rst_i : in std_logic;
reg_cr_rst_load_o : out std_logic;
-- Ports for PASS_THROUGH field: 'Manual Pulse Trigger' in reg: 'CR'
reg_cr_mpt_o : out std_logic_vector(7 downto 0);
reg_cr_mpt_wr_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH1PCR'
reg_ch1pcr_o : out std_logic_vector(31 downto 0);
reg_ch1pcr_i : in std_logic_vector(31 downto 0);
reg_ch1pcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH2PCR'
reg_ch2pcr_o : out std_logic_vector(31 downto 0);
reg_ch2pcr_i : in std_logic_vector(31 downto 0);
reg_ch2pcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH3PCR'
reg_ch3pcr_o : out std_logic_vector(31 downto 0);
reg_ch3pcr_i : in std_logic_vector(31 downto 0);
reg_ch3pcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH4PCR'
reg_ch4pcr_o : out std_logic_vector(31 downto 0);
reg_ch4pcr_i : in std_logic_vector(31 downto 0);
reg_ch4pcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH5PCR'
reg_ch5pcr_o : out std_logic_vector(31 downto 0);
reg_ch5pcr_i : in std_logic_vector(31 downto 0);
reg_ch5pcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH6PCR'
reg_ch6pcr_o : out std_logic_vector(31 downto 0);
reg_ch6pcr_i : in std_logic_vector(31 downto 0);
reg_ch6pcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'TAI seconds counter bits 31..0' in reg: 'TVLR'
reg_tvlr_o : out std_logic_vector(31 downto 0);
reg_tvlr_i : in std_logic_vector(31 downto 0);
reg_tvlr_load_o : out std_logic;
-- Port for std_logic_vector field: 'TAI seconds counter bits 39..32' in reg: 'TVHR'
reg_tvhr_o : out std_logic_vector(7 downto 0);
reg_tvhr_i : in std_logic_vector(7 downto 0);
reg_tvhr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Channel mask' in reg: 'TBMR'
reg_tbmr_chan_i : in std_logic_vector(5 downto 0);
-- Port for BIT field: 'White Rabbit present' in reg: 'TBMR'
reg_tbmr_wrtag_i : in std_logic;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'TBCYR'
reg_tbcyr_i : in std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'TBTLR'
reg_tbtlr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'TBTHR'
reg_tbthr_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'Buffer counter' in reg: 'TBCSR'
reg_tbcsr_usedw_i : in std_logic_vector(6 downto 0);
-- Port for BIT field: 'Buffer full' in reg: 'TBCSR'
reg_tbcsr_full_i : in std_logic;
-- Port for BIT field: 'Buffer empty' in reg: 'TBCSR'
reg_tbcsr_empty_i : in std_logic;
-- Ports for BIT field: 'Clear tag buffer' in reg: 'TBCSR'
reg_tbcsr_clr_o : out std_logic;
reg_tbcsr_clr_i : in std_logic;
reg_tbcsr_clr_load_o : out std_logic;
-- Tag buffer read request, asserted when reading from TBMR
reg_tb_rd_req_p_o : out std_logic;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH1LTSCYR'
reg_ch1ltscyr_i : in std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH1LTSTLR'
reg_ch1ltstlr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH1LTSTHR'
reg_ch1ltsthr_tai_i : in std_logic_vector(7 downto 0);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH1LTSTHR'
reg_ch1ltsthr_wrtag_i : in std_logic;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH2LTSCYR'
reg_ch2ltscyr_i : in std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH2LTSTLR'
reg_ch2ltstlr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH2LTSTHR'
reg_ch2ltsthr_tai_i : in std_logic_vector(7 downto 0);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH2LTSTHR'
reg_ch2ltsthr_wrtag_i : in std_logic;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH3LTSCYR'
reg_ch3ltscyr_i : in std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH3LTSTLR'
reg_ch3ltstlr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH3LTSTHR'
reg_ch3ltsthr_tai_i : in std_logic_vector(7 downto 0);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH3LTSTHR'
reg_ch3ltsthr_wrtag_i : in std_logic;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH4LTSCYR'
reg_ch4ltscyr_i : in std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH4LTSTLR'
reg_ch4ltstlr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH4LTSTHR'
reg_ch4ltsthr_tai_i : in std_logic_vector(7 downto 0);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH4LTSTHR'
reg_ch4ltsthr_wrtag_i : in std_logic;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH5LTSCYR'
reg_ch5ltscyr_i : in std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH5LTSTLR'
reg_ch5ltstlr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH5LTSTHR'
reg_ch5ltsthr_tai_i : in std_logic_vector(7 downto 0);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH5LTSTHR'
reg_ch5ltsthr_wrtag_i : in std_logic;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH6LTSCYR'
reg_ch6ltscyr_i : in std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH6LTSTLR'
reg_ch6ltstlr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH6LTSTHR'
reg_ch6ltsthr_tai_i : in std_logic_vector(7 downto 0);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH6LTSTHR'
reg_ch6ltsthr_wrtag_i : in std_logic;
-- Port for std_logic_vector field: 'Front panel channel input state' in reg: 'LSR'
reg_lsr_front_i : in std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Front panel INV-TTL input state' in reg: 'LSR'
reg_lsr_frontinv_i : in std_logic_vector(3 downto 0);
-- Port for std_logic_vector field: 'Rear panel input state' in reg: 'LSR'
reg_lsr_rear_i : in std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Input failsafe state' in reg: 'LSR'
reg_lsr_rearfs_i : in std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Multicast address (from switch)' in reg: 'MSWR'
reg_mswr_switches_i : in std_logic_vector(3 downto 0)
);
end conv_regs;
architecture syn of conv_regs is
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(5 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
reg_sr_i2c_wdto_load_o <= '0';
reg_sr_i2c_err_load_o <= '0';
reg_sr_pmisse_load_o <= '0';
reg_cr_rst_unlock_load_o <= '0';
reg_cr_rst_load_o <= '0';
reg_cr_mpt_wr_o <= '0';
reg_ch1pcr_load_o <= '0';
reg_ch2pcr_load_o <= '0';
reg_ch3pcr_load_o <= '0';
reg_ch4pcr_load_o <= '0';
reg_ch5pcr_load_o <= '0';
reg_ch6pcr_load_o <= '0';
reg_tvlr_load_o <= '0';
reg_tvhr_load_o <= '0';
reg_tbcsr_clr_load_o <= '0';
reg_tb_rd_req_p_o <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
reg_sr_i2c_wdto_load_o <= '0';
reg_sr_i2c_err_load_o <= '0';
reg_sr_pmisse_load_o <= '0';
reg_cr_rst_unlock_load_o <= '0';
reg_cr_rst_load_o <= '0';
reg_cr_mpt_wr_o <= '0';
reg_ch1pcr_load_o <= '0';
reg_ch2pcr_load_o <= '0';
reg_ch3pcr_load_o <= '0';
reg_ch4pcr_load_o <= '0';
reg_ch5pcr_load_o <= '0';
reg_ch6pcr_load_o <= '0';
reg_tvlr_load_o <= '0';
reg_tvhr_load_o <= '0';
reg_tbcsr_clr_load_o <= '0';
reg_tb_rd_req_p_o <= '0';
ack_in_progress <= '0';
else
reg_sr_i2c_wdto_load_o <= '0';
reg_sr_i2c_err_load_o <= '0';
reg_sr_pmisse_load_o <= '0';
reg_cr_rst_unlock_load_o <= '0';
reg_cr_rst_load_o <= '0';
reg_cr_mpt_wr_o <= '0';
reg_ch1pcr_load_o <= '0';
reg_ch2pcr_load_o <= '0';
reg_ch3pcr_load_o <= '0';
reg_ch4pcr_load_o <= '0';
reg_ch5pcr_load_o <= '0';
reg_ch6pcr_load_o <= '0';
reg_tvlr_load_o <= '0';
reg_tvhr_load_o <= '0';
reg_tbcsr_clr_load_o <= '0';
reg_tb_rd_req_p_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(5 downto 0) is
when "000000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= reg_bidr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000001" =>
if (wb_we_i = '1') then
reg_sr_i2c_wdto_load_o <= '1';
reg_sr_i2c_err_load_o <= '1';
reg_sr_pmisse_load_o <= '1';
end if;
rddata_reg(7 downto 0) <= reg_sr_gwvers_i;
rddata_reg(15 downto 8) <= reg_sr_switches_i;
rddata_reg(21 downto 16) <= reg_sr_rtm_i;
rddata_reg(22) <= reg_sr_i2c_wdto_i;
rddata_reg(23) <= reg_sr_wrpres_i;
rddata_reg(24) <= reg_sr_i2c_err_i;
rddata_reg(30 downto 25) <= reg_sr_pmisse_i;
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000010" =>
if (wb_we_i = '1') then
reg_cr_rst_unlock_load_o <= '1';
reg_cr_rst_load_o <= '1';
reg_cr_mpt_wr_o <= '1';
end if;
rddata_reg(0) <= reg_cr_rst_unlock_i;
rddata_reg(1) <= reg_cr_rst_i;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000011" =>
if (wb_we_i = '1') then
reg_ch1pcr_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= reg_ch1pcr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000100" =>
if (wb_we_i = '1') then
reg_ch2pcr_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= reg_ch2pcr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000101" =>
if (wb_we_i = '1') then
reg_ch3pcr_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= reg_ch3pcr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000110" =>
if (wb_we_i = '1') then
reg_ch4pcr_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= reg_ch4pcr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "000111" =>
if (wb_we_i = '1') then
reg_ch5pcr_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= reg_ch5pcr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001000" =>
if (wb_we_i = '1') then
reg_ch6pcr_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= reg_ch6pcr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001001" =>
if (wb_we_i = '1') then
reg_tvlr_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= reg_tvlr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001010" =>
if (wb_we_i = '1') then
reg_tvhr_load_o <= '1';
end if;
rddata_reg(7 downto 0) <= reg_tvhr_i;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001011" =>
if (wb_we_i = '1') then
end if;
reg_tb_rd_req_p_o <= '1';
rddata_reg(5 downto 0) <= reg_tbmr_chan_i;
rddata_reg(31) <= reg_tbmr_wrtag_i;
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(27 downto 0) <= reg_tbcyr_i;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= reg_tbtlr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= reg_tbthr_i;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001111" =>
if (wb_we_i = '1') then
reg_tbcsr_clr_load_o <= '1';
end if;
rddata_reg(6 downto 0) <= reg_tbcsr_usedw_i;
rddata_reg(16) <= reg_tbcsr_full_i;
rddata_reg(17) <= reg_tbcsr_empty_i;
rddata_reg(18) <= reg_tbcsr_clr_i;
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(27 downto 0) <= reg_ch1ltscyr_i;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= reg_ch1ltstlr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= reg_ch1ltsthr_tai_i;
rddata_reg(31) <= reg_ch1ltsthr_wrtag_i;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(27 downto 0) <= reg_ch2ltscyr_i;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= reg_ch2ltstlr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= reg_ch2ltsthr_tai_i;
rddata_reg(31) <= reg_ch2ltsthr_wrtag_i;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(27 downto 0) <= reg_ch3ltscyr_i;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= reg_ch3ltstlr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= reg_ch3ltsthr_tai_i;
rddata_reg(31) <= reg_ch3ltsthr_wrtag_i;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(27 downto 0) <= reg_ch4ltscyr_i;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= reg_ch4ltstlr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= reg_ch4ltsthr_tai_i;
rddata_reg(31) <= reg_ch4ltsthr_wrtag_i;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(27 downto 0) <= reg_ch5ltscyr_i;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= reg_ch5ltstlr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= reg_ch5ltsthr_tai_i;
rddata_reg(31) <= reg_ch5ltsthr_wrtag_i;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(27 downto 0) <= reg_ch6ltscyr_i;
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= reg_ch6ltstlr_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= reg_ch6ltsthr_tai_i;
rddata_reg(31) <= reg_ch6ltsthr_wrtag_i;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(5 downto 0) <= reg_lsr_front_i;
rddata_reg(9 downto 6) <= reg_lsr_frontinv_i;
rddata_reg(15 downto 10) <= reg_lsr_rear_i;
rddata_reg(21 downto 16) <= reg_lsr_rearfs_i;
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(3 downto 0) <= reg_mswr_switches_i;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- ID register bits
-- Gateware version
-- Status of on-board general-purpose switches
-- RTM detection lines~\cite{rtm-det}
-- I2C communication watchdog timeout error
reg_sr_i2c_wdto_o <= wrdata_reg(22);
-- White Rabbit present
-- I2C communication error
reg_sr_i2c_err_o <= wrdata_reg(24);
-- Pulse missed error
reg_sr_pmisse_o <= wrdata_reg(30 downto 25);
-- Reset unlock bit
reg_cr_rst_unlock_o <= wrdata_reg(0);
-- Reset bit
reg_cr_rst_o <= wrdata_reg(1);
-- Manual Pulse Trigger
-- pass-through field: Manual Pulse Trigger in register: CR
reg_cr_mpt_o <= wrdata_reg(9 downto 2);
-- Pulse counter value
reg_ch1pcr_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
reg_ch2pcr_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
reg_ch3pcr_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
reg_ch4pcr_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
reg_ch5pcr_o <= wrdata_reg(31 downto 0);
-- Pulse counter value
reg_ch6pcr_o <= wrdata_reg(31 downto 0);
-- TAI seconds counter bits 31..0
reg_tvlr_o <= wrdata_reg(31 downto 0);
-- TAI seconds counter bits 39..32
reg_tvhr_o <= wrdata_reg(7 downto 0);
-- Channel mask
-- White Rabbit present
-- Cycles counter
-- Lower part of TAI seconds counter
-- Upper part of TAI seconds counter
-- Buffer counter
-- Buffer full
-- Buffer empty
-- Clear tag buffer
reg_tbcsr_clr_o <= wrdata_reg(18);
-- Cycles counter
-- Lower part of TAI seconds counter
-- Upper part of TAI seconds counter
-- White Rabbit present
-- Cycles counter
-- Lower part of TAI seconds counter
-- Upper part of TAI seconds counter
-- White Rabbit present
-- Cycles counter
-- Lower part of TAI seconds counter
-- Upper part of TAI seconds counter
-- White Rabbit present
-- Cycles counter
-- Lower part of TAI seconds counter
-- Upper part of TAI seconds counter
-- White Rabbit present
-- Cycles counter
-- Lower part of TAI seconds counter
-- Upper part of TAI seconds counter
-- White Rabbit present
-- Cycles counter
-- Lower part of TAI seconds counter
-- Upper part of TAI seconds counter
-- White Rabbit present
-- Front panel channel input state
-- Front panel INV-TTL input state
-- Rear panel input state
-- Input failsafe state
-- Multicast address (from switch)
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/modules/conv_regs.wb 0000664 0000000 0000000 00000052504 12375155472 0025323 0 ustar 00root root 0000000 0000000 --==============================================================================
-- CERN (BE-CO-HT)
-- Converter board registers wbgen2 description file
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation:
--
-- version: 1.0
--
-- description:
-- This file contains the register description for the converter board
-- registers and is to be used as input to the wbgen2 tool for generating
-- an appropriate VHDL file.
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 03-05-2014 Theodor Stana Added GPL header
-- 31-07-2014 Theodor Stana Added MSWR & LSR registers
--==============================================================================
-- TODO: -
--==============================================================================
peripheral {
name = "Converter board registers";
hdl_entity = "conv_regs";
prefix = "reg";
-- Board ID register
reg {
name = "BIDR";
description = "Board ID Register";
prefix = "bidr";
reset_value = "g_board_id";
field {
name = "ID register bits";
reset_value = "g_board_id";
type = SLV;
size = 32;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
-- Status register
reg {
name = "SR";
description = "Status Register";
prefix = "sr";
field {
name = "Gateware version";
description = "Leftmost nibble hex value is major release decimal value \
Rightmost nibble hex value is minor release decimal value \
e.g. \
0x11 -- v1.1 \
0x2e -- v2.14";
prefix = "gwvers";
type = SLV;
size = 8;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "Status of on-board general-purpose switches";
description = "1 -- switch is ON \
0 -- switch is OFF";
prefix = "switches";
type = SLV;
size = 8;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "RTM detection lines~\\cite{rtm-det}";
description = "1 -- line active \
0 -- line inactive";
prefix = "rtm";
type = SLV;
size = 6;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "I2C communication watchdog timeout error";
description = "1 -- timeout occured \
0 -- no timeout \
This bit can be cleared by writing a '1' to it";
prefix = "i2c_wdto";
type = BIT;
size = 1;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "White Rabbit present";
description = "1 -- White Rabbit present \
0 -- White Rabbit not present";
prefix = "wrpres";
type = BIT;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "I2C communication error";
description = "1 -- attempted to address non-existing address \
0 -- idle \
This bit can be cleared by writing a '1' to it";
prefix = "i2c_err";
type = BIT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Pulse missed error";
description = "1 -- pulse arrived during pulse rejection phase \
0 -- idle \
Bit 0 -- channel 1 \
Bit 1 -- channel 2 \
etc. \
Each bit can be cleared by writing a '1' to it";
prefix = "pmisse";
type = SLV;
size = 6;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
};
-- Control Register
reg {
name = "CR";
description = "Control Register";
prefix = "cr";
-- Logic reset bits
field {
name = "Reset unlock bit";
description = "1 -- Reset bit unlocked \
0 -- Reset bit locked";
prefix = "rst_unlock";
type = BIT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Reset bit";
description = "1 -- initiate logic reset \
0 -- no reset";
prefix = "rst";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Manual Pulse Trigger";
description = "Write the following sequence to trigger a pulse: \
0xde -- Byte 1 of magic sequence \
0xad -- Byte 2 of magic sequence \
0xbe -- Byte 3 of magic sequence \
0xef -- Byte 4 of magic sequence \
Number in range 1..6 -- trigger a pulse";
prefix = "mpt";
size = 8;
type = PASS_THROUGH;
};
};
-- Pulse counter registers, R/W access from SysMon
reg {
name = "CH1PCR";
description = "Channel 1 Pulse Counter Register";
prefix = "ch1pcr";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH2PCR";
description = "Channel 2 Pulse Counter Register";
prefix = "ch2pcr";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH3PCR";
description = "Channel 3 Pulse Counter Register";
prefix = "ch3pcr";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH4PCR";
description = "Channel 4 Pulse Counter Register";
prefix = "ch4pcr";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH5PCR";
description = "Channel 5 Pulse Counter Register";
prefix = "ch5pcr";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH6PCR";
description = "Channel 6 Pulse Counter Register";
prefix = "ch6pcr";
field {
name = "Pulse counter value";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "TVLR";
description = "Time Value Low Register";
prefix = "tvlr";
field {
name = "TAI seconds counter bits 31..0";
description = "Writing this field resets the internal cycles counter.";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "TVHR";
description = "Time Value High Register";
prefix = "tvhr";
field {
name = "TAI seconds counter bits 39..32";
description = "Writing this field resets the internal cycles counter.";
type = SLV;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "TBMR";
description = "Tag Buffer Meta Register";
prefix = "tbmr";
field {
name = "Channel mask";
description = "Mask for the channel(s) that triggered time-tag storage: \
bit 0 -- channel 1 \
bit 1 -- channel 2 \
... \
bit 5 -- channel 6";
prefix = "chan";
type = SLV;
size = 6;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "White Rabbit present";
description = "1 - Current time tag generated with White Rabbit \
0 - Current time tag generated with internal counter";
prefix = "wrtag";
type = BIT;
align = 31;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "TBCYR";
description = "Tag Buffer Cycles Register";
prefix = "tbcyr";
field {
name = "Cycles counter";
description = "Value of the 8-ns cycles counter when time tag was taken.";
type = SLV;
size = 28;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "TBTLR";
description = "Tag Buffer TAI Low Register";
prefix = "tbtlr";
field {
name = "Lower part of TAI seconds counter";
description = "Value of the TAI seconds counter bits 31..0 when time tag was taken.";
type = SLV;
size = 32;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "TBTHR";
description = "Tag Buffer TAI High Register";
prefix = "tbthr";
field {
name = "Upper part of TAI seconds counter";
description = "Value of the TAI seconds counter bits 39..32 when time tag was taken.";
type = SLV;
size = 8;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "TBCSR";
description = "Tag Buffer Control and Status Register";
prefix = "tbcsr";
field {
name = "Buffer counter";
prefix = "usedw";
description = "Number of samples in the ring buffer";
type = SLV;
size = 7;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "Buffer full";
description = "1 -- buffer full \
0 -- buffer is not full";
prefix = "full";
type = BIT;
align = 16;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "Buffer empty";
description = "1 -- buffer empty\
0 -- buffer is not empty";
prefix = "empty";
type = BIT;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "Clear tag buffer";
description = "1 -- clear\
0 -- no effect";
prefix = "clr";
type = BIT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CH1LTSCYR";
description = "Channel 1 Latest Timestamp Cycles Register";
prefix = "ch1ltscyr";
field {
name = "Cycles counter";
description = "Value of the 8-ns cycles counter when time tag was taken.";
type = SLV;
size = 28;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "CH1LTSTLR";
description = "Channel 1 Latest Timestamp TAI Low Register";
prefix = "ch1ltstlr";
field {
name = "Lower part of TAI seconds counter";
description = "Value of the TAI seconds counter bits 31..0 when time tag was taken.";
type = SLV;
size = 32;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "CH1LTSTHR";
description = "Channel 1 Latest Timestamp TAI High Register";
prefix = "ch1ltsthr";
field {
name = "Upper part of TAI seconds counter";
description = "Value of the TAI seconds counter bits 39..32 when time tag was taken.";
prefix = "tai";
type = SLV;
size = 8;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "White Rabbit present";
description = "1 - Current time tag generated with White Rabbit \
0 - Current time tag generated with internal counter";
prefix = "wrtag";
type = BIT;
align = 31;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "CH2LTSCYR";
description = "Channel 2 Latest Timestamp Cycles Register";
prefix = "ch2ltscyr";
field {
name = "Cycles counter";
description = "Value of the 8-ns cycles counter when time tag was taken.";
type = SLV;
size = 28;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "CH2LTSTLR";
description = "Channel 2 Latest Timestamp TAI Low Register";
prefix = "ch2ltstlr";
field {
name = "Lower part of TAI seconds counter";
description = "Value of the TAI seconds counter bits 31..0 when time tag was taken.";
type = SLV;
size = 32;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "CH2LTSTHR";
description = "Channel 2 Latest Timestamp TAI High Register";
prefix = "ch2ltsthr";
field {
name = "Upper part of TAI seconds counter";
description = "Value of the TAI seconds counter bits 39..32 when time tag was taken.";
prefix = "tai";
type = SLV;
size = 8;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "White Rabbit present";
description = "1 - Current time tag generated with White Rabbit \
0 - Current time tag generated with internal counter";
prefix = "wrtag";
type = BIT;
align = 31;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "CH3LTSCYR";
description = "Channel 3 Latest Timestamp Cycles Register";
prefix = "ch3ltscyr";
field {
name = "Cycles counter";
description = "Value of the 8-ns cycles counter when time tag was taken.";
type = SLV;
size = 28;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "CH3LTSTLR";
description = "Channel 3 Latest Timestamp TAI Low Register";
prefix = "ch3ltstlr";
field {
name = "Lower part of TAI seconds counter";
description = "Value of the TAI seconds counter bits 31..0 when time tag was taken.";
type = SLV;
size = 32;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "CH3LTSTHR";
description = "Channel 3 Latest Timestamp TAI High Register";
prefix = "ch3ltsthr";
field {
name = "Upper part of TAI seconds counter";
description = "Value of the TAI seconds counter bits 39..32 when time tag was taken.";
prefix = "tai";
type = SLV;
size = 8;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "White Rabbit present";
description = "1 - Current time tag generated with White Rabbit \
0 - Current time tag generated with internal counter";
prefix = "wrtag";
type = BIT;
align = 31;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "CH4LTSCYR";
description = "Channel 4 Latest Timestamp Cycles Register";
prefix = "ch4ltscyr";
field {
name = "Cycles counter";
description = "Value of the 8-ns cycles counter when time tag was taken.";
prefix = "tai";
type = SLV;
size = 28;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "CH4LTSTLR";
description = "Channel 4 Latest Timestamp TAI Low Register";
prefix = "ch4ltstlr";
field {
name = "Lower part of TAI seconds counter";
description = "Value of the TAI seconds counter bits 31..0 when time tag was taken.";
type = SLV;
size = 32;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "CH4LTSTHR";
description = "Channel 4 Latest Timestamp TAI High Register";
prefix = "ch4ltsthr";
field {
name = "Upper part of TAI seconds counter";
description = "Value of the TAI seconds counter bits 39..32 when time tag was taken.";
prefix = "tai";
type = SLV;
size = 8;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "White Rabbit present";
description = "1 - Current time tag generated with White Rabbit \
0 - Current time tag generated with internal counter";
prefix = "wrtag";
type = BIT;
align = 31;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "CH5LTSCYR";
description = "Channel 5 Latest Timestamp Cycles Register";
prefix = "ch5ltscyr";
field {
name = "Cycles counter";
description = "Value of the 8-ns cycles counter when time tag was taken.";
type = SLV;
size = 28;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "CH5LTSTLR";
description = "Channel 5 Latest Timestamp TAI Low Register";
prefix = "ch5ltstlr";
field {
name = "Lower part of TAI seconds counter";
description = "Value of the TAI seconds counter bits 31..0 when time tag was taken.";
type = SLV;
size = 32;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "CH5LTSTHR";
description = "Channel 5 Latest Timestamp TAI High Register";
prefix = "ch5ltsthr";
field {
name = "Upper part of TAI seconds counter";
description = "Value of the TAI seconds counter bits 39..32 when time tag was taken.";
prefix = "tai";
type = SLV;
size = 8;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "White Rabbit present";
description = "1 - Current time tag generated with White Rabbit \
0 - Current time tag generated with internal counter";
prefix = "wrtag";
type = BIT;
align = 31;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "CH6LTSCYR";
description = "Channel 6 Latest Timestamp Cycles Register";
prefix = "ch6ltscyr";
field {
name = "Cycles counter";
description = "Value of the 8-ns cycles counter when time tag was taken.";
type = SLV;
size = 28;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "CH6LTSTLR";
description = "Channel 6 Latest Timestamp TAI Low Register";
prefix = "ch6ltstlr";
field {
name = "Lower part of TAI seconds counter";
description = "Value of the TAI seconds counter bits 31..0 when time tag was taken.";
type = SLV;
size = 32;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "CH6LTSTHR";
description = "Channel 6 Latest Timestamp TAI High Register";
prefix = "ch6ltsthr";
field {
name = "Upper part of TAI seconds counter";
description = "Value of the TAI seconds counter bits 39..32 when time tag was taken.";
prefix = "tai";
type = SLV;
size = 8;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "White Rabbit present";
description = "1 - Current time tag generated with White Rabbit \
0 - Current time tag generated with internal counter";
prefix = "wrtag";
type = BIT;
align = 31;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "LSR";
description = "Line Status Register";
prefix = "lsr";
field {
name = "Front panel channel input state";
description = "Line state at board input\
Bit 0 -- channel 1\
Bit 1 -- channel 2\
etc.";
prefix = "front";
type = SLV;
size = 6;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "Front panel INV-TTL input state";
description = "Line state at board input\
Bit 0 -- channel 1\
Bit 1 -- channel 2\
etc.";
prefix = "frontinv";
type = SLV;
size = 4;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "Rear panel input state";
description = "Line state at board input\
Bit 0 -- channel 1\
Bit 1 -- channel 2\
etc.";
prefix = "rear";
type = SLV;
size = 6;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "Input failsafe state";
description = "High if line is in failsafe mode (no cable plugged in)\
Bit 0 -- channel 1\
Bit 1 -- channel 2\
etc.";
prefix = "rearfs";
type = SLV;
size = 6;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "MSWR";
description = "Multicast Switch Register";
prefix = "mswr";
field {
name = "Multicast address (from switch)";
description = "1 -- switch is ON \
0 -- switch is OFF";
prefix = "switches";
type = SLV;
size = 4;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
};
conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/modules/conv_reset_gen.vhd 0000664 0000000 0000000 00000010014 12375155472 0026475 0 ustar 00root root 0000000 0000000 --==============================================================================
-- CERN (BE-CO-HT)
-- Reset generator for CONV-TTL-* boards
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-03-05
--
-- version: 1.0
--
-- description:
-- This module generates a controllable-width reset pulse. The width of the
-- reset pulse is set via the g_reset_time pulse; an internal counter counts
-- up to this value and de-asserts the active-low reset line when the value
-- has been reached. At the same time, the module is de-activated.
--
-- By default, a 20 MHz clock (50 ns period) is assumed, resulting in a 100ms
-- reset width.
--
-- dependencies:
-- none
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-03-05 Theodor Stana File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity conv_reset_gen is
generic
(
-- Reset time in number of clk_i cycles
g_reset_time : positive := 2_000_000
);
port
(
clk_i : in std_logic;
rst_i : in std_logic;
rst_n_o : out std_logic
);
end entity conv_reset_gen;
architecture behav of conv_reset_gen is
--============================================================================
-- Function and procedure declarations
--============================================================================
function f_log2_size (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 64 bits
if (2**I >= A) then
return(I);
end if;
end loop;
return(63);
end function f_log2_size;
--============================================================================
-- Signal declarations
--============================================================================
signal cnt : unsigned(f_log2_size(g_reset_time)-1 downto 0) := (others => '0');
signal cnt_en : std_logic := '1';
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Reset generation logic
--============================================================================
p_rst_gen: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_i = '1') then
cnt_en <= '1';
cnt <= (others => '0');
elsif (cnt_en = '1') then
rst_n_o <= '0';
cnt <= cnt + 1;
if (cnt = g_reset_time-1) then
rst_n_o <= '1';
cnt_en <= '0';
end if;
end if;
end if;
end process p_rst_gen;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/modules/conv_ring_buf.vhd 0000664 0000000 0000000 00000020046 12375155472 0026323 0 ustar 00root root 0000000 0000000 --==============================================================================
-- CERN (BE-CO-HT)
-- Ring buffer for converter board designs
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2014-03-19
--
-- version: 1.0
--
-- description:
-- Ring buffer memory with configurable (at synthesis time) data width and
-- size. Although created for the converter board design, it can be used in
-- any desing.
--
-- dependencies:
-- genram_pkg : git://ohwr.org/hdl-core-lib/general-cores.git
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2014-03-19 Theodor Stana Created file and copied content from
-- fd_ring_buffer.
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.genram_pkg.all;
entity conv_ring_buf is
generic
(
-- Buffer data input and output width
g_data_width : positive;
-- Buffer size in number of samples
g_size : positive
);
port
(
-- Clocks and reset
clk_rd_i : in std_logic;
clk_wr_i : in std_logic;
rst_n_a_i : in std_logic;
-- Buffer inputs
buf_dat_i : in std_logic_vector(g_data_width-1 downto 0);
buf_rd_req_i : in std_logic;
buf_wr_req_i : in std_logic;
buf_clr_i : in std_logic;
-- Buffer outputs
buf_dat_o : out std_logic_vector(g_data_width-1 downto 0);
buf_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
buf_full_o : out std_logic;
buf_empty_o : out std_logic
);
end entity conv_ring_buf;
architecture behav of conv_ring_buf is
--============================================================================
-- Type declarations
--============================================================================
--============================================================================
-- Constant declarations
--============================================================================
constant c_fifo_size : positive := 8;
--============================================================================
-- Signal declarations
--============================================================================
-- FIFO signals
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_read : std_logic;
signal fifo_read_d0 : std_logic;
signal fifo_write : std_logic;
signal fifo_in : std_logic_vector(g_data_width-1 downto 0);
signal fifo_out : std_logic_vector(g_data_width-1 downto 0);
-- Buffer signals
signal buf_write : std_logic;
signal buf_read : std_logic;
signal buf_wr_ptr : unsigned(f_log2_size(g_size)-1 downto 0);
signal buf_rd_ptr : unsigned(f_log2_size(g_size)-1 downto 0);
signal buf_wr_data : std_logic_vector(g_data_width-1 downto 0);
signal buf_rd_data : std_logic_vector(g_data_width-1 downto 0);
signal buf_count : unsigned(f_log2_size(g_size)-1 downto 0);
signal buf_empty : std_logic;
signal buf_full : std_logic;
signal buf_overflow : std_logic;
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Buffer FIFO and RAM
--============================================================================
-- Assign FIFO input and control
fifo_in <= buf_dat_i;
fifo_write <= not fifo_full and buf_wr_req_i;
fifo_read <= not fifo_empty;
-- Instantiate FIFO to synchronize data inputs from read clock to write clock
cmp_clk_adjust_fifo : generic_async_fifo
generic map
(
g_data_width => fifo_in'length,
g_size => c_fifo_size
)
port map (
rst_n_i => rst_n_a_i,
clk_wr_i => clk_wr_i,
d_i => fifo_in,
we_i => fifo_write,
wr_full_o => fifo_full,
clk_rd_i => clk_rd_i,
q_o => fifo_out,
rd_i => fifo_read,
rd_empty_o => fifo_empty);
-- Instantiate the actual buffer RAM
-- The buffer gets fed with data from the FIFO
buf_wr_data <= fifo_out;
cmp_buf_ram : generic_dpram
generic map (
g_data_width => g_data_width,
g_size => g_size,
g_dual_clock => false)
port map (
rst_n_i => rst_n_a_i,
clka_i => clk_rd_i,
bwea_i => (others => '1'),
wea_i => buf_write,
aa_i => std_logic_vector(buf_wr_ptr),
da_i => buf_wr_data,
qa_o => open,
clkb_i => clk_rd_i,
bweb_i => (others => '0'),
web_i => '0',
ab_i => std_logic_vector(buf_rd_ptr),
db_i => (others => '0'),
qb_o => buf_rd_data);
--============================================================================
-- Buffer control
--============================================================================
-- Assign buffer control signals
buf_write <= fifo_read_d0;
buf_read <= '1' when ((buf_rd_req_i = '1') and (buf_empty = '0')) or
(buf_overflow = '1')
else '0';
buf_overflow <= '1' when (buf_write = '1') and (buf_full = '1') else '0';
-- Buffer control process
p_buffer_control : process(clk_rd_i)
begin
if rising_edge(clk_rd_i) then
if (rst_n_a_i = '0') or (buf_clr_i = '1') then
buf_rd_ptr <= (others => '0');
buf_wr_ptr <= (others => '0');
buf_count <= (others => '0');
buf_full <= '0';
buf_empty <= '1';
fifo_read_d0 <= '0';
else
fifo_read_d0 <= fifo_read;
-- Read and write signals
if(buf_write = '1') then
buf_wr_ptr <= buf_wr_ptr + 1;
end if;
if(buf_read = '1') then
buf_rd_ptr <= buf_rd_ptr + 1;
end if;
-- Buffer count and full/empty control
if (buf_write = '1') and (buf_read = '0') and (buf_full = '0') then
buf_count <= buf_count + 1;
buf_empty <= '0';
if (buf_count = (buf_count'range => '1')) then
buf_full <= '1';
end if;
end if;
if (buf_write = '0') and (buf_read = '1') and (buf_empty = '0') then
buf_count <= buf_count - 1;
buf_full <= '0';
if (buf_count = 1) then
buf_empty <= '1';
end if;
end if;
end if;
end if;
end process;
--============================================================================
-- Output signals
--============================================================================
buf_full_o <= buf_full;
buf_empty_o <= buf_empty;
buf_count_o <= std_logic_vector(buf_count);
buf_dat_o <= buf_rd_data;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/top/ 0000775 0000000 0000000 00000000000 12375155472 0022130 5 ustar 00root root 0000000 0000000 conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/top/Manifest.py 0000664 0000000 0000000 00000000266 12375155472 0024254 0 ustar 00root root 0000000 0000000 files = [
"conv_common_gw.vhd",
"conv_common_gw_pkg.vhd"
]
modules = {
"local" : [
"../ip_cores/general-cores",
"../modules"
]
}
conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/top/conv_common_gw.vhd 0000664 0000000 0000000 00000130730 12375155472 0025651 0 ustar 00root root 0000000 0000000 --==============================================================================
-- CERN (BE-CO-HT)
-- Converter board common gateware top-level file
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2014-07-24
--
-- version: 1.0
--
-- description:
-- This module is to be instantiated in all pulse converter board designs,
-- for example the CONV-TTL-BLO or CONV-TTL-RS485. It contains a set of
-- modules common to all these boards, that are configurable via generics to
-- accommodate for the application of each board.
--
-- dependencies:
-- general-cores repository [1]
--
-- references:
-- [1] Board IDs for level conversion circuits
-- www.ohwr.org/projects/conv-common-gw/wiki/Board-id
-- [2] Platform-independent core collection webpage on OHWR,
-- http://www.ohwr.org/projects/general-cores/repository
-- [3] ELMA, Access to board data using SNMP and I2C
-- http://www.ohwr.org/documents/227
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2014-07-24 Theodor Stana File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.genram_pkg.all;
use work.conv_common_gw_pkg.all;
entity conv_common_gw is
generic
(
-- Number of repeater channels
g_nr_chans : integer := 6;
-- Board ID -- 4-letter ASCII string indicating the board ID
-- see [1] for example
g_board_id : std_logic_vector(31 downto 0);
-- Gateware version
g_gwvers : std_logic_vector(7 downto 0);
-- Generate pulse repetition logic with fixed output pulse width
g_pgen_fixed_width : boolean;
-- Pulse width at pulse generator output (valid with fixed output pulse width)
g_pgen_pwidth : natural range 20 to 40 := 24;
-- Duty cycle divider ratio for pulse generator
-- output pulse will be limited to 1/g_pgen_duty_cycle_div
g_pgen_duty_cycle_div : natural := 5;
-- Pulse generator glitch filter length in number of clk_20_i cycles
g_pgen_gf_len : integer := 4;
-- Generate logic with pulse counters
g_with_pulse_cnt : boolean := false;
-- Generate logic with pulse counters
g_with_pulse_timetag : boolean := false;
-- Generate logic with manual trigger
g_with_man_trig : boolean := false;
g_man_trig_pwidth : integer := 24;
-- Generate one-wire master for thermometer
g_with_thermometer : boolean := false;
-- Bicolor LED controller signals
g_bicolor_led_columns : integer := 6;
g_bicolor_led_lines : integer := 2
);
port
(
-- Clocks
clk_20_i : in std_logic;
clk_125_p_i : in std_logic;
clk_125_n_i : in std_logic;
-- Reset output signal, synchronous to 20 MHz clock
rst_n_o : out std_logic;
-- Glitch filter active-low enable signal
gf_en_n_i : in std_logic;
-- Channel enable
global_ch_oen_o : out std_logic;
pulse_front_oen_o : out std_logic;
pulse_rear_oen_o : out std_logic;
inv_oen_o : out std_logic;
-- Pulse inputs
pulse_i : in std_logic_vector(g_nr_chans-1 downto 0);
pulse_o : out std_logic_vector(g_nr_chans-1 downto 0);
-- Channel leds
-- 26 ms active-high pulse on pulse_o rising edge
led_pulse_o : out std_logic_vector(g_nr_chans-1 downto 0);
-- I2C interface
scl_i : in std_logic;
scl_o : out std_logic;
scl_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
sda_en_o : out std_logic;
-- I2C LED signals -- conect to a bicolor LED of choice
-- led_i2c_o pulses four times on I2C transfer
-- led_i2c_err_o is high when either SR.I2C_ERR = '1' or SR.I2C_WDTO = '1'
led_i2c_o : out std_logic;
led_i2c_err_o : out std_logic;
-- VME interface
vme_sysreset_n_i : in std_logic;
vme_ga_i : in std_logic_vector(4 downto 0);
vme_gap_i : in std_logic;
-- SPI interface to on-board flash chip
flash_cs_n_o : out std_logic;
flash_sclk_o : out std_logic;
flash_mosi_o : out std_logic;
flash_miso_i : in std_logic;
-- PLL DACs
-- 20 MHz VCXO control
dac20_din_o : out std_logic;
dac20_sclk_o : out std_logic;
dac20_sync_n_o : out std_logic;
-- 125 MHz clock generator control
dac125_din_o : out std_logic;
dac125_sclk_o : out std_logic;
dac125_sync_n_o : out std_logic;
-- SFP lines
sfp_los_i : in std_logic;
sfp_mod_def0_i : in std_logic;
sfp_rate_select_o : out std_logic;
sfp_mod_def1_b : inout std_logic;
sfp_mod_def2_b : inout std_logic;
sfp_tx_disable_o : out std_logic;
sfp_tx_fault_i : in std_logic;
-- Switch inputs (for readout from converter status register)
sw_gp_i : in std_logic_vector(7 downto 0);
sw_multicast_i : in std_logic_vector(3 downto 0);
-- RTM lines
rtmm_i : in std_logic_vector(2 downto 0);
rtmp_i : in std_logic_vector(2 downto 0);
-- TTL, INV-TTL and rear-panel channel inputs, for reflection in line status register
line_front_i : in std_logic_vector(g_nr_chans-1 downto 0);
line_inv_i : in std_logic_vector(3 downto 0);
line_rear_i : in std_logic_vector(g_nr_chans-1 downto 0);
line_rear_fs_i : in std_logic_vector(g_nr_chans-1 downto 0);
-- Thermometer line
thermometer_b : inout std_logic;
-- Bicolor LED signals
bicolor_led_state_i : in std_logic_vector(2*g_bicolor_led_columns*g_bicolor_led_lines-1 downto 0);
bicolor_led_col_o : out std_logic_vector(g_bicolor_led_columns-1 downto 0);
bicolor_led_line_o : out std_logic_vector(g_bicolor_led_lines-1 downto 0);
bicolor_led_line_oen_o : out std_logic_vector(g_bicolor_led_lines-1 downto 0)
);
end entity conv_common_gw;
architecture arch of conv_common_gw is
--============================================================================
-- Constant declarations
--============================================================================
-- Number of Wishbone masters and slaves, for wb_crossbar
constant c_nr_masters : natural := 1;
constant c_nr_slaves : natural := 3;
-- slave order definitions
constant c_slv_conv_regs : natural := 0;
constant c_slv_multiboot : natural := 1;
constant c_slv_onewire_mst : natural := 2;
-- base address definitions
constant c_addr_conv_regs : t_wishbone_address := x"00000000";
constant c_addr_multiboot : t_wishbone_address := x"00000100";
constant c_addr_onewire_mst : t_wishbone_address := x"00000200";
constant c_addr_sdb : t_wishbone_address := x"00000f00";
-- SDB interconnect layout
-- c_conv_regs_sdb defined in conv_common_gw_pkg.vhd
constant c_sdb_layout : t_sdb_record_array(c_nr_slaves-1 downto 0) := (
c_slv_conv_regs => f_sdb_embed_device(c_conv_regs_sdb, c_addr_conv_regs),
c_slv_multiboot => f_sdb_embed_device(c_xwb_xil_multiboot_sdb,
c_addr_multiboot),
c_slv_onewire_mst => f_sdb_embed_device(c_xwb_onewire_master_sdb,
c_addr_onewire_mst)
);
-- Tag bufferdata width: 40 -- TAI
-- 28 -- cycles
-- 1 -- WRPRES bit
-- xx -- channel mask for max. nr. channels
constant c_tagbuff_data_width : positive := 40 + 28 + 1 + c_max_nr_chans;
--============================================================================
-- Type declarations
--============================================================================
-- Max. channel count of c_max_nr_chans enforced here:
type t_pulse_led_cnt is array(c_max_nr_chans-1 downto 0)
of unsigned(18 downto 0);
type t_pulse_cnt is array(c_max_nr_chans-1 downto 0)
of unsigned(31 downto 0);
type t_ch_pcr is array(c_max_nr_chans-1 downto 0)
of std_logic_vector(31 downto 0);
type t_latest_timestamp_tai is array(c_max_nr_chans-1 downto 0)
of std_logic_vector(39 downto 0);
type t_latest_timestamp_cycles is array(c_max_nr_chans-1 downto 0)
of std_logic_vector(27 downto 0);
--============================================================================
-- Signal declarations
--============================================================================
-- Per-domain clock and reset signals
signal clk_125 : std_logic;
signal rst_125_n : std_logic;
signal rst_20_n : std_logic;
signal rst_ext : std_logic;
-- Pulse logic signals
signal trig_a : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_synced : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_degl : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_chan : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_chan_redge_p : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_man : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_pgen : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_d0 : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_redge_p : std_logic_vector(g_nr_chans-1 downto 0);
signal pmisse_p : std_logic_vector(g_nr_chans-1 downto 0);
-- Output enable signals
signal global_oen : std_logic;
signal ttl_oen, invttl_oen : std_logic;
signal rear_oen : std_logic;
-- I2C bridge signals
signal i2c_addr : std_logic_vector(6 downto 0);
signal i2c_tip : std_logic;
signal i2c_err_p : std_logic;
signal i2c_wdto_p : std_logic;
-- Signals to/from converter system registers component
signal rtm_lines : std_logic_vector(5 downto 0);
signal sw_gp : std_logic_vector(7 downto 0);
signal sw_multicast : std_logic_vector(3 downto 0);
signal rst_unlock : std_logic;
signal rst_unlock_bit : std_logic;
signal rst_unlock_bit_ld : std_logic;
signal rst_bit : std_logic;
signal rst_bit_ld : std_logic;
signal rst_fr_reg : std_logic;
signal i2c_wdto_bit : std_logic;
signal i2c_wdto_bit_rst : std_logic;
signal i2c_wdto_bit_rst_ld : std_logic;
signal pmisse_bit : std_logic_vector(c_max_nr_chans-1 downto 0);
signal pmisse_bit_rst : std_logic_vector(c_max_nr_chans-1 downto 0);
signal pmisse_bit_rst_ld : std_logic;
signal pulse_cnt : t_pulse_cnt;
signal ch_pcr : t_ch_pcr;
signal ch_pcr_ld : std_logic_vector(c_max_nr_chans-1 downto 0);
signal mpt_ld : std_logic;
signal mpt : std_logic_vector( 7 downto 0);
signal tvlr : std_logic_vector(31 downto 0);
signal tvlr_ld : std_logic;
signal tvhr : std_logic_vector( 7 downto 0);
signal tvhr_ld : std_logic;
signal wrpres : std_logic;
signal i2c_err_bit : std_logic;
signal i2c_err_bit_rst : std_logic;
signal i2c_err_bit_rst_ld : std_logic;
signal line_front : std_logic_vector(c_max_nr_chans-1 downto 0);
signal line_rear : std_logic_vector(c_max_nr_chans-1 downto 0);
signal line_rear_fs : std_logic_vector(c_max_nr_chans-1 downto 0);
-- LED signals
signal led_pulse : std_logic_vector(g_nr_chans-1 downto 0);
signal led_pulse_cnt : t_pulse_led_cnt;
signal led_i2c : std_logic;
signal led_i2c_clkdiv : unsigned(18 downto 0);
signal led_i2c_cnt : unsigned( 2 downto 0);
signal led_i2c_blink : std_logic;
-- Wishbone crossbar signals
signal xbar_slave_in : t_wishbone_slave_in_array (c_nr_masters-1 downto 0);
signal xbar_slave_out : t_wishbone_slave_out_array (c_nr_masters-1 downto 0);
signal xbar_master_in : t_wishbone_master_in_array (c_nr_slaves-1 downto 0);
signal xbar_master_out : t_wishbone_master_out_array(c_nr_slaves-1 downto 0);
-- Time-tagging component signals
signal tm_cycles : std_logic_vector(27 downto 0);
signal tm_tai : std_logic_vector(39 downto 0);
signal buf_wr_req_p : std_logic;
signal buf_rd_req_p : std_logic;
signal buf_count : std_logic_vector(f_log2_size(128)-1 downto 0);
signal buf_full : std_logic;
signal buf_empty : std_logic;
signal buf_chan : std_logic_vector(g_nr_chans-1 downto 0);
signal buf_wrtag : std_logic;
signal buf_clr_bit : std_logic;
signal buf_clr_bit_ld : std_logic;
signal buf_clr_p : std_logic;
signal buf_dat_in : std_logic_vector(c_tagbuff_data_width-1 downto 0);
signal buf_dat_out : std_logic_vector(c_tagbuff_data_width-1 downto 0);
-- Latest timestamp signals
signal latest_timestamp_ld : std_logic_vector(c_max_nr_chans-1 downto 0);
signal latest_timestamp_tai : t_latest_timestamp_tai;
signal latest_timestamp_cycles : t_latest_timestamp_cycles;
signal latest_timestamp_wrtag : std_logic_vector(c_max_nr_chans-1 downto 0);
-- One-wire master signals
signal owr_en : std_logic_vector(0 downto 0);
signal owr_in : std_logic_vector(0 downto 0);
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Differential input buffer for 125 MHz clock
--============================================================================
cmp_clk_125_buf : IBUFGDS
generic map (
DIFF_TERM => true, -- Differential Termination
IBUF_LOW_PWR => true, -- Low power (TRUE) vs. performance (FALSE) setting
-- for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => clk_125,
I => clk_125_p_i,
IB => clk_125_n_i
);
--============================================================================
-- Internal and external reset generation
--============================================================================
-- External reset input to reset generator
rst_ext <= rst_fr_reg or (not vme_sysreset_n_i);
-- Configure reset generator for 100ms power-on reset
cmp_reset_gen : conv_reset_gen
generic map
(
-- Reset time: 50ns * 2 * (10**6) = 100 ms
g_reset_time => 2*(10**6)
)
port map
(
clk_i => clk_20_i,
rst_i => rst_ext,
rst_n_o => rst_20_n
);
-- Output reset signal is synchronous to the 20 MHz clock
rst_n_o <= rst_20_n;
-- And synchronize the 20 MHz domain reset into the 125 MHz domain
cmp_sync_rst : gc_sync_ffs
generic map
(
g_sync_edge => "positive"
)
port map
(
clk_i => clk_125,
rst_n_i => '1',
data_i => rst_20_n,
synced_o => rst_125_n
);
--============================================================================
-- Output enable logic
--============================================================================
-- Enable outputs only when the FPGA is ready to handle them
-- One clock cycle delay from global OEN to rest of OENs
p_delay_oen : process (clk_20_i) is
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
global_oen <= '0';
ttl_oen <= '0';
invttl_oen <= '0';
rear_oen <= '0';
else
global_oen <= '1';
if global_oen = '1' then
ttl_oen <= '1';
invttl_oen <= '1';
rear_oen <= '1';
end if;
end if;
end if;
end process p_delay_oen;
-- Assign OEN outputs
global_ch_oen_o <= global_oen;
pulse_front_oen_o <= ttl_oen;
inv_oen_o <= invttl_oen;
pulse_rear_oen_o <= rear_oen;
--============================================================================
-- Pulse repetition logic
--============================================================================
trig_a <= pulse_i;
--------------------------------------------------------------------------------
gen_man_trig : if (g_with_man_trig = true) generate
-- Manual trigger logic
cmp_man_trig : conv_man_trig
generic map
(
g_nr_chan => g_nr_chans,
g_pwidth => g_man_trig_pwidth
)
port map
(
clk_i => clk_20_i,
rst_n_i => rst_20_n,
reg_ld_i => mpt_ld,
reg_i => mpt,
trig_o => trig_man
);
end generate gen_man_trig;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
gen_no_man_trig : if (g_with_man_trig = false) generate
trig_man <= (others => '0');
end generate gen_no_man_trig;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
gen_pulse_chan_logic : for i in 0 to g_nr_chans-1 generate
-- Synchronize the asynchronous trigger input into the 20 MHz clock
-- domain before passing it to the glitch filter
--
-- Reset value is '1' to avoid pulses being counted by pulse counter on
-- startup, when the board is in TTL-BAR repetition mode.
cmp_trig_sync : gc_sync_ffs
generic map
(
g_sync_edge => "positive"
)
port map
(
clk_i => clk_20_i,
rst_n_i => rst_20_n,
data_i => trig_a(i),
synced_o => trig_synced(i)
);
-- Deglitch synchronized trigger signal
--
-- Reset value is '1' to avoid pulses being counted by pulse counter on
-- startup, when the board is in TTL-BAR repetition mode.
cmp_inp_glitch_filt : gc_glitch_filt
generic map
(
g_len => g_pgen_gf_len
)
port map
(
clk_i => clk_20_i,
rst_n_i => rst_20_n,
dat_i => trig_synced(i),
dat_o => trig_degl(i)
);
-- Now that we have a deglitched signal, generate the MUX to select between
-- deglitched and direct channel input
trig_chan(i) <= trig_a(i) when (gf_en_n_i = '1') else
trig_degl(i);
-- Now, sync this channel trigger signal before passing it to the counters
--
-- The pulse counter is triggered only by a pulse that actually makes it
-- to the pulse generator.
--
-- NOTE: glitch-filtered signal is also synced in 20MHz clock domain, but
-- another sync chain here avoids extra logic complication and shoudl have
-- no influence on the correctness of the pulse counter value
cmp_sync_ffs : gc_sync_ffs
port map
(
clk_i => clk_20_i,
rst_n_i => rst_20_n,
data_i => trig_chan(i),
ppulse_o => trig_chan_redge_p(i)
);
--------------------------------------------------------------------------------
gen_pulse_cnt : if (g_with_pulse_cnt = true) generate
-- First, the pulse counters for the used channes (up to g_nr_chans)
p_pulse_cnt : process (clk_20_i)
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
pulse_cnt(i) <= (others => '0');
elsif (ch_pcr_ld(i) = '1') then
pulse_cnt(i) <= unsigned(ch_pcr(i));
elsif (trig_chan_redge_p(i) = '1') then
pulse_cnt(i) <= pulse_cnt(i) + 1;
end if;
end if;
end process p_pulse_cnt;
--------------------------------------------------------------------------------
-- Connect pulse counter values for unused channels to all zeroes
gen_pulse_cnt_unused_chans : if (g_nr_chans < c_max_nr_chans) generate
pulse_cnt(c_max_nr_chans-1 downto g_nr_chans) <= (others => (others => '0'));
end generate gen_pulse_cnt_unused_chans;
--------------------------------------------------------------------------------
end generate gen_pulse_cnt;
--------------------------------------------------------------------------------
-- The trigger to the pulse generator is either manual OR from the channel input
trig_pgen(i) <= trig_chan(i) or trig_man(i);
-- Instantiate pulse generator block for the channel
cmp_pulse_gen : conv_pulse_gen
generic map
(
g_with_fixed_pwidth => g_pgen_fixed_width,
g_pwidth => g_pgen_pwidth,
g_duty_cycle_div => g_pgen_duty_cycle_div
)
port map
(
clk_i => clk_20_i,
rst_n_i => rst_20_n,
gf_en_n_i => gf_en_n_i,
en_i => '1',
trig_a_i => trig_pgen(i),
pulse_err_p_o => pmisse_p(i),
pulse_o => pulse_outp(i)
);
-- Process to flash pulse LED when a pulse is output
-- LED flash length: 26 ms
p_pulse_led : process (clk_20_i) is
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
pulse_outp_d0(i) <= '0';
pulse_outp_redge_p(i) <= '0';
led_pulse_cnt(i) <= (others => '0');
led_pulse(i) <= '0';
else
pulse_outp_d0(i) <= pulse_outp(i);
pulse_outp_redge_p(i) <= pulse_outp(i) and (not pulse_outp_d0(i));
case led_pulse(i) is
when '0' =>
if (pulse_outp_redge_p(i) = '1') then
led_pulse(i) <= '1';
end if;
when '1' =>
led_pulse_cnt(i) <= led_pulse_cnt(i) + 1;
if (led_pulse_cnt(i) = (led_pulse_cnt(i)'range => '1')) then
led_pulse(i) <= '0';
end if;
when others =>
led_pulse(i) <= '0';
end case;
end if;
end if;
end process p_pulse_led;
end generate gen_pulse_chan_logic;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
gen_pulse_timetag : if (g_with_pulse_timetag = true) generate
cmp_pulse_timetag : conv_pulse_timetag
generic map
(
-- Frequency in Hz of the clk_i signal
g_clk_rate => 125000000,
-- Number of repetition channels
g_nr_chan => g_nr_chans
)
port map
(
-- Clock and active-low reset
clk_i => clk_125,
rst_n_i => rst_125_n,
-- Asynchronous pulse input
pulse_a_i => trig_chan,
-- Time inputs from White Rabbit
wr_tm_cycles_i => (others => '0'),
wr_tm_tai_i => (others => '0'),
wr_tm_valid_i => '0',
-- Timing inputs from Wishbone-mapped registers
wb_tm_tai_l_i => tvlr,
wb_tm_tai_l_ld_i => tvlr_ld,
wb_tm_tai_h_i => tvhr,
wb_tm_tai_h_ld_i => tvhr_ld,
-- Timing outputs
tm_cycles_o => tm_cycles,
tm_tai_o => tm_tai,
tm_wrpres_o => buf_wrtag,
chan_p_o => buf_chan,
-- Ring buffer I/O
buf_wr_req_p_o => buf_wr_req_p
);
--------------------------------------------------------------------------------
gen_buf_chan : if (g_nr_chans = c_max_nr_chans) generate
buf_dat_in(c_max_nr_chans-1 downto 0) <= buf_chan;
end generate gen_buf_chan;
gen_buf_chan_unused_chans: if (g_nr_chans < c_max_nr_chans) generate
buf_dat_in(g_nr_chans-1 downto 0) <= buf_chan;
buf_dat_in(c_max_nr_chans-1 downto g_nr_chans) <= (others => '0');
end generate gen_buf_chan_unused_chans;
--------------------------------------------------------------------------------
buf_dat_in( 6) <= buf_wrtag;
buf_dat_in(34 downto 7) <= tm_cycles;
buf_dat_in(74 downto 35) <= tm_tai;
-- Instantiate the ring buffer
cmp_ring_buf : conv_ring_buf
generic map
(
g_data_width => c_tagbuff_data_width,
g_size => 128
)
port map
(
-- Clocks and reset
clk_rd_i => clk_20_i,
clk_wr_i => clk_125,
rst_n_a_i => rst_20_n,
-- Buffer inputs
buf_dat_i => buf_dat_in,
buf_rd_req_i => buf_rd_req_p,
buf_wr_req_i => buf_wr_req_p,
buf_clr_i => buf_clr_p,
-- Buffer outputs
buf_dat_o => buf_dat_out,
buf_full_o => buf_full,
buf_empty_o => buf_empty,
buf_count_o => buf_count
);
end generate gen_pulse_timetag;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Channel output assignments
pulse_o <= pulse_outp;
led_pulse_o <= led_pulse;
--============================================================================
-- I2C bridge logic
--============================================================================
-- Set the I2C address signal according to ELMA protocol [2]
i2c_addr <= "10" & vme_ga_i;
-- Instantiate I2C bridge component
--
-- FSM watchdog timeout timer:
-- * consider bit period of 30 us
-- * 10 bits / byte transfer => 300 us
-- * 40 bytes in one transfer => 12000 us
-- * clk_i period = 50 ns => g_fsm_wdt = 12000 us / 50 ns = 240000
-- * multiply by two for extra safety => g_fsm_wdt = 480000
-- * Time to watchdog timeout: 480000 * 50ns = 24 ms
cmp_i2c_bridge : wb_i2c_bridge
generic map
(
g_fsm_wdt => 480000
)
port map
(
-- Clock, reset
clk_i => clk_20_i,
rst_n_i => rst_20_n,
-- I2C lines
scl_i => scl_i,
scl_o => scl_o,
scl_en_o => scl_en_o,
sda_i => sda_i,
sda_o => sda_o,
sda_en_o => sda_en_o,
-- I2C address and status
i2c_addr_i => i2c_addr,
-- TIP and ERR outputs
tip_o => i2c_tip,
err_p_o => i2c_err_p,
wdto_p_o => i2c_wdto_p,
-- Wishbone master signals
wbm_stb_o => xbar_slave_in(0).stb,
wbm_cyc_o => xbar_slave_in(0).cyc,
wbm_sel_o => xbar_slave_in(0).sel,
wbm_we_o => xbar_slave_in(0).we,
wbm_dat_i => xbar_slave_out(0).dat,
wbm_dat_o => xbar_slave_in(0).dat,
wbm_adr_o => xbar_slave_in(0).adr,
wbm_ack_i => xbar_slave_out(0).ack,
wbm_rty_i => xbar_slave_out(0).rty,
wbm_err_i => xbar_slave_out(0).err
);
-- Process to blink the LED when an I2C transfer is in progress
-- blinks four times per transfer
-- blink width : 20 ms
-- blink period: 40 ms
p_i2c_blink : process(clk_20_i)
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
led_i2c_clkdiv <= (others => '0');
led_i2c_cnt <= (others => '0');
led_i2c <= '0';
led_i2c_blink <= '0';
else
case led_i2c_blink is
when '0' =>
led_i2c <= '0';
if (i2c_tip = '1') then
led_i2c_blink <= '1';
end if;
when '1' =>
led_i2c_clkdiv <= led_i2c_clkdiv + 1;
if (led_i2c_clkdiv = 399999) then
led_i2c_clkdiv <= (others => '0');
led_i2c_cnt <= led_i2c_cnt + 1;
led_i2c <= not led_i2c;
if (led_i2c_cnt = 7) then
led_i2c_cnt <= (others => '0');
led_i2c_blink <= '0';
end if;
end if;
when others =>
led_i2c_blink <= '0';
end case;
end if;
end if;
end process p_i2c_blink;
-- And set the I2C LED Output
led_i2c_o <= led_i2c;
-- Register for the I2C_WDTO bit in the SR, cleared by writing a '1'
p_sr_wdto_bit : process(clk_20_i)
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
i2c_wdto_bit <= '0';
elsif (i2c_wdto_p = '1') then
i2c_wdto_bit <= '1';
elsif (i2c_wdto_bit_rst_ld = '1') and (i2c_wdto_bit_rst = '1') then
i2c_wdto_bit <= '0';
end if;
end if;
end process p_sr_wdto_bit;
-- Register for the I2C_ERR bit in the SR
p_i2c_err_led : process(clk_20_i)
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
i2c_err_bit <= '0';
elsif (i2c_err_p = '1') then
i2c_err_bit <= '1';
elsif (i2c_err_bit_rst_ld = '1') and (i2c_err_bit_rst = '1') then
i2c_err_bit <= '0';
end if;
end if;
end process p_i2c_err_led;
-- Set the I2C err signal for the LED
led_i2c_err_o <= i2c_err_bit or i2c_wdto_bit;
--============================================================================
-- Instantiation and connection of the main Wishbone crossbar
--============================================================================
cmp_wb_crossbar : xwb_sdb_crossbar
generic map
(
g_num_masters => c_nr_masters,
g_num_slaves => c_nr_slaves,
g_registered => false,
g_wraparound => true,
g_layout => c_sdb_layout,
g_sdb_addr => c_addr_sdb
)
port map
(
clk_sys_i => clk_20_i,
rst_n_i => rst_20_n,
slave_i => xbar_slave_in,
slave_o => xbar_slave_out,
master_i => xbar_master_in,
master_o => xbar_master_out
);
--============================================================================
-- Converter board registers
--============================================================================
-- RTM lines combo
rtm_lines <= rtmp_i & rtmm_i;
--------------------------------------------------------------------------------
gen_line : if (g_nr_chans = c_max_nr_chans) generate
line_front <= line_front_i;
line_rear <= line_rear_i;
line_rear_fs <= line_rear_fs_i;
end generate gen_line;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
gen_line_unused_chans : if (g_nr_chans < c_max_nr_chans) generate
-- connect used lines
line_front(g_nr_chans-1 downto 0) <= line_front_i;
line_rear(g_nr_chans-1 downto 0) <= line_rear_i;
line_rear_fs(g_nr_chans-1 downto 0) <= line_rear_fs_i;
-- unused lines to zeroes
line_front(c_max_nr_chans-1 downto g_nr_chans) <= (others => '0');
line_rear(c_max_nr_chans-1 downto g_nr_chans) <= (others => '0');
line_rear_fs(c_max_nr_chans-1 downto g_nr_chans) <= (others => '0');
end generate gen_line_unused_chans;
--------------------------------------------------------------------------------
-- Implement the RST_UNLOCK bit
p_rst_unlock : process (clk_20_i)
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
rst_unlock <= '0';
elsif (rst_unlock_bit_ld = '1') then
if (rst_unlock_bit = '1') then
rst_unlock <= '1';
else
rst_unlock <= '0';
end if;
end if;
end if;
end process p_rst_unlock;
-- Implement the reset bit register
-- The register can only be set when the RST_UNLOCK bit is '1'.
p_rst_fr_reg : process (clk_20_i)
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
rst_fr_reg <= '0';
elsif (rst_bit_ld = '1') and (rst_bit = '1') and (rst_unlock = '1') then
rst_fr_reg <= '1';
else
rst_fr_reg <= '0';
end if;
end if;
end process p_rst_fr_reg;
-- Register for the PMISSE bits in the SR, set when a channel misses a pulse
-- Each bit is cleared by writing a '1' to it
p_sr_pmisse_bit : process (clk_20_i)
begin
if rising_edge(clk_20_i) then
for i in 0 to g_nr_chans-1 loop
if (rst_20_n = '0') then
pmisse_bit(i) <= '0';
elsif (pmisse_p(i) = '1') then
pmisse_bit(i) <= '1';
elsif (pmisse_bit_rst_ld = '1') and (pmisse_bit_rst(i) = '1') then
pmisse_bit(i) <= '0';
end if;
end loop;
end if;
end process p_sr_pmisse_bit;
--------------------------------------------------------------------------------
-- Set the rest of the PMISSE bits to zero when g_nr_chans < c_max_nr_chans
gen_pmisse_unused_chans : if (g_nr_chans < c_max_nr_chans) generate
pmisse_bit(c_max_nr_chans-1 downto g_nr_chans) <= (others => '0');
end generate;
--------------------------------------------------------------------------------
-- Synchronize WR valid signal to implement the WRPRES bit
cmp_wrpres_sync : gc_sync_ffs
generic map
(
g_sync_edge => "positive"
)
port map
(
clk_i => clk_20_i,
rst_n_i => rst_20_n,
data_i => buf_wrtag,
synced_o => wrpres
);
-- Implement the TBCSR.CLR bit
p_tbcsr_clr : process (clk_20_i)
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
buf_clr_p <= '0';
else
buf_clr_p <= '0';
if (buf_clr_bit_ld = '1') and (buf_clr_bit = '1') then
buf_clr_p <= '1';
end if;
end if;
end if;
end process p_tbcsr_clr;
-- Implement the latest timestamp registers
-- NOTE: Updated in the 125 MHz clock domain
p_latest_timestamp : process (clk_125)
begin
if rising_edge(clk_125) then
for i in 0 to g_nr_chans-1 loop
if (rst_125_n = '0') then
latest_timestamp_cycles(i) <= (others => '0');
latest_timestamp_tai(i) <= (others => '0');
latest_timestamp_wrtag(i) <= '0';
elsif (buf_chan(i) = '1') then
latest_timestamp_cycles(i) <= tm_cycles;
latest_timestamp_tai(i) <= tm_tai;
latest_timestamp_wrtag(i) <= buf_wrtag;
end if;
end loop;
end if;
end process p_latest_timestamp;
--------------------------------------------------------------------------------
-- Connect unused timestamps to all zeroes
gen_latest_timestamp_unused_chans : if (g_nr_chans < c_max_nr_chans) generate
latest_timestamp_cycles(c_max_nr_chans-1 downto g_nr_chans) <= (others => (others => '0'));
latest_timestamp_tai(c_max_nr_chans-1 downto g_nr_chans) <= (others => (others => '0'));
latest_timestamp_tai(c_max_nr_chans-1 downto g_nr_chans) <= (others => (others => '0'));
end generate gen_latest_timestamp_unused_chans;
--------------------------------------------------------------------------------
-- Then, instantiate the component
cmp_conv_regs : conv_regs
port map (
rst_n_i => rst_20_n,
clk_sys_i => clk_20_i,
wb_adr_i => xbar_master_out(c_slv_conv_regs).adr(7 downto 2),
wb_dat_i => xbar_master_out(c_slv_conv_regs).dat,
wb_dat_o => xbar_master_in (c_slv_conv_regs).dat,
wb_cyc_i => xbar_master_out(c_slv_conv_regs).cyc,
wb_sel_i => xbar_master_out(c_slv_conv_regs).sel,
wb_stb_i => xbar_master_out(c_slv_conv_regs).stb,
wb_we_i => xbar_master_out(c_slv_conv_regs).we,
wb_ack_o => xbar_master_in (c_slv_conv_regs).ack,
wb_stall_o => xbar_master_in (c_slv_conv_regs).stall,
reg_bidr_i => g_board_id,
reg_sr_gwvers_i => g_gwvers,
reg_sr_switches_i => sw_gp_i,
reg_sr_rtm_i => rtm_lines,
reg_sr_i2c_wdto_o => i2c_wdto_bit_rst,
reg_sr_i2c_wdto_i => i2c_wdto_bit,
reg_sr_i2c_wdto_load_o => i2c_wdto_bit_rst_ld,
reg_sr_wrpres_i => wrpres,
reg_sr_i2c_err_o => i2c_err_bit_rst,
reg_sr_i2c_err_i => i2c_err_bit,
reg_sr_i2c_err_load_o => i2c_err_bit_rst_ld,
reg_sr_pmisse_o => pmisse_bit_rst,
reg_sr_pmisse_i => pmisse_bit,
reg_sr_pmisse_load_o => pmisse_bit_rst_ld,
reg_cr_rst_unlock_o => rst_unlock_bit,
reg_cr_rst_unlock_i => rst_unlock,
reg_cr_rst_unlock_load_o => rst_unlock_bit_ld,
reg_cr_rst_o => rst_bit,
reg_cr_rst_i => rst_fr_reg,
reg_cr_rst_load_o => rst_bit_ld,
reg_cr_mpt_o => mpt,
reg_cr_mpt_wr_o => mpt_ld,
reg_ch1pcr_o => ch_pcr(0),
reg_ch1pcr_i => std_logic_vector(pulse_cnt(0)),
reg_ch1pcr_load_o => ch_pcr_ld(0),
reg_ch2pcr_o => ch_pcr(1),
reg_ch2pcr_i => std_logic_vector(pulse_cnt(1)),
reg_ch2pcr_load_o => ch_pcr_ld(1),
reg_ch3pcr_o => ch_pcr(2),
reg_ch3pcr_i => std_logic_vector(pulse_cnt(2)),
reg_ch3pcr_load_o => ch_pcr_ld(2),
reg_ch4pcr_o => ch_pcr(3),
reg_ch4pcr_i => std_logic_vector(pulse_cnt(3)),
reg_ch4pcr_load_o => ch_pcr_ld(3),
reg_ch5pcr_o => ch_pcr(4),
reg_ch5pcr_i => std_logic_vector(pulse_cnt(4)),
reg_ch5pcr_load_o => ch_pcr_ld(4),
reg_ch6pcr_o => ch_pcr(5),
reg_ch6pcr_i => std_logic_vector(pulse_cnt(5)),
reg_ch6pcr_load_o => ch_pcr_ld(5),
reg_tvlr_o => tvlr,
reg_tvlr_i => tm_tai(31 downto 0),
reg_tvlr_load_o => tvlr_ld,
reg_tvhr_o => tvhr,
reg_tvhr_i => tm_tai(39 downto 32),
reg_tvhr_load_o => tvhr_ld,
reg_tbmr_chan_i => buf_dat_out( 5 downto 0),
reg_tbmr_wrtag_i => buf_dat_out( 6),
reg_tb_rd_req_p_o => buf_rd_req_p,
reg_tbcyr_i => buf_dat_out(34 downto 7),
reg_tbtlr_i => buf_dat_out(66 downto 35),
reg_tbthr_i => buf_dat_out(74 downto 67),
reg_tbcsr_clr_o => buf_clr_bit,
reg_tbcsr_clr_i => '0',
reg_tbcsr_clr_load_o => buf_clr_bit_ld,
reg_tbcsr_usedw_i => buf_count,
reg_tbcsr_full_i => buf_full,
reg_tbcsr_empty_i => buf_empty,
reg_ch1ltscyr_i => latest_timestamp_cycles(0),
reg_ch1ltstlr_i => latest_timestamp_tai(0)(31 downto 0),
reg_ch1ltsthr_tai_i => latest_timestamp_tai(0)(39 downto 32),
reg_ch1ltsthr_wrtag_i => latest_timestamp_wrtag(0),
reg_ch2ltscyr_i => latest_timestamp_cycles(1),
reg_ch2ltstlr_i => latest_timestamp_tai(1)(31 downto 0),
reg_ch2ltsthr_tai_i => latest_timestamp_tai(1)(39 downto 32),
reg_ch2ltsthr_wrtag_i => latest_timestamp_wrtag(1),
reg_ch3ltscyr_i => latest_timestamp_cycles(2),
reg_ch3ltstlr_i => latest_timestamp_tai(2)(31 downto 0),
reg_ch3ltsthr_tai_i => latest_timestamp_tai(2)(39 downto 32),
reg_ch3ltsthr_wrtag_i => latest_timestamp_wrtag(2),
reg_ch4ltscyr_i => latest_timestamp_cycles(3),
reg_ch4ltstlr_i => latest_timestamp_tai(3)(31 downto 0),
reg_ch4ltsthr_tai_i => latest_timestamp_tai(3)(39 downto 32),
reg_ch4ltsthr_wrtag_i => latest_timestamp_wrtag(3),
reg_ch5ltscyr_i => latest_timestamp_cycles(4),
reg_ch5ltstlr_i => latest_timestamp_tai(4)(31 downto 0),
reg_ch5ltsthr_tai_i => latest_timestamp_tai(4)(39 downto 32),
reg_ch5ltsthr_wrtag_i => latest_timestamp_wrtag(4),
reg_ch6ltscyr_i => latest_timestamp_cycles(5),
reg_ch6ltstlr_i => latest_timestamp_tai(5)(31 downto 0),
reg_ch6ltsthr_tai_i => latest_timestamp_tai(5)(39 downto 32),
reg_ch6ltsthr_wrtag_i => latest_timestamp_wrtag(5),
reg_lsr_front_i => line_front,
reg_lsr_frontinv_i => line_inv_i,
reg_lsr_rear_i => line_rear,
reg_lsr_rearfs_i => line_rear_fs,
reg_mswr_switches_i => sw_multicast_i
);
--============================================================================
-- Instantiate Xilinx MultiBoot module
--============================================================================
cmp_multiboot : xwb_xil_multiboot
port map
(
clk_i => clk_20_i,
rst_n_i => rst_20_n,
wbs_i => xbar_master_out(c_slv_multiboot),
wbs_o => xbar_master_in(c_slv_multiboot),
spi_cs_n_o => flash_cs_n_o,
spi_sclk_o => flash_sclk_o,
spi_mosi_o => flash_mosi_o,
spi_miso_i => flash_miso_i
);
--============================================================================
-- On-board DS18B20 Thermometer logic
--============================================================================
-- The one-wire master component is used to control the on-board DS18B20
-- thermometer
cmp_onewire_master : wb_onewire_master
generic map
(
g_interface_mode => CLASSIC,
g_address_granularity => WORD,
g_num_ports => 1,
g_ow_btp_normal => "5.0",
g_ow_btp_overdrive => "1.0"
)
port map
(
clk_sys_i => clk_20_i,
rst_n_i => rst_20_n,
wb_cyc_i => xbar_master_out(c_slv_onewire_mst).cyc,
wb_sel_i => xbar_master_out(c_slv_onewire_mst).sel,
wb_stb_i => xbar_master_out(c_slv_onewire_mst).stb,
wb_we_i => xbar_master_out(c_slv_onewire_mst).we,
wb_adr_i => xbar_master_out(c_slv_onewire_mst).adr(4 downto 2),
wb_dat_i => xbar_master_out(c_slv_onewire_mst).dat,
wb_dat_o => xbar_master_in(c_slv_onewire_mst).dat,
wb_ack_o => xbar_master_in(c_slv_onewire_mst).ack,
wb_int_o => open,
wb_stall_o => xbar_master_in(c_slv_onewire_mst).stall,
owr_pwren_o => open,
owr_en_o => owr_en,
owr_i => owr_in
);
-- Generate tri-state buffer for thermometer
thermometer_b <= '0' when (owr_en(0) = '1') else
'Z';
owr_in(0) <= thermometer_b;
--============================================================================
-- Bicolor LED matrix logic
--============================================================================
-- connect column, line & state signals outside
cmp_bicolor_led_ctrl : gc_bicolor_led_ctrl
generic map
(
g_NB_COLUMN => g_bicolor_led_columns,
g_NB_LINE => g_bicolor_led_lines,
g_clk_freq => 20000000,
g_refresh_rate => 250
)
port map
(
clk_i => clk_20_i,
rst_n_i => rst_20_n,
led_intensity_i => "1111111",
led_state_i => bicolor_led_state_i,
column_o => bicolor_led_col_o,
line_o => bicolor_led_line_o,
line_oen_o => bicolor_led_line_oen_o
);
--============================================================================
-- Drive unused outputs with safe values
--============================================================================
-- DAC outputs: enables to '1' (disable DAC comm interface) and SCK, DIN to '0'
dac20_sync_n_o <= '1';
dac20_din_o <= '0';
dac20_sclk_o <= '0';
dac125_sync_n_o <= '1';
dac125_din_o <= '0';
dac125_sclk_o <= '0';
-- SFP lines all open-drain, set to high-impedance
sfp_rate_select_o <= 'Z';
sfp_mod_def1_b <= 'Z';
sfp_mod_def2_b <= 'Z';
sfp_tx_disable_o <= 'Z';
end architecture arch;
--==============================================================================
-- architecture end
--==============================================================================
conv-common-gw-8e4921b9be26327b1138c5ec9cd50b8a11b69d89/top/conv_common_gw_pkg.vhd 0000664 0000000 0000000 00000064037 12375155472 0026520 0 ustar 00root root 0000000 0000000 --==============================================================================
-- CERN (BE-CO-HT)
-- Converter board common gateware package
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2014-08-01
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2014-08-01 Theodor Stana File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.genram_pkg.all;
package conv_common_gw_pkg is
--============================================================================
-- Constant declarations
--============================================================================
-- Convenience constant if changes need be made later
--
-- Note that if you change this constant you will make conv-common-gw
-- _incompatible_ with BLO and RS-485 pulse repeaters and you will need to
-- _reimplement_ the conv_regs module
constant c_max_nr_chans : natural := 6;
--============================================================================
-- Component declarations
--============================================================================
------------------------------------------------------------------------------
-- Top-level module
------------------------------------------------------------------------------
component conv_common_gw is
generic
(
-- Number of repeater channels
g_nr_chans : integer := 6;
-- Board ID -- 4-letter ASCII string indicating the board ID
-- see [1] for example
g_board_id : std_logic_vector(31 downto 0);
-- Gateware version
g_gwvers : std_logic_vector(7 downto 0);
-- Generate pulse repetition logic with fixed output pulse width
g_pgen_fixed_width : boolean;
-- Pulse width at pulse generator output (valid with fixed output pulse width)
g_pgen_pwidth : natural range 20 to 40 := 24;
-- Duty cycle divider ratio for pulse generator
-- output pulse will be limited to 1/g_pgen_duty_cycle_div
g_pgen_duty_cycle_div : natural := 5;
-- Pulse generator glitch filter length in number of clk_20_i cycles
g_pgen_gf_len : integer := 4;
-- Generate logic with pulse counters
g_with_pulse_cnt : boolean := false;
-- Generate logic with pulse counters
g_with_pulse_timetag : boolean := false;
-- Generate logic with manual trigger
g_with_man_trig : boolean := false;
g_man_trig_pwidth : integer := 24;
-- Generate one-wire master for thermometer
g_with_thermometer : boolean := false;
-- Bicolor LED controller signals
g_bicolor_led_columns : integer := 6;
g_bicolor_led_lines : integer := 2
);
port
(
-- Clocks
clk_20_i : in std_logic;
clk_125_p_i : in std_logic;
clk_125_n_i : in std_logic;
-- Reset output signal, synchronous to 20 MHz clock
rst_n_o : out std_logic;
-- Glitch filter active-low enable signal
gf_en_n_i : in std_logic;
-- Channel enable
global_ch_oen_o : out std_logic;
pulse_front_oen_o : out std_logic;
pulse_rear_oen_o : out std_logic;
inv_oen_o : out std_logic;
-- Pulse inputs
pulse_i : in std_logic_vector(g_nr_chans-1 downto 0);
pulse_o : out std_logic_vector(g_nr_chans-1 downto 0);
-- Channel leds
-- 26 ms active-high pulse on pulse_o rising edge
led_pulse_o : out std_logic_vector(g_nr_chans-1 downto 0);
-- I2C interface
scl_i : in std_logic;
scl_o : out std_logic;
scl_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
sda_en_o : out std_logic;
-- I2C LED signals -- conect to a bicolor LED of choice
-- led_i2c_o pulses four times on I2C transfer
-- led_i2c_err_o is high when either SR.I2C_ERR = '1' or SR.I2C_WDTO = '1'
led_i2c_o : out std_logic;
led_i2c_err_o : out std_logic;
-- VME interface
vme_sysreset_n_i : in std_logic;
vme_ga_i : in std_logic_vector(4 downto 0);
vme_gap_i : in std_logic;
-- SPI interface to on-board flash chip
flash_cs_n_o : out std_logic;
flash_sclk_o : out std_logic;
flash_mosi_o : out std_logic;
flash_miso_i : in std_logic;
-- PLL DACs
-- 20 MHz VCXO control
dac20_din_o : out std_logic;
dac20_sclk_o : out std_logic;
dac20_sync_n_o : out std_logic;
-- 125 MHz clock generator control
dac125_din_o : out std_logic;
dac125_sclk_o : out std_logic;
dac125_sync_n_o : out std_logic;
-- SFP lines
sfp_los_i : in std_logic;
sfp_mod_def0_i : in std_logic;
sfp_rate_select_o : out std_logic;
sfp_mod_def1_b : inout std_logic;
sfp_mod_def2_b : inout std_logic;
sfp_tx_disable_o : out std_logic;
sfp_tx_fault_i : in std_logic;
-- Switch inputs (for readout from converter status register)
sw_gp_i : in std_logic_vector(7 downto 0);
sw_multicast_i : in std_logic_vector(3 downto 0);
-- RTM lines
rtmm_i : in std_logic_vector(2 downto 0);
rtmp_i : in std_logic_vector(2 downto 0);
-- TTL, INV-TTL and rear-panel channel inputs, for reflection in line status register
line_front_i : in std_logic_vector(g_nr_chans-1 downto 0);
line_inv_i : in std_logic_vector(3 downto 0);
line_rear_i : in std_logic_vector(g_nr_chans-1 downto 0);
line_rear_fs_i : in std_logic_vector(g_nr_chans-1 downto 0);
-- Thermometer line
thermometer_b : inout std_logic;
-- Bicolor LED signals
bicolor_led_state_i : in std_logic_vector(2*g_bicolor_led_columns*g_bicolor_led_lines-1 downto 0);
bicolor_led_col_o : out std_logic_vector(g_bicolor_led_columns-1 downto 0);
bicolor_led_line_o : out std_logic_vector(g_bicolor_led_lines-1 downto 0);
bicolor_led_line_oen_o : out std_logic_vector(g_bicolor_led_lines-1 downto 0)
);
end component conv_common_gw;
------------------------------------------------------------------------------
-- Fixed-width reset generator
------------------------------------------------------------------------------
component conv_reset_gen is
generic
(
-- Reset time in number of clk_i cycles
g_reset_time : positive := 2_000_000
);
port
(
clk_i : in std_logic;
rst_i : in std_logic;
rst_n_o : out std_logic
);
end component conv_reset_gen;
------------------------------------------------------------------------------
-- Pulse generator with optional configurable pulse width
------------------------------------------------------------------------------
component conv_pulse_gen is
generic
(
-- This generic enables elaboration of the fixed pulse width logic
g_with_fixed_pwidth : boolean;
-- Pulse width, in number of clk_i cycles
-- Default pulse width (20 MHz clock): 1.2 us
-- Minimum allowable pulse width (20 MHz clock): 1 us
-- Maximum allowable pulse width (20 MHz clock): 2 us
g_pwidth : natural range 20 to 40 := 24;
-- Duty cycle divider: D = 1/g_duty_cycle_div
g_duty_cycle_div : natural := 5
);
port
(
-- Clock and active-low reset inputs
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Glitch filter enable input
-- '1' - Glitch filter disabled (glitch-sensitive, no output jitter)
-- '0' - Glitch filter enabled (glitch-insensitive, with output jitter)
gf_en_n_i : in std_logic;
-- Enable input, pulse generation is enabled when '1'
en_i : in std_logic;
-- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays.
trig_a_i : in std_logic;
-- Pulse error output, pulses high for one clock cycle when a pulse arrives
-- within a pulse period
pulse_err_p_o : out std_logic;
-- Pulse output, active-high
-- latency:
-- glitch filter disabled: none
-- glitch filter enabled: glitch filter length + 5 clk_i cycles
pulse_o : out std_logic
);
end component conv_pulse_gen;
------------------------------------------------------------------------------
-- Converter board control registers
------------------------------------------------------------------------------
component conv_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(5 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'ID register bits' in reg: 'BIDR'
reg_bidr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Gateware version' in reg: 'SR'
reg_sr_gwvers_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'Status of on-board switches' in reg: 'SR'
reg_sr_switches_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM detection lines~\cite{rtm-det}' in reg: 'SR'
reg_sr_rtm_i : in std_logic_vector(5 downto 0);
-- Ports for BIT field: 'I2C communication watchdog timeout error' in reg: 'SR'
reg_sr_i2c_wdto_o : out std_logic;
reg_sr_i2c_wdto_i : in std_logic;
reg_sr_i2c_wdto_load_o : out std_logic;
-- Port for BIT field: 'White Rabbit present' in reg: 'SR'
reg_sr_wrpres_i : in std_logic;
-- Ports for BIT field: 'I2C communication error' in reg: 'SR'
reg_sr_i2c_err_o : out std_logic;
reg_sr_i2c_err_i : in std_logic;
reg_sr_i2c_err_load_o : out std_logic;
-- Ports for BIT field: 'Pulse missed error' in reg: 'SR'
reg_sr_pmisse_o : out std_logic_vector(5 downto 0);
reg_sr_pmisse_i : in std_logic_vector(5 downto 0);
reg_sr_pmisse_load_o : out std_logic;
-- Ports for BIT field: 'Reset unlock bit' in reg: 'CR'
reg_cr_rst_unlock_o : out std_logic;
reg_cr_rst_unlock_i : in std_logic;
reg_cr_rst_unlock_load_o : out std_logic;
-- Ports for BIT field: 'Reset bit' in reg: 'CR'
reg_cr_rst_o : out std_logic;
reg_cr_rst_i : in std_logic;
reg_cr_rst_load_o : out std_logic;
-- Ports for PASS_THROUGH field: 'Manual Pulse Trigger' in reg: 'CR'
reg_cr_mpt_o : out std_logic_vector(7 downto 0);
reg_cr_mpt_wr_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH1PCR'
reg_ch1pcr_o : out std_logic_vector(31 downto 0);
reg_ch1pcr_i : in std_logic_vector(31 downto 0);
reg_ch1pcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH2PCR'
reg_ch2pcr_o : out std_logic_vector(31 downto 0);
reg_ch2pcr_i : in std_logic_vector(31 downto 0);
reg_ch2pcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH3PCR'
reg_ch3pcr_o : out std_logic_vector(31 downto 0);
reg_ch3pcr_i : in std_logic_vector(31 downto 0);
reg_ch3pcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH4PCR'
reg_ch4pcr_o : out std_logic_vector(31 downto 0);
reg_ch4pcr_i : in std_logic_vector(31 downto 0);
reg_ch4pcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH5PCR'
reg_ch5pcr_o : out std_logic_vector(31 downto 0);
reg_ch5pcr_i : in std_logic_vector(31 downto 0);
reg_ch5pcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Pulse counter value' in reg: 'CH6PCR'
reg_ch6pcr_o : out std_logic_vector(31 downto 0);
reg_ch6pcr_i : in std_logic_vector(31 downto 0);
reg_ch6pcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'TAI seconds counter bits 31..0' in reg: 'TVLR'
reg_tvlr_o : out std_logic_vector(31 downto 0);
reg_tvlr_i : in std_logic_vector(31 downto 0);
reg_tvlr_load_o : out std_logic;
-- Port for std_logic_vector field: 'TAI seconds counter bits 39..32' in reg: 'TVHR'
reg_tvhr_o : out std_logic_vector(7 downto 0);
reg_tvhr_i : in std_logic_vector(7 downto 0);
reg_tvhr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Channel mask' in reg: 'TBMR'
reg_tbmr_chan_i : in std_logic_vector(5 downto 0);
-- Port for BIT field: 'White Rabbit present' in reg: 'TBMR'
reg_tbmr_wrtag_i : in std_logic;
-- Tag buffer read request, asserted when reading from TBMR
reg_tb_rd_req_p_o : out std_logic;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'TBCYR'
reg_tbcyr_i : in std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'TBTLR'
reg_tbtlr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'TBTHR'
reg_tbthr_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'Buffer counter' in reg: 'TBCSR'
reg_tbcsr_usedw_i : in std_logic_vector(6 downto 0);
-- Port for BIT field: 'Buffer full' in reg: 'TBCSR'
reg_tbcsr_full_i : in std_logic;
-- Port for BIT field: 'Buffer empty' in reg: 'TBCSR'
reg_tbcsr_empty_i : in std_logic;
-- Ports for BIT field: 'Clear tag buffer' in reg: 'TBCSR'
reg_tbcsr_clr_o : out std_logic;
reg_tbcsr_clr_i : in std_logic;
reg_tbcsr_clr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH1LTSCYR'
reg_ch1ltscyr_i : in std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH1LTSTLR'
reg_ch1ltstlr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH1LTSTHR'
reg_ch1ltsthr_tai_i : in std_logic_vector(7 downto 0);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH1LTSTHR'
reg_ch1ltsthr_wrtag_i : in std_logic;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH2LTSCYR'
reg_ch2ltscyr_i : in std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH2LTSTLR'
reg_ch2ltstlr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH2LTSTHR'
reg_ch2ltsthr_tai_i : in std_logic_vector(7 downto 0);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH2LTSTHR'
reg_ch2ltsthr_wrtag_i : in std_logic;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH3LTSCYR'
reg_ch3ltscyr_i : in std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH3LTSTLR'
reg_ch3ltstlr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH3LTSTHR'
reg_ch3ltsthr_tai_i : in std_logic_vector(7 downto 0);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH3LTSTHR'
reg_ch3ltsthr_wrtag_i : in std_logic;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH4LTSCYR'
reg_ch4ltscyr_i : in std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH4LTSTLR'
reg_ch4ltstlr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH4LTSTHR'
reg_ch4ltsthr_tai_i : in std_logic_vector(7 downto 0);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH4LTSTHR'
reg_ch4ltsthr_wrtag_i : in std_logic;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH5LTSCYR'
reg_ch5ltscyr_i : in std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH5LTSTLR'
reg_ch5ltstlr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH5LTSTHR'
reg_ch5ltsthr_tai_i : in std_logic_vector(7 downto 0);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH5LTSTHR'
reg_ch5ltsthr_wrtag_i : in std_logic;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH6LTSCYR'
reg_ch6ltscyr_i : in std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH6LTSTLR'
reg_ch6ltstlr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH6LTSTHR'
reg_ch6ltsthr_tai_i : in std_logic_vector(7 downto 0);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH6LTSTHR'
reg_ch6ltsthr_wrtag_i : in std_logic;
-- Port for std_logic_vector field: 'Front panel channel input state' in reg: 'LSR'
reg_lsr_front_i : in std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Front panel INV-TTL input state' in reg: 'LSR'
reg_lsr_frontinv_i : in std_logic_vector(3 downto 0);
-- Port for std_logic_vector field: 'Rear panel input state' in reg: 'LSR'
reg_lsr_rear_i : in std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Input failsafe state' in reg: 'LSR'
reg_lsr_rearfs_i : in std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Multicast address (from switch)' in reg: 'MSWR'
reg_mswr_switches_i : in std_logic_vector(3 downto 0)
);
end component conv_regs;
-- Converter board registers SDB definition
constant c_conv_regs_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"3ab464e8", -- echo "conv_regs " | md5sum | cut -c1-8
version => x"00000001",
date => x"20140731",
name => "conv_regs ")));
------------------------------------------------------------------------------
-- Pulse time-tagging component
------------------------------------------------------------------------------
component conv_pulse_timetag is
generic
(
-- Frequency in Hz of the clk_i signal
g_clk_rate : positive := 125000000;
-- Number of repetition channels
g_nr_chan : positive := 6
);
port
(
-- Clock and active-low reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Asynchronous pulse input
pulse_a_i : in std_logic_vector(g_nr_chan-1 downto 0);
-- Time inputs from White Rabbit
wr_tm_cycles_i : in std_logic_vector(27 downto 0);
wr_tm_tai_i : in std_logic_vector(39 downto 0);
wr_tm_valid_i : in std_logic;
-- Timing inputs from Wishbone-mapped registers
wb_tm_tai_l_i : in std_logic_vector(31 downto 0);
wb_tm_tai_l_ld_i : in std_logic;
wb_tm_tai_h_i : in std_logic_vector( 7 downto 0);
wb_tm_tai_h_ld_i : in std_logic;
-- Timing outputs
tm_cycles_o : out std_logic_vector(27 downto 0);
tm_tai_o : out std_logic_vector(39 downto 0);
tm_wrpres_o : out std_logic;
chan_p_o : out std_logic_vector(g_nr_chan-1 downto 0);
-- Ring buffer I/O
buf_wr_req_p_o : out std_logic
);
end component conv_pulse_timetag;
------------------------------------------------------------------------------
-- Ring buffer component
-- use: buffer time stamps generated by the conv_pulse_timetag component
------------------------------------------------------------------------------
component conv_ring_buf is
generic
(
g_data_width : positive;
g_size : positive
);
port
(
-- Clocks and reset
clk_rd_i : in std_logic;
clk_wr_i : in std_logic;
rst_n_a_i : in std_logic;
-- Buffer inputs
buf_dat_i : in std_logic_vector(g_data_width-1 downto 0);
buf_rd_req_i : in std_logic;
buf_wr_req_i : in std_logic;
buf_clr_i : in std_logic;
-- Buffer outputs
buf_dat_o : out std_logic_vector(g_data_width-1 downto 0);
buf_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
buf_full_o : out std_logic;
buf_empty_o : out std_logic
);
end component conv_ring_buf;
------------------------------------------------------------------------------
-- Manual trigger component
------------------------------------------------------------------------------
component conv_man_trig is
generic
(
-- Number of conversion channels
g_nr_chan : positive := 6;
-- Length of pulse in clk_i cycles generated at trig_o output
g_pwidth : positive := 1
);
port
(
-- Clock, active-low inputs
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Control inputs from conv_regs
reg_ld_i : in std_logic;
reg_i : in std_logic_vector(7 downto 0);
-- Trigger output, g_pwidth long
trig_o : out std_logic_vector(g_nr_chan downto 1)
);
end component conv_man_trig;
end package conv_common_gw_pkg;