pax_global_header 0000666 0000000 0000000 00000000064 13055247455 0014524 g ustar 00root root 0000000 0000000 52 comment=4b29f81745c3c0a760395b21be78b872bfc85060
conv-common-gw-4b29f81745c3c0a760395b21be78b872bfc85060/ 0000775 0000000 0000000 00000000000 13055247455 0021157 5 ustar 00root root 0000000 0000000 conv-common-gw-4b29f81745c3c0a760395b21be78b872bfc85060/.gitmodules 0000664 0000000 0000000 00000000167 13055247455 0023340 0 ustar 00root root 0000000 0000000 [submodule "ip_cores/general-cores"]
path = ip_cores/general-cores
url = git@ohwr.org:hdl-core-lib/general-cores.git
conv-common-gw-4b29f81745c3c0a760395b21be78b872bfc85060/Manifest.py 0000664 0000000 0000000 00000000047 13055247455 0023300 0 ustar 00root root 0000000 0000000 modules = {
"local" : [ "top" ]
}
conv-common-gw-4b29f81745c3c0a760395b21be78b872bfc85060/README 0000664 0000000 0000000 00000000065 13055247455 0022040 0 ustar 00root root 0000000 0000000 Generic common gateware for converter board projects
conv-common-gw-4b29f81745c3c0a760395b21be78b872bfc85060/doc/ 0000775 0000000 0000000 00000000000 13055247455 0021724 5 ustar 00root root 0000000 0000000 conv-common-gw-4b29f81745c3c0a760395b21be78b872bfc85060/doc/Makefile 0000664 0000000 0000000 00000000602 13055247455 0023362 0 ustar 00root root 0000000 0000000 FILE=conv-common-gw
all:
$(MAKE) -C fig
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
bibtex $(FILE).aux
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
pdflatex -synctex=1 -interaction=nonstopmode $(FILE).tex *.tex
evince $(FILE).pdf &
clean:
$(MAKE) -C fig clean
rm -rf *.aux *.dvi *.log $(FILE).pdf *.lof *.lot *.out *.toc *.bbl *.blg *.gz
conv-common-gw-4b29f81745c3c0a760395b21be78b872bfc85060/doc/README.txt 0000664 0000000 0000000 00000000205 13055247455 0023417 0 ustar 00root root 0000000 0000000 Type 'make' to create your .pdf documentation file.
You need Inkscape to make the documentation files:
sudo apt-get install inkscape conv-common-gw-4b29f81745c3c0a760395b21be78b872bfc85060/doc/cern-title.tex 0000664 0000000 0000000 00000001417 13055247455 0024517 0 ustar 00root root 0000000 0000000 \begin{titlepage}
\vspace*{3cm}
%---------------------------------------------------------------
% name
%---------------------------------------------------------------
\noindent{\LARGE \textbf{Converter board common gateware}}
\noindent \rule{\textwidth}{.1cm}
\hfill 17 February 2017
\vspace*{3cm}
\begin{figure}[h]
\includegraphics[height=3cm]{fig/cern-logo}
\hfill
\includegraphics[height=3cm]{fig/ohwr-logo}
\end{figure}
\vfill
%---------------------------------------------------------------
% name
%---------------------------------------------------------------
\noindent {\Large \textbf{Theodor-Adrian Stana (CERN/BE-CO-HT)}}\\
\noindent {Last modified by \textit{Denia Bouhired-Ferrag (CERN/BE-CO-HT)}}\\
\noindent \rule{\textwidth}{.05cm}
\end{titlepage}
conv-common-gw-4b29f81745c3c0a760395b21be78b872bfc85060/doc/conv-common-gw.bib 0000664 0000000 0000000 00000005343 13055247455 0025255 0 ustar 00root root 0000000 0000000 @misc{conv-common-gw-wiki,
title = {{Converter Common Gateware Wiki page on OHWR}},
howpublished = {\url{http://www.ohwr.org/projects/conv-common-gw/wiki}}
}
@misc{coding-guidelines,
author = "Patrick Loschmidt and Nata{\v s}a Simani\'c and C\'esar Prados and Pablo Alvarez and Javier Serrano",
title = {{Guidelines for VHDL Coding}},
month = 04,
year = 2011,
note = {\url{http://www.ohwr.org/documents/24}}
}
@misc{level-conversion,
title = {{Level Conversion Circuits}},
note = {\url{http://www.ohwr.org/projects/level-conversion/wiki}}
}
@misc{conv-common-gw-git,
title = {{Repository for converter board common gateware}},
note = {\url{http://www.ohwr.org/projects/conv-common-gw/repository}}
}
@misc{bib:doulos-counter,
title = {{Repository for converter board common gateware}},
note = {\url{https://www.doulos.com/knowhow/fpga/fastcounter/}}
}
@misc{board-id,
title = {{A counter for fast events, using a Flancter}},
note = {\url{http://www.ohwr.org/projects/conv-common-gw/wiki/Board-id}}
}
@misc{conv-ttl-blo-ohwr,
title = {{Conv TTL Blocking Project Page on OHWR}},
howpublished = {\url{http://www.ohwr.org/projects/conv-ttl-blo}}
}
@misc{conv-ttl-rs485-ohwr,
title = {{Conv TTL Blocking Project Page on OHWR}},
howpublished = {\url{http://www.ohwr.org/projects/conv-ttl-rs485}}
}
@misc{sdb,
title = {{SDB specification v1.1}},
howpublished = {\url{http://www.ohwr.org/documents/256}}
}
@misc{gencores-ohwr,
title = {{Platform-independent Core Collection webage on Open Hardware Repository}},
howpublished = {\url{http://www.ohwr.org/projects/general-cores/wiki}}
}
@misc{rtm-det,
title = {{Rear Transition Module detection}},
howpublished = {\url{http://www.ohwr.org/projects/conv-ttl-blo/wiki/RTM_board_detection}}
}
@misc{blocking,
author = "C. Gil Soriano",
title = {{Standard Blocking Output Signal Definition for CTDAH board}},
month = sep,
year = 2011,
note = {\url{http://www.ohwr.org/documents/109}}
}
@misc{ug380,
title = {{UG380 - Spartan-6 Configuration Guide}},
author = {Xilinx},
month = jan,
year = {2013},
note = {v2.5},
howpublished = {\url{http://www.xilinx.com/support/documentation/user_guides/ug380.pdf}}
}
@misc{onewire-core,
author = {Iztok Jeras},
title = {{sockit\_owm, 1-wire (onewire) master}},
year = 2011,
note = {\url{http://opencores.org/websvn,filedetails?repname=sockit_owm&path=%2Fsockit_owm%2Ftrunk%2Fdoc%2Fsockit_owr.pdf}}
}
@misc{ds18b20,
author = {{Maxim Integrated}},
title = {{DS18B20 -- Programmable Resolution 1-Wire Digital Thermometer}},
note = {\url{http://datasheets.maximintegrated.com/en/ds/DS18B20.pdf}}
}
@misc{wbgen2,
title = {{Wishbone Slave Generator}},
howpublished = {\url{http://www.ohwr.org/projects/wishbone-gen/wiki}}
}
conv-common-gw-4b29f81745c3c0a760395b21be78b872bfc85060/doc/conv-common-gw.tex 0000664 0000000 0000000 00000125375 13055247455 0025331 0 ustar 00root root 0000000 0000000 %==============================================================================
% Document header
%==============================================================================
\documentclass[a4paper,11pt]{article}
% Color package
\usepackage[usenames,dvipsnames,table]{xcolor}
% Hyperrefs
\usepackage[
colorlinks = true,
linkcolor = black,
citecolor = black,
urlcolor = blue,
]{hyperref}
% Longtable
\usepackage{longtable}
% Graphics, multirow
\usepackage{graphicx}
\usepackage{multirow}
% Appendix package
\usepackage[toc,page]{appendix}
\usepackage{fancyhdr}
\setlength{\headheight}{15.2pt}
\pagestyle{fancy}
\fancyhead[L]{\nouppercase{\leftmark}}
\fancyhead[R]{}
\renewcommand{\footrulewidth}{0.4pt}
% Row number command
\newcounter{rownr}
\newcommand{\rownumber}{\stepcounter{rownr}\arabic{rownr}}
%==============================================================================
% Start of document
%==============================================================================
\begin{document}
%------------------------------------------------------------------------------
% Title
%------------------------------------------------------------------------------
\include{cern-title}
%------------------------------------------------------------------------------
% Revision history
%------------------------------------------------------------------------------
\pagebreak
\addcontentsline{toc}{section}{Revision history}
\section*{Revision history}
\centerline
{
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l c p{.6\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Date}} & \multicolumn{1}{c}{\textbf{Version}} & \multicolumn{1}{c}{\textbf{Change}} \\
\hline
05-08-2014 & 0.1 & First draft \\
12-08-2014 & 1.0 & First release \\
29-08-2014 & 2.0 & Added sections for input pulse counters, time-tagging,
manual pulse triggering, one-wire thermometer module, the switches
on the converter boards, and changed and corrected some wording \\
\hline
\end{tabular}
}
%------------------------------------------------------------------------------
% List of figs, tables
%------------------------------------------------------------------------------
\pagebreak
\pdfbookmark[1]{\contentsname}{toc}
\tableofcontents
\listoffigures
\listoftables
%------------------------------------------------------------------------------
% List of abbreviations
%------------------------------------------------------------------------------
\pagebreak
\section*{List of Abbreviations}
\begin{tabular}{l l}
CR & Control Register \\
FPGA & Field-Programmable Gate Array \\
LSR & Line Status Register \\
MSWR & Multicast Switch Register \\
SR & Status Register \\
WRPC & White Rabbit PTP Core \\
\end{tabular}
\addcontentsline{toc}{section}{List of abbreviations}
%==============================================================================
% SEC: Intro
%==============================================================================
\pagebreak
\section{Introduction}
\label{sec:intro}
This document presents the common gateware for converter board projects~\cite{level-conversion}.
This gateware, mainly written in VHDL, is a grouping of modules common to all converter board projects.
A synthesized version thereof is intended to be downloaded to the FPGA on the converter board.
No specific FPGA is assumed for the converter boards, therefore the VHDL code is as generic as possible.
However, some details about the way that the boards are designed in the Hardware \& Timing section at CERN
are assumed, and these details are described throughout the document.
The document will start with a summary of the VHDL entity's ports, continue with presenting
a top-level diagram of the gateware, followed by a high-level description of each module in the gateware.
More involved details can be obtained by consulting the code itself, which can be freely obtained (including
the \textit{general-cores}) submodule from the \textit{git} repository~\cite{conv-common-gw-git} using the
following commands:
\begin{small}
\begin{verbatim}
git clone git://ohwr.org/level-conversion/conv-common-gw.git
git submodule init
git submodule update
\end{verbatim}
\end{small}
%==============================================================================
% SEC: Instantiation
%==============================================================================
\pagebreak
\section{Instantiation}
\label{sec:instantiation}
To use the common gateware, the designer should instantiate the module \textit{conv\_common\_gw},
which is part of the repository and contains all sub-modules required to implement
the pulse repetition functionality.
A corresponding VHDL component declaration can be found in the associated package file
(\textit{conv\_common\_gw\_pkg.vhd}), which needs to be imported into the file of the
instantiating module.
Port names follow the OHWR coding style guide~\cite{coding-guidelines}. Except for few cases,
the module uses active-high ports, any adaptations to active-low logic must be made in external logic.
Since there are a lot of ports in the component, listing them all here would be a waste of space.
The reader is referred to the package file or the source file directly, where each port declaration
is commented. Projects where this gateware is already used can also be a good source of
reference (see the \textit{conv-common-gw} project Wiki page~\cite{conv-common-gw-wiki}).
%==============================================================================
% SEC: Top-level diagram
%==============================================================================
\pagebreak
\section{Overview}
\label{sec:overview}
The common gateware comprises various modules, as shown in Figure~\ref{fig:block-diagram}.
The channel logic, presented in Section~\ref{sec:chan-logic}, is multiplied \textit{g\_nr\_chans} times.
Its status and select functionality can be controlled via the controller board
registers (Section~\ref{subsec:conv-regs}), which are part of a Wishbone memory-mapped
peripheral. This peripheral, along with the rest of the memory-mapped peripherals on converter boards,
is accessible through an I$^2$C interface, and an I$^2$C to Wishbone bridge performs
the conversion between the two interfaces.
\begin{figure}[h]
\centerline{\includegraphics[width=1.1\textwidth]{fig/block-diagram}}
\caption{\label{fig:block-diagram} Block diagram of common gateware}
\end{figure}
%------------------------------------------------------------------------------
% SUBSEC: Switches
%------------------------------------------------------------------------------
\subsection{Switches on converter boards}
Various converter boards may use various switches, so a convention should be made
about switch names and locations.
The CONV-TTL-BLO~\cite{conv-ttl-blo-ohwr}, which is the first converter project using
an FPGA, had eight switches which we called \textit{general-purpose switches}. These
appear on the CONV-TTL-RS485~\cite{conv-ttl-rs485-ohwr} as well. It is recommended to add
general-purpose switches on all converter boards in a similar manner to the two projects
mentioned above.
Additionally, the RS-485 pulse repeater adds four other switches, which are called MultiCast switches
and despite their seemingly dedicated name, they are also general-purpose switches at the
time of writing of this document. Therefore, they are considered as \textit{other switches},
due to the fact they do not appear on the CONV-TTL-BLO.
The state of the general-purpose switches can be read from the status register
(SR -- see Appendix~\ref{app:conv-regs-SR}), and the state of the MultiCast
switches can be read from the other switches register (OSWR -- see Appendix~\ref{app:conv-regs-OSWR}).
A total of 32 dedicated switches can be implemented on converter boards and mapped to the OSWR, should
they be required. This number-of-32 constraint is imposed by the number of bits in the OSWR.
Table~\ref{tbl:switches} summarizes the switches on converter boards.
\begin{table}[ht]
\caption{\label{tbl:switches} Switches on converter boards}
\rowcolors{2}{white}{gray!25}
\centerline {
\begin{tabular}{l p{.7\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Name}} & \multicolumn{1}{c}{\textbf{Comments}} \\
\hline
General-purpose & Eight switches that \textit{should} be implemented on all converter boards.
Read their state from the SR.SWITCHES field (see Appendix~\ref{app:conv-regs-SR}) \\
Other & Dedicated switches for specific converter boards.
y Read their state from the OSWR register
(see Appendix~\ref{app:conv-regs-OSWR}) \\
\hline
\end{tabular}
}
\end{table}
%==============================================================================
% SEC: Clocking
%==============================================================================
\pagebreak
\section{Clocks}
\label{sec:clocks}
There are two clock signals input to the FPGA (Figure~\ref{fig:clocks}).
The first is a 20~MHz signal from a VCXO. The second clock signal with a frequency
of 125~MHz is generated on-board via a Texas Instruments PLL IC from a 25~MHz VCXO.
Two DACs are provided on-board for controlling the two VCXOs. The DACs can be
controlled via SPI, and if White Rabbit is available, the White Rabbit PTP Core (WRPC)
can control these DACs to discipline these clocks.
Table~\ref{tbl:clocks} lists the clock domains used in the gateware.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/clocks}}
\caption{FPGA clock inputs}
\label{fig:clocks}
\end{figure}
\begin{table}[h]
\caption{\label{tbl:clocks} Clock domains}
\rowcolors{2}{white}{gray!25}
\centerline
{
\begin{tabular}{c c p{.6\textwidth}}
\hline
\textbf{Clock domain} & \textbf{Frequency} & \multicolumn{1}{c}{\textbf{Comments}} \\
\hline
\textit{clk\_20\_i} & 20~MHz & Clock input to most of the sequential logic \\
\textit{clk\_125} & 125~MHz & Time-tagging logic and WR reference clock \\
\hline
\end{tabular}
}
\end{table}
%==============================================================================
% SEC: Reset
%==============================================================================
\pagebreak
\section{Reset}
\label{sec:reset}
An internal reset generator (\textit{conv\_reset\_gen}) is used to supply a reset pulse to the sequential
modules of the \textit{conv\_common\_gw}, so that they start up in a known state.
This reset pulse occurs either when the FPGA finishes configuration and goes into user mode, or when
an external reset is received. The external reset can come from one of two sources:
\begin{itemize}
\item the VME system reset pin
\item a write to the CR.RST bit, after having been previously unlocked by a write to the
CR.RST\_UNLOCK bit (see Appendix~\ref{app:conv-regs-CR})
\end{itemize}
The \textit{conv\_reset\_gen} component is clocked from \textit{clk\_20\_i}, so the reset
it generates is in the 20~MHz clock domain. This is also the reset that is present at the
\textit{rst\_n\_o} pin. A reset synchronized to the 125~MHz clock domain is generated
inside \textit{conv\_common\_gw}, but this is not provided at the output.
Note that the VHDL of this module is Xilinx and XST-specific and porting to a different
FPGA architecture or synthesis tool is not guaranteed to provide the same results.
The \textit{conv\_reset\_gen} module has an initial value set for the counter signal after
power-up, which is guaranteed by XST to be set after the FPGA's GSR signal is de-asserted.
By default, the reset time is set to 100~ms.
%==============================================================================
% SEC: Channel logic
%==============================================================================
\pagebreak
\section{Channel logic}
\label{sec:chan-logic}
The channel logic is presented in Figure~\ref{fig:chan-logic}. The central part
thereof is a pulse generator which can be configured for pass-through mode, or
fixed-width pulse generation with subsequent pulse rejection after a pulse has
been generated. The generator can be triggered in two ways:
\begin{itemize}
\item by the pulse input, which can be fed directly to the generator's input,
or optionally glitch filtered (the selection is done by means of a general-purpose
switch)
\item manually, through commands sent by a user via the I$^2$C and ultimately Wishbone bus
\end{itemize}
The output of this pulse generator triggers lighting a pulse LED,
apart from driving the pulse output of the module. Input pulses also trigger
the incrementing of a pulse counter, as well as the storage of a timestamp to a dedicated
FIFO memory.
\begin{figure}[h]
\centerline{\includegraphics[width=1.1\textwidth]{fig/chan-logic}}
\caption{\label{fig:chan-logic} Channel logic diagram}
\end{figure}
%------------------------------------------------------------------------------
\subsection{Output enable}
\label{subsec:oen}
%------------------------------------------------------------------------------
Converter board outputs have to be enabled prior to being used. Within the
\textit{conv\_common\_gw}, there are four output enables. Apart from the global
channel output enable, there are dedicated output enables for potential front
and rear panel connections (see the converter board's specific user guide for information
on front and rear panels).
To make sure that pulses are output only when the FPGA can handle them, the global
output enable is set only after the reset period is finished. The rest of the
output enables are set one clock cycle later. This in combination with the
rest of the circuitry outside the FPGA makes sure no glitches or erroneous pulses
are output during the internal reset period.
An example connection of the output enable signals on the CONV-TTL-RS485~\cite{conv-ttl-rs485-ohwr}
is shown in Figure~\ref{fig:outp-enable}.
\begin{figure}
\centerline{\includegraphics[width=\textwidth]{fig/outp-enable}}
\caption{\label{fig:outp-enable} Output enable example}
\end{figure}
%------------------------------------------------------------------------------
\subsection{Glitch filter}
\label{subsec:glitch-filt}
%------------------------------------------------------------------------------
The glitch filter input (\textit{gf\_en\_n\_i}) is intended to be enabled via one
of the general-purpose switches on the converter board when the environment where
the board is placed is hazardous and can potentially create harmful glitches on the
line. It is active-low, therefore a '0' on the pin enables the glitch filter.
The length of the glitch filter can be selected at top-level via the generic
\textit{g\_pgen\_glitch\_filt\_len}, which is in measures of \textit{clk\_20\_i} cycles.
For information on the module's implementation, consult its documentation in the
\textit{ip\_cores/general-cores/doc/} folder.
%------------------------------------------------------------------------------
\subsection{Pulse counter}
\label{subsec:pulse-cnt}
%------------------------------------------------------------------------------
Figure~\ref{fig:pulse-cnt} presents the implementation of the pulse counters.
When a pulse arrives on either the TTL or blocking side, it is resynchronized
in the 20~MHz clock domain and passed to a \textit{fast counter} module. Indeed, at high frequencies it was found that internal counters need to be able to cope with high frequency triggers howvwer short. A \textit{Flancter} based counter is therefore used~\cite{bib:doulos-counter}. When
a rising edge occurs on the pulse, the result of the counter is stored
to the channel pulse counter register. On v4 release of the gateware\footnotemark\footnotetext{On preceding releases, there was a single counter per channel, aggregating both types of pulses.}, there are two counters implemented separately for TTL
and BLO outputs of each channel (CHxTTLPCR and CHxBLOPCR -- see Appendix~\ref{app:conv-regs}).
Figure~\ref{fig:pulse-cnt} presents the implementation for the TTL case only, the same is duplicated for the
blocking counter.
The pulse counter register can be written via the \textit{conv\_regs} component as a
result of an I$^2$C write access to the register's address.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/pulse-cnt}}
\caption{Pulse counter implementation}
\label{fig:pulse-cnt}
\end{figure}
%------------------------------------------------------------------------------
\subsection{Time-tagging mechanism}
\label{subsec:pulse-timetag}
%------------------------------------------------------------------------------
The architecture of the pulse time-tagging mechanism is shown in Figure~\ref{fig:timetag-arch}.
The time-tagging mechanism is clocked from the 125~MHz clock domain. Input pulses trigger the storage
to a ring buffer of either internally-generated timestamps, or precise timestamps from the White
Rabbit network. Four tag buffer (TB*) registers point to the latest sample in the buffer and
allow for reading the buffer entirely. Since the ring buffer is shared between the channels, the latest timestamp
for a specific channel is available in the latest timestamp registers for the channel.
Finally, the current value of TAI time can be read from dedicated registers.
\begin{figure}[h]
\centerline{\includegraphics[width=1\textwidth]{fig/timetag-arch}}
\caption{\label{fig:timetag-arch} Pulse time-tagging architecture}
\end{figure}
%------------------------------------------------------------------------------
\subsubsection{Time-tagging controller}
\label{subsec:pulse-timetag-ctrl}
%------------------------------------------------------------------------------
The architecture of the time-tag controller is shown in Figure~\ref{fig:timetag-core}.
The time-tag controller contains two counters used for counting time
as well as logic for multiplexing between internally and externally generated timestamps.
The two counters implemented are:
\begin{itemize}
\item \textit{cycles counter} -- count the number of clock cycles to one second
\item \textit{TAI counter} -- count full seconds
\end{itemize}
The TAI counter can be loaded with a new value by writing the TVLR and TVHR registers
(see Appendix~\ref{app:conv-regs-TVLR} and~\ref{app:conv-regs-TVHR}). A load of either
of these registers will reset the internal cycles counter.
Note that due to the synchronization logic, rising edge detector and the latching of the
ORed pulse rising edge detection signal, a timestamp is stored to the time-tag buffer
two to three cycles after its actual arrival on the input (Figure~\ref{fig:timetag-delay}).
The same delay applies to the latest timestamp registers.
\pagebreak
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/timetag-core}}
\caption{\label{fig:timetag-core} Time-tagging controller architecture}
\vspace*{22pt}
\centerline{\includegraphics[width=.8\textwidth]{fig/timetag-delay}}
\caption{\label{fig:timetag-delay} Timestamp storage delay}
\end{figure}
%------------------------------------------------------------------------------
\subsubsection{Ring buffer}
\label{subsec:pulse-timetag-buf}
%------------------------------------------------------------------------------
The implementation of the ring buffer is shown in Figure~\ref{fig:timetag-ring-buf}.
A dual-clock asynchronous FIFO synchronizes data between the read and write clock domains.
Data from the FIFO is stored to the RAM clocked from the read clock domain.
\begin{figure}
\centerline{\includegraphics[width=.8\textwidth]{fig/timetag-ring-buf}}
\caption{Ring buffer implementation}
\label{fig:timetag-ring-buf}
\end{figure}
Figure~\ref{fig:timetag-buf-mech} shows the mechanics of the ring buffer, and helps
better understand the control logic. Note that by listing the converter board registers to
access, the figure is oriented towards converter board designs, but the ring buffer
component is usable in other designs as well.
In few words, the buffer read and write pointers
advance on read or write requests from the buffer. While a read can not be performed if the
buffer is empty, a write to a full buffer will start overwriting old timestamps.
For converter board designs, a caution should be put in place. Because the TBMR
register (see Appendix~\ref{app:conv-regs-TBMR}) causes the read pointer to advance,
it should be the last register read in a readout cycle. Otherwise, the values of the
other tag buffer registers will return the next sample in the tag buffer.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/timetag-buf-mech}}
\caption{\label{fig:timetag-buf-mech} Ring buffer mechanics}
\end{figure}
%------------------------------------------------------------------------------
\subsubsection{Synchronization issues}
\label{subsec:pulse-timetag-sync}
%------------------------------------------------------------------------------
Apart from the data coming from the faster clock domain into the slower clock domain, where
synchronization is handled by the FIFO insde the ring buffer component (see Figure~\ref{fig:timetag-ring-buf}),
there are three other places where synchronization may be a concern. These places are
shown in Figure~\ref{fig:timetag-sync}, along with the solution to the concern.
Note that although the TAI time signal is generated in the 125~MHz
clock domain, it is not synchronized before connection to the \textit{conv\_regs}.
This is because its rate of change of once per second is considered too slow to present
any problem of synchronization when read by the user.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/timetag-sync}}
\caption{\label{fig:timetag-sync} Synchronization in the time-tagging logic}
\end{figure}
%------------------------------------------------------------------------------
\subsection{Manual pulse triggering}
\label{subsec:man-trig}
%------------------------------------------------------------------------------
The manual pulse trigger module (\textit{conv\_man\_trig}) is implemented in the form
of a simple state machine, which is shown in Figure~\ref{fig:man-trig}. The module
is directly connected to the register load output of the \textit{conv\_regs} module,
and a register load signal from the latter triggers the FSM. If the value sent via
the register to the module are part of the expected value in the password, the FSM
advances. Otherwise, the FSM returns to the IDLE state and the sequence must be re-commenced.
The FSM waits in each state indefinitely for a value to be input.
\begin{figure}[h]
\centerline{\includegraphics[width=.7\textwidth]{fig/man-trig-fsm}}
\caption{\label{fig:man-trig} FSM of the manual pulse trigger module}
\end{figure}
%------------------------------------------------------------------------------
\subsection{Pulse generation and dynamic burst control}
For hardware v4 of the CONV-TTL-BLO in particular (CONV-TTL-RS485 boards outputs are not sensitive to repetition frequency), release 4 of the gateware includes a \textit{burst mode} capability. Pulses output from the (\textit{conv\_pulse\_gen}) block, Sec~\ref{subsec:pulse-gen}, are fed onto to the \textit{conv\_dyn\_burst\_ctrl}, Sec~\ref{subsec:burst-ctrl}, where frequencies are limited over time and not on a pulse by pulse basis.
Moreover, v4 boards, give the possibility to select pulse width at the output via a \textit{general-purpose switch}. In addition to that, and for backwards compatibility with v3 boards and earlier, a fixed width, fixed frequency output is also available on the output for legacy boards\footnotemark.\footnotetext{These boards cannot handle high frequencies purely because of their hardware design and in that case \textit{burst mode} is disabled.}
Figure~\ref{fig:pulse-out-sel} shows how the output is selected depending on whether \textit{burst\_en\_n\_i} is activated or not, and also on which pulse width is selected (options are for \textit{SHORT} and \textit{LONG} pulses).
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/pulse-out-select}}
\caption{\label{fig:pulse-out-sel} Pulse repetition output selection}
\end{figure}
\subsubsection{Pulse generator}
\label{subsec:pulse-gen}
%------------------------------------------------------------------------------
Figure~\ref{fig:pulse-gen} shows the implementation of the pulse generator (\textit{conv\_pulse\_gen})
block. When \textit{g\_pgen\_fixed\_width} is \textit{false},
the pulse generator is a simple pass-through. This is usable in converter boards
such as the CONV-TTL-RS485~\cite{conv-ttl-rs485-ohwr}, where the RS-485 outputs are not sensitive to the
duty cycle of the outputs pulses, and which can also be used to distribute
timing information.
When an output stage is sensitive to the pulse duty cycle, such as in the TTL to
blocking converter (CONV-TTL-BLO~\cite{conv-ttl-blo-ohwr}), the \textit{g\_pgen\_fixed\_width}
generic can be set to \textit{true} and this will synthesize a pulse generator
which outputs a pulse with a fixed width (\textit{g\_pgen\_pwidth}) and fixed
duty cycle (1/\textit{g\_pgen\_duty\_cycle\_div}).
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/pulse-gen}}
\caption{\label{fig:pulse-gen} Pulse generator block}
\end{figure}
In this latter case, a finite-state machine (FSM) handles pulse generation and rejection.
Its general operation is shown in Figure~\ref{fig:pulse-gen-operation}.
The operation of the pulse generator depends on whether the glitch filter is enabled.
If this is enabled, then the pulse is synchronized externally to the \textit{conv\_pulse\_gen}
block and it triggers the FSM directly. Alternatively, if the glitch filter is disabled, the
trigger
input starts the pulse (to avoid glitches on the leading edge) and then the pulse is synchronized
and the
FSM triggered to generate the fixed-width pulse. After the pulse width has been reached, the FSM
resets
the input flip-flop and goes into the rejection state.
If any pulses arrive either during the generation state, or the rejection state, the error output
is set high for one clock cycle. This type of error is identified as a \textit{flim\_err\_p}. It is the result of the maximum allowed frequency being reached.
\begin{figure}
\centerline{\includegraphics[width=\textwidth]{fig/pulse-gen-operation}}
\caption{\label{fig:pulse-gen-operation} Pulse generator operation with \textit{g\_pgen\_fixed\_width = true}}
\end{figure}
\subsubsection{Dynamic burst controller}
\label{subsec:burst-ctrl}
The dynamic burst control block emulates temperature rise when new pulses arrive, when the
temperature counter reaches a pre-set maximum value (corresponding to maximum temperature), the
burst controller starts missing
pulses. This means that the board needs to \textit{cool off} between pulses and therefore
implements rejection only as long as the temperature is above the maximum. As soon as recovery is
achieved (temperature is again below maximum) the board starts repeating again.
The time at which the rejection starts depends on the frequency of the pulses coming out of the
\textit{Pulse Generator} block. For high frequencies, temperature will rise quickly and pulses
are rejected earlier. The lower the frequency the longer are repetition times.
The information relating repetition frequency and repetition times is embedded inside the FPGA and is generated in pre-processing and fed as a generic to the entity. The values used for a given thermal model is an array of constant values input as the \textit{g\_temp\_decre\_step} generic.
%They differ for the SHORT and LONG pulse implementations. Appendix~\ref{app:} shows how these values can be generated in pre-processing.
In terms of gateware implementation, see Fig.\ref{fig:burst_ctrl}, the \textit{conv\_dyn\_burst\_ctrl}, module uses a finite
state machine (FSM) to handle transitions between pulse repetition and pulse rejection depending
on the \textit{temp\_rise} counter value.
The FSM is triggered by pulse signals \textit{pulse\_r\_edge\_p\_i} and \textit{pulse\_f\_edge\_p\_i}
that had been generated as a result of synchronisation inside the \textit{Pulse Generator} block. The
FSM outputs a \textit{burst\_ctrl\_rst} signal as a select signal to a multiplexer. The block's output replicates the input or clears it depending on the status of the \textit{burst\_ctrl\_rst} signal.
An error pulse is generated every time a pulse is missed. This is the \textit{frequency watchdog error}, \textit{fwdg\_err\_p}, which signifies that the board has started to miss pulses in order to limit temperature rise.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/burst-ctrl}}
\caption{\label{fig:burst_ctrl} Dynamic burst controller block}
\end{figure}
%------------------------------------------------------------------------------
\subsection{Pulse LED control}
\label{subsec:pulse-led}
%------------------------------------------------------------------------------
A rising edge on the \textit{pulse\_o} signal from the \textit{conv\_pulse\_gen}
block generates a 26-ms active-high pulse signal on the \textit{led\_pulse\_o} port of
\textit{conv\_common\_gw}. This port should be connected to the channel's pulse LED output. The same logic is used to drive LEDs on the inverting channels.
%==============================================================================
% SEC: Memory-mapped peripherals
%==============================================================================
\pagebreak
\section{Memory-mapped peripherals}
\label{sec:memmapped-periphs}
Various memory-mapped peripherals are implemented within \textit{conv\_common\_gw},
as seen below. They are interfaced to a Wishbone interconnect, which is SDB-enabled~\cite{sdb},
granted to the \textit{xwb\_sdb\_crossbar} module used to connect the slaves to the
master.
%==============================================================================
\subsection{I$^2$C to Wishbone bridge}
\label{subsec:i2c-bridge}
%==============================================================================
The Wishbone master in the interconnect is an I$^2$C to Wishbone bridge (\textit{wb\_i2c\_bridge} from
the \textit{general-cores} library~\cite{gencores-ohwr}), which implements the protocol
defined together with ELMA for communication via the serial lines on the VME P1 connector.
Details about this protocol, as well as implementation details for \textit{wb\_i2c\_bridge} can be
found in the module's documentation under the \textit{general-cores/doc/} folder.
Upon instantiating the \textit{wb\_i2c\_bridge} inside \textit{conv\_common\_gw}, the
module's watchdog timeout generic (\textit{g\_fsm\_wdt}) is set such that the watchdog
times out in 24~ms. This value is explained in comments inside the code, as well as
in the appendix to the \textit{wb\_i2c\_bridge} module's documentation.
When an I$^2$C transfer takes place according to the defined protocol, the \textit{led\_i2c\_o}
output strobes four times. This output should be connected to a bicolor LED of choice
for signaling communication.
%==============================================================================
\subsection{Converter board registers}
\label{subsec:conv-regs}
%==============================================================================
The \textit{conv\_regs} module contains various Wishbone-addressable registers that contain status information,
as well as select control functionality. The module was generated using \textit{wbgen2}~\cite{wbgen2}, but has
been adapted to allow for generating the read request to the tag buffer. It is the module which constrains
\textit{conv\_common\_gw} to a maximum of six pulse repetition channels, due to need of relative compatibility
to previously-released implementations of the \textit{conv\_regs} memory map.
Some of the bits in the converter board registers are set from inside the \textit{conv\_common\_gw}
module, but some are status bits that should be connected to external logic. Most of the bits implemented
as part of \textit{conv\_regs} are intended to be active-high logic, so adaptations for this should be made
in logic external to the \textit{conv\_common\_gw} when an external connection is needed.
The inputs that connect to bits in the status register are shown in Table~\ref{tbl:conv-regs-ext-inputs}.
Should some of these inputs not be used, such as for example the rear-panel failsafe lines in the case of
CONV-TTL-BLO~\cite{conv-ttl-blo-ohwr}, the corresponding lines should be connected to all-zeroes.
The \textit{g\_board\_id} and \textit{g\_gwvers} generics connect to registers in
\textit{conv\_regs} as shown in Figure~\ref{fig:bidr-gwvers}.
\begin{table}[h]
\caption{\label{tbl:conv-regs-ext-inputs} Active-high inputs to converter board registers from external logic}
\rowcolors{2}{white}{gray!25}
\centerline {
\begin{tabular}{l l p{.5\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Input port}} & \multicolumn{1}{c}{\textbf{Register}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
sw\_gp\_i & SR.SWITCHES & General-purpose switch state \\
rtmm\_i & SR.RTM[2:0] & RTM Motherboard detection lines \\
rtmp\_i & SR.RTM[5:3] & RTM Piggyback detection lines \\
line\_front\_i & LSR.FRONT & State of front-panel channel lines at FPGA input \\
line\_inv\_i & LSR.FRONTINV & State of front-panel general-purpose inverter channels at FPGA input \\
line\_rear\_i & LSR.REAR & State of rear-panel channel lines at FPGA input \\
line\_front\_fs\_i & LSR.FRONTFS & State of front-panel channel failsafe lines at FPGA input \\
line\_inv\_fs\_i & LSR.FRONTINVFS & State of front-panel general-purpose inverter failsafe lines at FPGA input \\
line\_rear\_fs\_i & LSR.REARFS & State of rear-panel input failsafe lines (whether a cable is plugged in or not) \\
sw\_other\_i & OSWR & State of other on-board switches \\
\hline
\end{tabular}
}
\end{table}
\begin{figure}[h]
\centerline{\includegraphics[width=.7\textwidth]{fig/bidr-gwvers}}
\caption{\label{fig:bidr-gwvers} BIDR and SR.GWVERS connections}
\end{figure}
Some bits or fields inside \textit{conv\_regs} are generated based on the settings of
\textit{g\_with\_*} generics. Should such a generic set to \textit{false}, the corresponding
bits or fields in \textit{conv\_regs} are set to a 'safe' value of '0'. Consult the code
for details on how this is done and which are the fields concerned.
Note that the logic allows less than 6 pulse repetition channels, but not more.
If \textit{g\_nr\_chans $<$ 6}, then the rest of the bits are automatically set to '0',
as in the case a \textit{g\_with\_*} generic is \textit{false}. If \textit{g\_nr\_chans $>$ 6}
a synthesis error will be thrown.
\subsubsection{Fail-safe lines in the line status register}
The CONV-TTL-RS485~\cite{conv-ttl-rs485-ohwr} board has a an extra RS-485 transceiver per each
channel input and output line, dedicated to detecting whether a line is in a fault state, or whether
a cable is not plugged in.
This in RS-485 parlance is called the fail-safe state and half the bits in the
line status register (LSR -- see Appendix~\ref{app:conv-regs-lsr}) take their name after it. Designers of
future converter boards would implement similar features for all the inputs might want to implement a
similar feature on future converter boards. For this, bits are provided in the LSR as shown in Table~\ref{tbl:conv-regs-ext-inputs}.
If no such feature exists, or if the feature is only implemented for one of the two panels (front or rear),
the non-used lines in Table~\ref{tbl:conv-regs-ext-inputs} can simply be connected to all-zeroes.
Note that the register limits the user to six pulse repetition channels and four general-purpose inverter
channels. Should more be needed, another \textit{conv\_common\_gw} module should be used, as shown in
Appendix~\ref{app:more-than-six-chans}.
%==============================================================================
\subsection{MultiBoot}
\label{subsec:multiboot}
%==============================================================================
The \textit{xwb\_xil\_multiboot} module from the \textit{general-cores} library~\cite{gencores-ohwr}
is used to provide MultiBoot functionality via I$^2$C. To find out more about the
module and how to use it, consult its documentation under the \textit{general-cores/doc/} folder.
%%==============================================================================
\subsection{One-wire temperature}
\label{subsec:onewire}
%%==============================================================================
The \textit{conv\_common\_gw} used a one-wire interface module (\textit{gc\_ds182x\_interface}) to the one-wire ds182x thermometer chip present on the board.
The module requires the thermometer input \textit{thermometer\_b}, directly from the board plus a pps (pulse-per-second) signal (generated by \textit{wf\_decr\_counter} component). This interface outputs the chip unique ID as a 64-bit value, and the board temperature as a 16-bit value. These 2 values result in 3 memory mapped registers, 2, 32-bit registers for the chip ID, and 1 for the temperature.
.
%%==============================================================================
%\subsection{One-wire master}
%\label{subsec:onewire}
%%==============================================================================
%
%Converter boards are expected to contain a DS18B20 thermometer chip~\cite{ds18b20},
%which can be used for monitoring the temperature of, and obtaining a unique
%identifier for the board.
%
%The one-wire master module provides two registers for software control of the module.
%Note that the FPGA does not control the one-wire thermometer lines in any way.
%Accessing the thermometer is done through software only.
%
%More details about how to access the one-wire master module can be found in its
%documentation~\cite{onewire-core}.
%==============================================================================
% Appendices
%==============================================================================
\pagebreak
\begin{appendices}
%==============================================================================
% APP: Memmap
%==============================================================================
\section{Memory map}
\label{app:memmap}
Table~\ref{tbl:memmap} shows the maximum memory map obtainable with the \textit{conv\_common\_gw}
module. This is obtained when the \textit{g\_nr\_chans} generic is set to the maximum value of
\textit{6}. Should less channels be desired, the higher-numbered registers for the channels
(e.g., CH5PCR and CH6PCR for \textit{g\_nr\_chans = 4}) can be considered as \textit{Reserved}
(read out as 0).
The following sections list the memory map of each peripheral.
\begin{table}[h]
\caption{\textit{conv\_common\_gw} memory map}
\label{tbl:memmap}
\centerline
{
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l l l p{.4\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Peripheral}} & \multicolumn{2}{c}{\textbf{Address range}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
Board registers & 0x000 & 0x0ff & Coverter board registers \\
MultiBoot & 0x100 & 0x11f & MultiBoot module \\
%One-wire master & 0x200 & 0x2ff & One-wire master for DS18B20 thermometer module \\
SDB descriptor & 0xf00 & 0xfff & SDB descriptor (see~\cite{sdb}) \\
\hline
\end{tabular}
}
\end{table}
%%------------------------------------------------------------------------------
%% SUBSEC: conv-regs
%%------------------------------------------------------------------------------
\include{conv-regs}
%------------------------------------------------------------------------------
% SUBSEC: MultiBoot
%------------------------------------------------------------------------------
\include{multiboot-regs}
%------------------------------------------------------------------------------
% SUBSEC: Thermo
%------------------------------------------------------------------------------
%\subsection{Thermometer module}
%\label{app:memmap-thermo}
%
%\indent Base address: 0x200
%
%\vspace*{11pt}
%
%\centerline
%{
%\rowcolors{2}{white}{gray!25}
%\begin{tabular}{l l l p{.5\textwidth}}
%\hline
%\textbf{Offset} & \textbf{Default} & \textbf{Name} & \textbf{Description} \\
%\hline
%0x00 & 0x00000000 & OWCSR & One-Wire Control and Status Register \\
%0x04 & 0x00000004 & OWCDR & One-Wire Clock Divider Registers \\
%\hline
%\end{tabular}
%}
%
%\vspace*{11pt}
%
%For details on the bits of the thermometer module access registers, see the
%OneWire Master module's documentation~\cite{onewire-core}.
%
%Note that the OWCDR should be set accordingly for proper functioning of the
%one-wire timings. The value for the current version of the gateware is
%\verb-OWCDR = 0x00130063-.
%==============================================================================
% APP: Changing the code for more than six pulse repetition channels
%==============================================================================
\pagebreak
\section{Gateware for pulse converters with more than six conversion channels}
\label{app:more-than-six-chans}
This appendix offers guidelines on how to use or change \textit{conv\_common\_gw}
should a pulse repeater with more than six channels be eventually implemented.
Note that none of the guidelines here have been tested, since no board exists
with more than six channels at the time of writing of this document.
The first option is obviously instantiating more than one \textit{conv\_common\_gw}
component, each with its appropriate \textit{g\_nr\_chans} and making the appropriate connections
to the FPGA outputs. Note that each \textit{conv\_common\_gw} will
come with its own \textit{conv\_regs}, MultiBoot and one-wire master peripherals.
In this case, since it is expected that there is only one flash and thermometer
chip on-board, connect only the outputs of one of the \textit{conv\_common\_gw} modules
to the top-level module outputs, as shown in Figure~\ref{fig:more-than-six-chans}.
The synthesis tool should be smart enough to optimize away the unused modules.
\begin{figure}[h]
\centerline{\includegraphics[width=1.1\textwidth]{fig/more-than-six-chans}}
\caption{\label{fig:more-than-six-chans} Connect the outputs of only one \textit{conv\_common\_gw} module at the top-level}
\end{figure}
\pagebreak
The second, non-encouraged option, is to change the \textit{conv\_common\_gw} code.
Note that this will:
\begin{enumerate}
\item Involve changing the memory map and \textit{conv\_regs} component,
which will
\item Make the \textit{conv\_common\_gw} module incompatible with the
version described in this document
\end{enumerate}
If this option is chosen, the reader should start by changing the
\textit{c\_max\_nr\_chans} generic in the package file (\textit{conv\_common\_gw\_pkg.vhd}).
Then, a new memory map should be chosen and the \textit{conv\_regs} component
adapted as appropriate.
%==============================================================================
\end{appendices}
%==============================================================================
%==============================================================================
% Bibliography
%==============================================================================
\pagebreak
\bibliographystyle{ieeetr}
\bibliography{conv-common-gw}
\addcontentsline{toc}{section}{References}
\end{document}
conv-common-gw-4b29f81745c3c0a760395b21be78b872bfc85060/doc/conv-regs.tex 0000664 0000000 0000000 00000170534 13055247455 0024363 0 ustar 00root root 0000000 0000000 \subsection{Converter board registers}
\label{app:conv-regs}
Base address: 0x000
{
\rowcolors{2}{white}{gray!25}
\begin{longtable}{l l l p{.5\textwidth}}
\hline
\textbf{Offset} & \textbf{Reset} & \textbf{Name}
& \textbf{Description} \\
\hline
\endfirsthead
\hline
\textbf{Offset} & \textbf{Reset} & \textbf{Name}
& \textbf{Description} \\
\hline
\endhead
\hline
\endfoot
0x0& 0x54424c4f & BIDR & Board ID Register\\
0x4& Note(1)& SR & Status Register\\
0x8& 0x00000000 & ERR & Error Register\\
0xc& 0x00000000 & CR & Control Register\\
0x10& 0x00000000 & CH1TTLPCR & Channel 1 TTL Pulse Counter Register\\
0x14& 0x00000000 & CH2TTLPCR & Channel 2 TTL Pulse Counter Register\\
0x18& 0x00000000 & CH3TTLPCR & Channel 3 TTL Pulse Counter Register\\
0x1c& 0x00000000 & CH4TTLPCR & Channel 4 TTL Pulse Counter Register\\
0x20& 0x00000000 & CH5TTLPCR & Channel 5 TTL Pulse Counter Register\\
0x24& 0x00000000 & CH6TTLPCR & Channel 6 TTL Pulse Counter Register\\
0x28& 0x00000000 & CH1BLOPCR & Channel 1 BLO Pulse Counter Register\\
0x2c& 0x00000000 & CH2BLOPCR & Channel 2 BLO Pulse Counter Register\\
0x30& 0x00000000 & CH3BLOPCR & Channel 3 BLO Pulse Counter Register\\
0x34& 0x00000000 & CH4BLOPCR & Channel 4 BLO Pulse Counter Register\\
0x38& 0x00000000 & CH5BLOPCR & Channel 5 BLO Pulse Counter Register\\
0x3c& 0x00000000 & CH6BLOPCR & Channel 6 BLO Pulse Counter Register\\
0x40& 0x00000000 & TVLR & Time Value Low Register\\
0x44& 0x00000000 & TVHR & Time Value High Register\\
0x48& 0x00000000 & TBMR & Tag Buffer Meta Register\\
0x4c& 0x00000000 & TBCYR & Tag Buffer Cycles Register\\
0x50& 0x00000000 & TBTLR & Tag Buffer TAI Low Register\\
0x54& 0x00000000 & TBTHR & Tag Buffer TAI High Register\\
0x58& 0x00020000 & TBCSR & Tag Buffer Control and Status Register\\
0x5c& 0x00000000 & CH1LTSCYR & Channel 1 Latest Timestamp Cycles Register\\
0x60& 0x00000000 & CH1LTSTLR & Channel 1 Latest Timestamp TAI Low Register\\
0x64& 0x00000000 & CH1LTSTHR & Channel 1 Latest Timestamp TAI High Register\\
0x68& 0x00000000 & CH2LTSCYR & Channel 2 Latest Timestamp Cycles Register\\
0x6c& 0x00000000 & CH2LTSTLR & Channel 2 Latest Timestamp TAI Low Register\\
0x70& 0x00000000 & CH2LTSTHR & Channel 2 Latest Timestamp TAI High Register\\
0x74& 0x00000000 & CH3LTSCYR & Channel 3 Latest Timestamp Cycles Register\\
0x78& 0x00000000 & CH3LTSTLR & Channel 3 Latest Timestamp TAI Low Register\\
0x7c& 0x00000000 & CH3LTSTHR & Channel 3 Latest Timestamp TAI High Register\\
0x80& 0x00000000 & CH4LTSCYR & Channel 4 Latest Timestamp Cycles Register\\
0x84& 0x00000000 & CH4LTSTLR & Channel 4 Latest Timestamp TAI Low Register\\
0x88& 0x00000000 & CH4LTSTHR & Channel 4 Latest Timestamp TAI High Register\\
0x8c& 0x00000000 & CH5LTSCYR & Channel 5 Latest Timestamp Cycles Register\\
0x90& 0x00000000 & CH5LTSTLR & Channel 5 Latest Timestamp TAI Low Register\\
0x94& 0x00000000 & CH5LTSTHR & Channel 5 Latest Timestamp TAI High Register\\
0x98& 0x00000000 & CH6LTSCYR & Channel 6 Latest Timestamp Cycles Register\\
0x9c& 0x00000000 & CH6LTSTLR & Channel 6 Latest Timestamp TAI Low Register\\
0xa0& 0x00000000 & CH6LTSTHR & Channel 6 Latest Timestamp TAI High Register\\
0xa4& Note(2) & LSR & Line Status Register\\
0xa8& 0x00000000 & OSWR & Other switch resistor\\
0xac& Unique ID & UIDLR & Thermometer ID Low register\\
0xb0& Unique ID & UIDHR & Thermometer ID High register\\
0xb4& 0x00000000 & TEMPR & Board Temperature Register\\
\hline
\end{longtable}
}
\noindent Note (1): The reset value of the SR cannot be specified, since it is based on the
gateware version, the state of the on-board switches and whether an RTM is plugged in or not.
\noindent Note (2): The reset value of the LSR cannot be specified, since it depends on whether a cable
is plugged into the channel or not.
\vspace{11pt}
\subsubsection{BIDR -- Board ID Register}
\label{app:conv-regs-BIDR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BIDR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BIDR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BIDR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BIDR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
BIDR
} [\emph{read-only}]: ID register bits
\\
Reset value: 0x54424c4f
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{SR -- Status Register}
\label{app:conv-regs-SR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}WRPRES} & \multicolumn{4}{|c|}{\cellcolor{gray!25}HWVERS[5:2]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{2}{|c|}{\cellcolor{gray!25}HWVERS[1:0]} & \multicolumn{6}{|c|}{\cellcolor{gray!25}RTM[5:0]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}SWITCHES[7:0]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}GWVERS[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
GWVERS
} [\emph{read-only}]: Gateware version
\\
Leftmost nibble hex value is major release decimal value \\ Rightmost nibble hex value is minor release decimal value \\ e.g. \\ 0x11 -- v1.1 \\ 0x2e -- v2.14
\end{small}
\item \begin{small}
{\bf
SWITCHES
} [\emph{read-only}]: Status of on-board general-purpose switches
\\
Eg: SW1.1-- SR.SWITCHES[0] \\ SW1.2-- SR.SWITCHES[1] \\ SW2.1-- SR.SWITCHES[4] \\ SW2.4-- SR.SWITCHES[7] \\ 1 -- switch is ON \\ 0 -- switch is OFF
\end{small}
\item \begin{small}
{\bf
RTM
} [\emph{read-only}]: RTM detection lines cite{rtm-det}
\\
1 bit per RTM output channel \\ 1 -- line active \\ 0 -- line inactive
\end{small}
\item \begin{small}
{\bf
HWVERS
} [\emph{read-only}]: Hardware version
\\
PCB version - Hardwired on the board \\ Only meaningful for HW v4.0 and over \\ Earlier versions show 0. The register \\ uses 4 bits for the version number and\\ 2 bits for the execution.\\ e.g. \\ 0x010001 -- hw v4.1 \\ 0x010111 -- hw v5.3 \\ 0x00-- hw v3 and earlier
\end{small}
\item \begin{small}
{\bf
WRPRES
} [\emph{read-only}]: White Rabbit present
\\
1 -- White Rabbit present \\ 0 -- White Rabbit not present
\end{small}
\end{itemize}
\subsubsection{ERR - Error Register}
\label{app:conv-regs-ERR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & \multicolumn{6}{|c|}{\cellcolor{gray!25}FWDG\_PMISSE[5:0]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{6}{|c|}{\cellcolor{gray!25}FLIM\_PMISSE[5:0]} & \multicolumn{1}{|c|}{\cellcolor{gray!25}I2C\_ERR} & \multicolumn{1}{|c|}{\cellcolor{gray!25}I2C\_WDTO}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
I2C\_WDTO
} [\emph{read/write}]: I2C communication watchdog timeout error
\\
1 -- timeout occured \\ 0 -- no timeout \\ This bit can be cleared by writing a '1' to it
\end{small}
\item \begin{small}
{\bf
I2C\_ERR
} [\emph{read/write}]: I2C communication error
\\
1 -- attempted to address non-existing address \\ 0 -- idle \\ This bit can be cleared by writing a '1' to it
\end{small}
\item \begin{small}
{\bf
FLIM\_PMISSE
} [\emph{read/write}]: Frequency error
\\
1 -- Input above maximum supported frequency \\ 0 -- idle \\ Bit 0 -- channel 1 \\ Bit 1 -- channel 2 \\ etc. \\ Each bit can be cleared by writing a '1' to it
\end{small}
\item \begin{small}
{\bf
FWDG\_PMISSE
} [\emph{read/write}]: Frequency watchdog error
\\
1 -- Pulse over maximum pulse count for given frequency' \\ 0 -- idle \\ Bit 0 -- channel 1 \\ Bit 1 -- channel 2 \\ etc. \\ Each bit can be cleared by writing a '1' to it
\end{small}
\end{itemize}
\subsubsection{CR - Control Register}
\label{app:conv-regs-CR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & \multicolumn{2}{|c|}{\cellcolor{gray!25}MPT[7:6]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{6}{|c|}{\cellcolor{gray!25}MPT[5:0]} & \multicolumn{1}{|c|}{\cellcolor{gray!25}RST} & \multicolumn{1}{|c|}{\cellcolor{gray!25}RST\_UNLOCK}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
RST\_UNLOCK
} [\emph{read/write}]: Reset unlock bit
\\
1 -- Reset bit unlocked \\ 0 -- Reset bit locked
\end{small}
\item \begin{small}
{\bf
RST
} [\emph{read/write}]: Reset bit - active only if RST\_UNLOCK is 1
\\
1 -- initiate logic reset \\ 0 -- no reset
\end{small}
\item \begin{small}
{\bf
MPT
} [\emph{write-only}]: Manual Pulse Trigger
\\
Write the following sequence to trigger a pulse: \\ 0xde -- Byte 1 of magic sequence \\ 0xad -- Byte 2 of magic sequence \\ 0xbe -- Byte 3 of magic sequence \\ 0xef -- Byte 4 of magic sequence \\ Number in range 1..6 -- trigger a pulse
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\subsubsection{CH1TTLPCR - Channel 1 Pulse Counter Register for TTL pulses}
\label{app:conv-regs-CH1TTLPCR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1TTLPCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1TTLPCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1TTLPCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1TTLPCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH1TTLPCR
} [\emph{read/write}]: TTL pulse counter value
\end{small}
\end{itemize}
\subsubsection{CH2TTLPCR - Channel 2 Pulse Counter Register for TTL pulses}
\label{app:conv-regs-CH2TTLPCR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2TTLPCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2TTLPCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2TTLPCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2TTLPCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH2TTLPCR
} [\emph{read/write}]: TTL pulse counter value
\end{small}
\end{itemize}
\subsubsection{CH3TTLPCR - Channel 3 Pulse Counter Register for TTL pulses}
\label{app:conv-regs-CH3TTLPCR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3TTLPCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3TTLPCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3TTLPCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3TTLPCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH3TTLPCR
} [\emph{read/write}]: TTL pulse counter value
\end{small}
\end{itemize}
\subsubsection{CH4TTLPCR - Channel 4 Pulse Counter Register for TTL pulses}
\label{app:conv-regs-CH4TTLPCR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4TTLPCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4TTLPCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4TTLPCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4TTLPCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH4TTLPCR
} [\emph{read/write}]: TTL pulse counter value
\end{small}
\end{itemize}
\subsubsection{CH5TTLPCR - Channel 5 Pulse Counter Register for TTL pulses}
\label{app:conv-regs-CH5TTLPCR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5TTLPCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5TTLPCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5TTLPCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5TTLPCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH5TTLPCR
} [\emph{read/write}]: TTL pulse counter value
\end{small}
\end{itemize}
\subsubsection{CH6TTLPCR - Channel 6 Pulse Counter Register for TTL pulses}
\label{app:conv-regs-CH6TTLPCR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6TTLPCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6TTLPCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6TTLPCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6TTLPCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH6TTLPCR
} [\emph{read/write}]: TTL pulse counter value
\end{small}
\end{itemize}
\subsubsection{CH1BLOPCR - Channel 1 Pulse Counter Register for BLO pulses}
\label{app:conv-regs-CH1BLOPCR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1BLOPCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1BLOPCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1BLOPCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1BLOPCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH1BLOPCR
} [\emph{read/write}]: BLO pulse counter value
\end{small}
\end{itemize}
\subsubsection{CH2BLOPCR - Channel 2 Pulse Counter Register for BLO pulses}
\label{app:conv-regs-CH2BLOPCR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2BLOPCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2BLOPCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2BLOPCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2BLOPCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH2BLOPCR
} [\emph{read/write}]: BLO pulse counter value
\end{small}
\end{itemize}
\subsubsection{CH3BLOPCR - Channel 3 Pulse Counter Register for BLO pulses}
\label{app:conv-regs-CH3BLOPCR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3BLOPCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3BLOPCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3BLOPCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3BLOPCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH3BLOPCR
} [\emph{read/write}]: BLO pulse counter value
\end{small}
\end{itemize}
\subsubsection{CH4BLOPCR - Channel 4 Pulse Counter Register for BLO pulses}
\label{app:conv-regs-CH4BLOPCR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4BLOPCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4BLOPCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4BLOPCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4BLOPCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH4BLOPCR
} [\emph{read/write}]: BLO pulse counter value
\end{small}
\end{itemize}
\subsubsection{CH5BLOPCR - Channel 5 Pulse Counter Register for BLO pulses}
\label{app:conv-regs-CH5BLOPCR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5BLOPCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5BLOPCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5BLOPCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5BLOPCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH5BLOPCR
} [\emph{read/write}]: BLO pulse counter value
\end{small}
\end{itemize}
\subsubsection{CH6BLOPCR - Channel 6 Pulse Counter Register for BLO pulses}
\label{app:conv-regs-CH6BLOPCR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6BLOPCR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6BLOPCR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6BLOPCR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6BLOPCR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH6BLOPCR
} [\emph{read/write}]: BLO pulse counter value
\end{small}
\end{itemize}
\subsubsection{TVLR - Time Value Low Register}
\label{app:conv-regs-TVLR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TVLR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TVLR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TVLR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TVLR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TVLR
} [\emph{read/write}]: TAI seconds counter bits 31..0
\\
Writing this field resets the internal cycles counter.
\end{small}
\end{itemize}
\subsubsection{TVHR - Time Value High Register}
\label{app:conv-regs-TVHR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TVHR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TVHR
} [\emph{read/write}]: TAI seconds counter bits 39..32
\\
Writing this field resets the internal cycles counter.
\end{small}
\end{itemize}
\subsubsection{TBMR - Tag Buffer Meta Register}
\label{app:conv-regs-TBMR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c|}{\cellcolor{gray!25}WRTAG} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{1}{|c}{-} & - & \multicolumn{6}{|c|}{\cellcolor{gray!25}CHAN[5:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CHAN
} [\emph{read-only}]: Channel mask
\\
Mask for the channel(s) that triggered time-tag storage: \\ bit 0 -- channel 1 \\ bit 1 -- channel 2 \\ ... \\ bit 5 -- channel 6
\end{small}
\item \begin{small}
{\bf
WRTAG
} [\emph{read-only}]: White Rabbit present
\\
1 - Current time tag generated with White Rabbit \\ 0 - Current time tag generated with internal counter
\end{small}
\end{itemize}
\subsubsection{TBCYR - Tag Buffer Cycles Register}
\label{app:conv-regs-TBCYR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}TBCYR[27:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TBCYR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TBCYR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TBCYR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TBCYR
} [\emph{read-only}]: Cycles counter
\\
Value of the 8-ns cycles counter when time tag was taken.
\end{small}
\end{itemize}
\subsubsection{TBTLR - Tag Buffer TAI Low Register}
\label{app:conv-regs-TBTLR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TBTLR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TBTLR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TBTLR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TBTLR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TBTLR
} [\emph{read-only}]: Lower part of TAI seconds counter
\\
Value of the TAI seconds counter bits 31..0 when time tag was taken.
\end{small}
\end{itemize}
\subsubsection{TBTHR - Tag Buffer TAI High Register}
\label{app:conv-regs-TBTHR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TBTHR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TBTHR
} [\emph{read-only}]: Upper part of TAI seconds counter
\\
Value of the TAI seconds counter bits 39..32 when time tag was taken.
\end{small}
\end{itemize}
\subsubsection{TBCSR - Tag Buffer Control and Status Register}
\label{app:conv-regs-TBCSR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}CLR} & \multicolumn{1}{|c|}{\cellcolor{gray!25}EMPTY} & \multicolumn{1}{|c|}{\cellcolor{gray!25}FULL}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{1}{|c}{-} & \multicolumn{7}{|c|}{\cellcolor{gray!25}USEDW[6:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
USEDW
} [\emph{read-only}]: Buffer counter
\\
Number of samples in the ring buffer
\end{small}
\item \begin{small}
{\bf
FULL
} [\emph{read-only}]: Buffer full
\\
1 -- buffer full \\ 0 -- buffer is not full
\end{small}
\item \begin{small}
{\bf
EMPTY
} [\emph{read-only}]: Buffer empty
\\
1 -- buffer empty\\ 0 -- buffer is not empty
\end{small}
\item \begin{small}
{\bf
CLR
} [\emph{read/write}]: Clear tag buffer
\\
1 -- clear\\ 0 -- no effect
\end{small}
\end{itemize}
\subsubsection{CH1LTSCYR - Channel 1 Latest Timestamp Cycles Register}
\label{app:conv-regs-CH1LTSCYR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}CH1LTSCYR[27:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1LTSCYR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1LTSCYR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1LTSCYR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH1LTSCYR
} [\emph{read-only}]: Cycles counter
\\
Value of the 8-ns cycles counter when time tag was taken.
\end{small}
\end{itemize}
\subsubsection{CH1LTSTLR - Channel 1 Latest Timestamp TAI Low Register}
\label{app:conv-regs-CH1LTSTLR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1LTSTLR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1LTSTLR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1LTSTLR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH1LTSTLR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH1LTSTLR
} [\emph{read-only}]: Lower part of TAI seconds counter
\\
Value of the TAI seconds counter bits 31..0 when time tag was taken.
\end{small}
\end{itemize}
\subsubsection{CH1LTSTHR - Channel 1 Latest Timestamp TAI High Register}
\label{app:conv-regs-CH1LTSTHR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c|}{\cellcolor{gray!25}WRTAG} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TAI
} [\emph{read-only}]: Upper part of TAI seconds counter
\\
Value of the TAI seconds counter bits 39..32 when time tag was taken.
\end{small}
\item \begin{small}
{\bf
WRTAG
} [\emph{read-only}]: White Rabbit present
\\
1 - Current time tag generated with White Rabbit \\ 0 - Current time tag generated with internal counter
\end{small}
\end{itemize}
\subsubsection{CH2LTSCYR - Channel 2 Latest Timestamp Cycles Register}
\label{app:conv-regs-CH2LTSCYR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}CH2LTSCYR[27:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2LTSCYR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2LTSCYR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2LTSCYR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH2LTSCYR
} [\emph{read-only}]: Cycles counter
\\
Value of the 8-ns cycles counter when time tag was taken.
\end{small}
\end{itemize}
\subsubsection{CH2LTSTLR - Channel 2 Latest Timestamp TAI Low Register}
\label{app:conv-regs-CH2LTSTLR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2LTSTLR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2LTSTLR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2LTSTLR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH2LTSTLR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH2LTSTLR
} [\emph{read-only}]: Lower part of TAI seconds counter
\\
Value of the TAI seconds counter bits 31..0 when time tag was taken.
\end{small}
\end{itemize}
\subsubsection{CH2LTSTHR - Channel 2 Latest Timestamp TAI High Register}
\label{app:conv-regs-CH2LTSTHR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c|}{\cellcolor{gray!25}WRTAG} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TAI
} [\emph{read-only}]: Upper part of TAI seconds counter
\\
Value of the TAI seconds counter bits 39..32 when time tag was taken.
\end{small}
\item \begin{small}
{\bf
WRTAG
} [\emph{read-only}]: White Rabbit present
\\
1 - Current time tag generated with White Rabbit \\ 0 - Current time tag generated with internal counter
\end{small}
\end{itemize}
\subsubsection{CH3LTSCYR - Channel 3 Latest Timestamp Cycles Register}
\label{app:conv-regs-CH3LTSCYR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}CH3LTSCYR[27:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3LTSCYR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3LTSCYR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3LTSCYR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH3LTSCYR
} [\emph{read-only}]: Cycles counter
\\
Value of the 8-ns cycles counter when time tag was taken.
\end{small}
\end{itemize}
\subsubsection{CH3LTSTLR - Channel 3 Latest Timestamp TAI Low Register}
\label{app:conv-regs-CH3LTSTLR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3LTSTLR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3LTSTLR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3LTSTLR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH3LTSTLR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH3LTSTLR
} [\emph{read-only}]: Lower part of TAI seconds counter
\\
Value of the TAI seconds counter bits 31..0 when time tag was taken.
\end{small}
\end{itemize}
\subsubsection{CH3LTSTHR - Channel 3 Latest Timestamp TAI High Register}
\label{app:conv-regs-CH3LTSTHR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c|}{\cellcolor{gray!25}WRTAG} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TAI
} [\emph{read-only}]: Upper part of TAI seconds counter
\\
Value of the TAI seconds counter bits 39..32 when time tag was taken.
\end{small}
\item \begin{small}
{\bf
WRTAG
} [\emph{read-only}]: White Rabbit present
\\
1 - Current time tag generated with White Rabbit \\ 0 - Current time tag generated with internal counter
\end{small}
\end{itemize}
\subsubsection{CH4LTSCYR - Channel 4 Latest Timestamp Cycles Register}
\label{app:conv-regs-CH4LTSCYR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}CH4LTSCYR[27:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4LTSCYR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4LTSCYR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4LTSCYR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH4LTSCYR
} [\emph{read-only}]: Cycles counter
\\
Value of the 8-ns cycles counter when time tag was taken.
\end{small}
\end{itemize}
\subsubsection{CH4LTSTLR - Channel 4 Latest Timestamp TAI Low Register}
\label{app:conv-regs-CH4LTSTLR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4LTSTLR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4LTSTLR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4LTSTLR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH4LTSTLR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH4LTSTLR
} [\emph{read-only}]: Lower part of TAI seconds counter
\\
Value of the TAI seconds counter bits 31..0 when time tag was taken.
\end{small}
\end{itemize}
\subsubsection{CH4LTSTHR - Channel 4 Latest Timestamp TAI High Register}
\label{app:conv-regs-CH4LTSTHR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c|}{\cellcolor{gray!25}WRTAG} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TAI
} [\emph{read-only}]: Upper part of TAI seconds counter
\\
Value of the TAI seconds counter bits 39..32 when time tag was taken.
\end{small}
\item \begin{small}
{\bf
WRTAG
} [\emph{read-only}]: White Rabbit present
\\
1 - Current time tag generated with White Rabbit \\ 0 - Current time tag generated with internal counter
\end{small}
\end{itemize}
\subsubsection{CH5LTSCYR - Channel 5 Latest Timestamp Cycles Register}
\label{app:conv-regs-CH5LTSCYR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}CH5LTSCYR[27:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5LTSCYR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5LTSCYR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5LTSCYR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH5LTSCYR
} [\emph{read-only}]: Cycles counter
\\
Value of the 8-ns cycles counter when time tag was taken.
\end{small}
\end{itemize}
\subsubsection{CH5LTSTLR - Channel 5 Latest Timestamp TAI Low Register}
\label{app:conv-regs-CH5LTSTLR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5LTSTLR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5LTSTLR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5LTSTLR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH5LTSTLR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH5LTSTLR
} [\emph{read-only}]: Lower part of TAI seconds counter
\\
Value of the TAI seconds counter bits 31..0 when time tag was taken.
\end{small}
\end{itemize}
\subsubsection{CH5LTSTHR - Channel 5 Latest Timestamp TAI High Register}
\label{app:conv-regs-CH5LTSTHR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c|}{\cellcolor{gray!25}WRTAG} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TAI
} [\emph{read-only}]: Upper part of TAI seconds counter
\\
Value of the TAI seconds counter bits 39..32 when time tag was taken.
\end{small}
\item \begin{small}
{\bf
WRTAG
} [\emph{read-only}]: White Rabbit present
\\
1 - Current time tag generated with White Rabbit \\ 0 - Current time tag generated with internal counter
\end{small}
\end{itemize}
\subsubsection{CH6LTSCYR - Channel 6 Latest Timestamp Cycles Register}
\label{app:conv-regs-CH6LTSCYR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}CH6LTSCYR[27:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6LTSCYR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6LTSCYR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6LTSCYR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH6LTSCYR
} [\emph{read-only}]: Cycles counter
\\
Value of the 8-ns cycles counter when time tag was taken.
\end{small}
\end{itemize}
\subsubsection{CH6LTSTLR - Channel 6 Latest Timestamp TAI Low Register}
\label{app:conv-regs-CH6LTSTLR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6LTSTLR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6LTSTLR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6LTSTLR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CH6LTSTLR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CH6LTSTLR
} [\emph{read-only}]: Lower part of TAI seconds counter
\\
Value of the TAI seconds counter bits 31..0 when time tag was taken.
\end{small}
\end{itemize}
\subsubsection{CH6LTSTHR - Channel 6 Latest Timestamp TAI High Register}
\label{app:conv-regs-CH6LTSTHR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c|}{\cellcolor{gray!25}WRTAG} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TAI
} [\emph{read-only}]: Upper part of TAI seconds counter
\\
Value of the TAI seconds counter bits 39..32 when time tag was taken.
\end{small}
\item \begin{small}
{\bf
WRTAG
} [\emph{read-only}]: White Rabbit present
\\
1 - Current time tag generated with White Rabbit \\ 0 - Current time tag generated with internal counter
\end{small}
\end{itemize}
\subsubsection{LSR - Line Status Register}
\label{app:conv-regs-lsr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{6}{|c|}{\cellcolor{gray!25}REARFS[5:0]} & \multicolumn{2}{|c|}{\cellcolor{gray!25}FRONTINVFS[3:2]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{2}{|c|}{\cellcolor{gray!25}FRONTINVFS[1:0]} & \multicolumn{6}{|c|}{\cellcolor{gray!25}FRONTFS[5:0]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{6}{|c|}{\cellcolor{gray!25}REAR[5:0]} & \multicolumn{2}{|c|}{\cellcolor{gray!25}FRONTINV[3:2]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{2}{|c|}{\cellcolor{gray!25}FRONTINV[1:0]} & \multicolumn{6}{|c|}{\cellcolor{gray!25}FRONT[5:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
FRONT
} [\emph{read-only}]: Front panel channel input state
\\
Line state at board input\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
\end{small}
\item \begin{small}
{\bf
FRONTINV
} [\emph{read-only}]: Front panel INV-TTL input state
\\
Line state at board input\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
\end{small}
\item \begin{small}
{\bf
REAR
} [\emph{read-only}]: Rear panel input state
\\
Line state at board input\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
\end{small}
\item \begin{small}
{\bf
FRONTFS
} [\emph{read-only}]: Front panel input failsafe state
\\
High if line is in failsafe mode (e.g., no cable plugged in)\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
\end{small}
\item \begin{small}
{\bf
FRONTINVFS
} [\emph{read-only}]: Front panel inverter input failsafe state
\\
High if line is in failsafe mode (e.g., no cable plugged in)\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
\end{small}
\item \begin{small}
{\bf
REARFS
} [\emph{read-only}]: Rear panel input failsafe state
\\
High if line is in failsafe mode (e.g., no cable plugged in)\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
\end{small}
\end{itemize}
\subsubsection{OSWR - Other Switch Register}
\label{app:conv-regs-OSWR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}SWITCHES[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}SWITCHES[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}SWITCHES[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}SWITCHES[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
SWITCHES
} [\emph{read-only}]: Switch state
\\
1 -- switch is ON \\ 0 -- switch is OFF
\end{small}
\end{itemize}
\subsubsection{UIDLR - 32 LS bits of 1-wire thermometer ID}
\label{app:conv-regs-UIDLR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}UIDLR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}UIDLR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}UIDLR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}UIDLR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
UIDLR
} [\emph{read-only}]: LS bits of 1-wire DS18B20U thermometer ID
\end{small}
\end{itemize}
\subsubsection{UIDHR - 32 MS bits of 1-wire thermometer ID}
\label{app:conv-regs-UIDHR}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}UIDHR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}UIDHR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}UIDHR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}UIDHR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
UIDHR
} [\emph{read-only}]: MS bits of 1-wire DS18B20U thermometer ID
\end{small}
\end{itemize}
\subsubsection{TEMPR - Temperature Resgister }
\label{app:conv-regs-TEMPR}
Raw temperature data from the one wire DS18B20U. The register is 2-bytes long; it translates to ${}^{o}C$ as follows: Temp = register value / 16.0
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TEMPR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TEMPR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
TEMPR
} [\emph{read-only}]: TEMP
\\
Current on-board temperature
\end{small}
\end{itemize}
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conv-common-gw-4b29f81745c3c0a760395b21be78b872bfc85060/doc/multiboot-regs.tex 0000664 0000000 0000000 00000022134 13055247455 0025424 0 ustar 00root root 0000000 0000000 \subsection{MultiBoot controller}
\label{app:multiboot-regs}
Base address: 0x100
{
\rowcolors{2}{white}{gray!25}
\begin{longtable}{l l l p{.5\textwidth}}
\hline
\textbf{Offset} & \textbf{Reset} & \textbf{Name}
& \textbf{Description} \\
\hline
\endfirsthead
\hline
\hline
\endhead
\hline
\endfoot
0x0 & 0x00000000 & CR & Control Register\\
0x4 & 0x00000000 & SR & Status Register\\
0x8 & 0x00000000 & GBBAR & Golden Bitstream Base Address Register\\
0xc & 0x00000000 & MBBAR & MultiBoot Bitstream Base Address Register\\
0x10 & 0x10000000 & FAR & Flash Access Register\\
\end{longtable}
}
\vspace{11pt}
\subsubsection{CR -- Control Register}
\label{app:multiboot-regs-cr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}IPROG} & \multicolumn{1}{|c|}{\cellcolor{gray!25}IPROG\_UNLOCK}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{1}{|c}{-} & \multicolumn{1}{|c|}{\cellcolor{gray!25}RDCFGREG} & \multicolumn{6}{|c|}{\cellcolor{gray!25}CFGREGADR[5:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CFGREGADR
} [\emph{read/write}]: Configuration register address
\\
Address of FPGA configuration register to read.
\end{small}
\item \begin{small}
{\bf
RDCFGREG
} [\emph{write-only}]: Read FPGA configuration register
\\
1 -- Start FPGA configuration register sequence. \\ 0 -- No effect.
\end{small}
\item \begin{small}
{\bf
IPROG\_UNLOCK
} [\emph{read/write}]: Unlock bit for the IPROG command
\\
1 -- Unlock IPROG bit. \\ 0 -- No effect.
\end{small}
\item \begin{small}
{\bf
IPROG
} [\emph{read/write}]: Start IPROG sequence
\\
1 -- Start IPROG configuration sequence \\ 0 -- No effect \\ This bit needs to be unlocked by writing the IPROG\_UNLOCK bit first. \\ A write to this bit with IPROG\_UNLOCK cleared has no effect.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{SR -- Status Register}
\label{app:multiboot-regs-sr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}WDTO} & \multicolumn{1}{|c|}{\cellcolor{gray!25}IMGVALID}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CFGREGIMG[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CFGREGIMG[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CFGREGIMG
} [\emph{read-only}]: Configuration register image
\\
Image of the FPGA configuration register at address CFGREGADR (see Configuration Registers section in Xilinx UG380~\cite{ug380}); validated by IMGVALID bit
\end{small}
\item \begin{small}
{\bf
IMGVALID
} [\emph{read-only}]: Configuration register image valid
\\
1 -- CFGREGIMG valid \\ 0 -- CFGREGIMG not valid;
\end{small}
\item \begin{small}
{\bf
WDTO
} [\emph{read/write}]: MultiBoot FSM stalled at one point and was reset by FSM watchdog
\\
1 -- FSM watchdog fired \\ 0 -- FSM watchdog has not fired
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{GBBAR -- Golden Bitstream Base Address Register}
\label{app:multiboot-regs-gbbar}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
BITS
} [\emph{read/write}]: Bits of GBBAR register
\\
31..24 -- Read or fast-read OPCODE of the flash chip (obtain it from the flash chip datasheet) \\ 23..0 -- Golden bitstream address in flash
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{MBBAR -- MultiBoot Bitstream Base Address Register}
\label{app:multiboot-regs-mbbar}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
BITS
} [\emph{read/write}]: Bits of MBBAR register
\\
31..24 -- Read or fast-read OPCODE of the flash chip (obtain it from the flash chip datasheet) \\ 23..0 -- MultiBoot bitstream start address in flash
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\subsubsection{FAR -- Flash Access Register}
\label{app:multiboot-regs-far}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}READY} & \multicolumn{1}{|c|}{\cellcolor{gray!25}CS} & \multicolumn{1}{|c|}{\cellcolor{gray!25}XFER} & \multicolumn{2}{|c|}{\cellcolor{gray!25}NBYTES[1:0]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}DATA[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}DATA[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}DATA[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
DATA
} [\emph{read/write}]: Flash data field
\\
23..16 -- DATA[2]; after an SPI transfer, this register contains the value of data byte 2 read from the flash \\ 15..8 -- DATA[1]; after an SPI transfer, this register contains the value of data byte 1 read from the flash \\ 7..0 -- DATA[0]; after an SPI transfer, this register contains the value of data byte 0 read from the flash
\end{small}
\item \begin{small}
{\bf
NBYTES
} [\emph{read/write}]: Number of DATA fields to send and receive in one transfer:
\\
0x0 -- Send 1 byte (DATA[0]) \\ 0x1 -- Send 2 bytes (DATA[0], DATA[1]) \\ 0x2 -- Send 3 bytes (DATA[0], DATA[1], DATA[2])
\end{small}
\item \begin{small}
{\bf
XFER
} [\emph{write-only}]: Start transfer to and from flash
\\
1 -- Start transfer \\ 0 -- Idle
\end{small}
\item \begin{small}
{\bf
CS
} [\emph{read/write}]: Chip select bit
\\
1 - Flash chip selected (CS pin low) \\ 0 - Flash chip not selected (CS pin is high)
\end{small}
\item \begin{small}
{\bf
READY
} [\emph{read-only}]: Flash access ready
\\
1 - Flash access completed \\ 0 - Flash access in progress
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
conv-common-gw-4b29f81745c3c0a760395b21be78b872bfc85060/ip_cores/ 0000775 0000000 0000000 00000000000 13055247455 0022762 5 ustar 00root root 0000000 0000000 conv-common-gw-4b29f81745c3c0a760395b21be78b872bfc85060/ip_cores/general-cores/ 0000775 0000000 0000000 00000000000 13055247455 0025510 5 ustar 00root root 0000000 0000000 conv-common-gw-4b29f81745c3c0a760395b21be78b872bfc85060/modules/ 0000775 0000000 0000000 00000000000 13055247455 0022627 5 ustar 00root root 0000000 0000000 conv-common-gw-4b29f81745c3c0a760395b21be78b872bfc85060/modules/Manifest.py 0000664 0000000 0000000 00000000265 13055247455 0024752 0 ustar 00root root 0000000 0000000 files = [
"conv_regs.vhd",
"conv_pulse_gen.vhd",
"conv_man_trig.vhd",
"conv_ring_buf.vhd",
"conv_pulse_timetag.vhd",
"conv_reset_gen.vhd"
];
conv-common-gw-4b29f81745c3c0a760395b21be78b872bfc85060/modules/README 0000664 0000000 0000000 00000003025 13055247455 0023507 0 ustar 00root root 0000000 0000000 conv_regs.wb
============
If you change the FIFO width in the top-level conv_ttl_blo.vhd, you need to
also change the width of the USEDW field.
conv_regs.vhd
=============
You need to make some changes to this file after EVERY RUN of wbgen2:
1. Add the following output port declaration after the reg_tbmr_wrtag_i port:
-- Tag buffer read request, asserted when reading from TBMR
reg_tb_rd_req_p_o : out std_logic;
2. Assign the port FOUR TIMES in the register bank process:
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
-- [...]
reg_tb_rd_req_p_o <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
-- [...]
reg_tb_rd_req_p_o <= '0';
ack_in_progress <= '0';
else
-- [...]
reg_tb_rd_req_p_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(3 downto 0) is
[...]
when "1011" =>
if (wb_we_i = '1') then
end if;
reg_tb_rd_req_p_o <= '1';
rddata_reg(5 downto 0) <= reg_tbmr_chan_i;
rddata_reg(31) <= reg_tbmr_wrtag_i;
[...]
conv-common-gw-4b29f81745c3c0a760395b21be78b872bfc85060/modules/conv_burst_ctrl.vhd 0000664 0000000 0000000 00000033545 13055247455 0026554 0 ustar 00root root 0000000 0000000 --==============================================================================
-- CERN (BE-CO-HT)
-- Burst mode control module
--==============================================================================
--
-- author: Denia Bouhired (denia.bouhired@cern.ch)
--
-- Date of creation: 19-09-2016
--
-- version: 1.0
--
-- description:
-- This module serves as a burst mode controller. When pulses of pre-defined length (250 ns) arrive, this module evaluates whether the module needs some "cool-off" time every burst_length number of pulses. Burst-length is the maximum number of pulses the board can handle at maximum frequency 2MHz and is determined through direct laboratory measurements on board prototypes. It is considered a pure hardware limitation. For version 1 this is set to absolute maximum of 1000 but the generic value can be changed for lower values.
-- dependencies:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 19-09-2016 Denia Bouhired File created.
--
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- use work.gencores_pkg.all;
-- use work.wishbone_pkg.all;
use work.conv_common_gw_pkg.all;
entity conv_burst_ctrl is
generic
(
-- Short pulse width, in number of clk_i cycles
-- Default short pulse width (20 MHz clock): 250 ns = 5 clk cycles
g_pwidth : natural range 2 to 40 := 5;
-- Duty cycle divider: D = 1/g_duty_cycle_div
g_duty_cycle_div : natural := 200;
-- Number of pulses allowed before decision is made on whether to continue burst
-- Maximum number of pulses that can be received at the worst case 2MHz scenario
g_max_burst_len : natural := 1000; -- Check every "g_eval_burst_len" pulses
-- Burst is evaluated after g_max_burst_len or after a timeout g_burst_timeout set to 1 s.
--g_cnt_size : natural := 32;
g_burst_timeout : natural := 200000 -- 20000000 corresponds to 1 second timeout
-- 60000 corresponds to 3ms timeout
);
port
(
-- Clock and active-low reset inputs
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Enable input, pulse generation is enabled when '1'
en_i : in std_logic;
pulse_burst_i : in std_logic;
pulse_burst_o : out std_logic;
-- Burst error output, pulses high for one clock cycle when a pulse arrives
-- within a burst rejection phase
burst_err_p_o : out std_logic
);
end entity conv_burst_ctrl;
architecture behav of conv_burst_ctrl is
--============================================================================
-- Type declarations
--============================================================================
type t_state is (
IDLE, --Idle state wait for pulse to arrive
GEN_PULSE_ON, --Continue generating pulses and counting them
GEN_PULSE_OFF, --And count pulse OFF time
REJ_PULSE --Reject pulses and start cool-off period
);
--============================================================================
-- Constant declarations
--============================================================================
-- This bit can be done by adding second counter to count pulse on time
constant c_average_pulse_off : natural := (g_duty_cycle_div)*g_pwidth; -- 250 ns * (200)
constant c_max_burst_rej : natural := g_max_burst_len*c_average_pulse_off; -- (250ns * (200)) *1000
--============================================================================
-- Function and procedure declarations
--============================================================================
--============================================================================
-- Signal declarations
--============================================================================
signal burst_ctrl_rst : std_logic;
-- Pulse burst trigger
signal pulse_train_in : std_logic;
--signal pulse_redge_p : std_logic;
--signal pulse_burst_sf : std_logic;
-- Pulse, pulse ON/OFF, burst length counters
signal pulse_cnt : unsigned(31 downto 0); -- Pulse counter
---signal cumul_pulse_on_c : unsigned(g_cnt_size-1 downto 0); -- Cumulative PULSE ON counter
---signal cumul_pulse_off_c : unsigned(g_cnt_size-1 downto 0); -- Cumulative PULSE OFF counter
signal cumul_burst_time : unsigned(31 downto 0); -- Cumulative burst time (ON and OFF)
signal burst_rq_off_c : unsigned(31 downto 0); -- Required rejection time for current burst
-- Flag new pulse
signal new_pulse : boolean;
--Flag burst rejection
--signal rej_active : boolean;
-- FSM signal
signal state : t_state;
signal nxt_state : t_state;
signal pulse_train_in_d0 : std_logic;
signal pulse_train_in_r_edge_p : std_logic;
--==============================================================================
-- architecture begin
--==============================================================================
begin
-- Generate the pulse on rising edge of pulse_burst_i
p_pulse_redge: process (burst_ctrl_rst, pulse_burst_i, en_i)
begin
if (burst_ctrl_rst = '1') then
pulse_train_in <= '0';
else
-- if (en_i = '1') then
pulse_train_in <= pulse_burst_i;
-- end if;
end if;
end process p_pulse_redge;
p_pulse_redge_detect : process (clk_i) is
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
pulse_train_in_d0 <= '0';
pulse_train_in_r_edge_p <= '0';
else
pulse_train_in_d0 <= pulse_burst_i;
pulse_train_in_r_edge_p <= pulse_burst_i and (not pulse_train_in_d0);
end if;
end if;
end process p_pulse_redge_detect;
-- Synchronize the trigger in clk_i domain
-- cmp_sync_ffs : gc_sync_ffs
-- generic map
-- (
-- g_sync_edge => "positive"
-- )
-- port map
-- (
-- clk_i => clk_i,
-- rst_n_i => rst_n_i,
-- data_i => pulse_burst,
-- ppulse_o => pulse_redge_p
-- );
--pulse_redge_p <= pulse_burst;
-- process (clk_i)
-- begin
-- if rising_edge(clk_i) then
pulse_burst_o <= pulse_train_in;
-- end if;
-- end process;
--============================================================================
-- Burst length adjustment logic
--============================================================================
--Synchronous procees to define state conditions
p_fsm_transitions: process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
state <= IDLE;
elsif (en_i = '1') then
state <= nxt_state;
end if;
end if;
end process;
-- FSM States
p_FSM_states: process(state, pulse_train_in, cumul_burst_time, pulse_cnt, burst_rq_off_c)
begin
case state is
---------------------------------------------------------------------
-- IDLE
---------------------------------------------------------------------
-- Clear all values and go to pulse generation state when the
-- appropriate input arrives
---------------------------------------------------------------------
when IDLE =>
if (pulse_train_in = '1') then
nxt_state <= GEN_PULSE_ON;
else
nxt_state <= state;
end if;
---------------------------------------------------------------------
-- GEN_PULSE_ON
---------------------------------------------------------------------
-- When a new pulse arrives increment the pulse ON cycle counter and the pulse ON counter
-- Got to GEN_PULSE_OFF state when the pulse is OFF
---------------------------------------------------------------------
when GEN_PULSE_ON =>
if (pulse_train_in = '1') then
nxt_state <= state;
else
nxt_state <= GEN_PULSE_OFF;
end if;
---------------------------------------------------------------------
-- GEN_PULSE_OFF
---------------------------------------------------------------------
-- Count the number of cycles of pulse OFF
-- Go to GEN_PULSE_ON state when new pulse arrives
-- If the maximum number of pulses per burst is reached, go to REJ_PULSE state
-- If the the burst time out is reached got to TIMEOUT state
---------------------------------------------------------------------
when GEN_PULSE_OFF =>
-- If maximum number of consecutive pulses is reached start rejection phase
if (pulse_cnt = g_max_burst_len or cumul_burst_time >= g_burst_timeout) then
if (cumul_burst_time < burst_rq_off_c) then
nxt_state <= REJ_PULSE;
else
nxt_state <= IDLE;
end if;
elsif (pulse_train_in = '1' ) then
nxt_state <= GEN_PULSE_ON;
end if;
---------------------------------------------------------------------
-- REJ_PULSE
---------------------------------------------------------------------
-- Start pulse rejection until c_max_burst_rej time is reached
-- the go back to IDLE state
---------------------------------------------------------------------
when REJ_PULSE =>
if (cumul_burst_time >= burst_rq_off_c) then
nxt_state <= IDLE;
else
nxt_state <= state;
end if;
when others =>
nxt_state <= IDLE;
end case;
end process p_FSM_states;
-- FSM Outputs
p_FSM_outputs: process(clk_i)
begin
if rising_edge (clk_i) then
case state is
---------------------------------------------------------------------
-- IDLE
---------------------------------------------------------------------
-- Clear all values and go to pulse generation state when the
-- appropriate input arrives
---------------------------------------------------------------------
when IDLE =>
pulse_cnt <= (others => '0');
cumul_burst_time <= (others => '0');
burst_rq_off_c <= (others => '0');
burst_ctrl_rst <= '0';
new_pulse <= false;
--rej_active <= false;
if (pulse_train_in = '1') then
cumul_burst_time <= cumul_burst_time + 1;
new_pulse <= true;
end if;
---------------------------------------------------------------------
-- GEN_PULSE_ON
---------------------------------------------------------------------
-- When a new pulse arrives increment the pulse ON cycle counter and the pulse ON counter
-- Got to GEN_PULSE_OFF state when the pulse is OFF
---------------------------------------------------------------------
when GEN_PULSE_ON =>
cumul_burst_time <= cumul_burst_time + 1;
if (new_pulse) then -- count only new pulses, once
pulse_cnt <= pulse_cnt + 1;
new_pulse <= false; -- A new pulse has already been counted
burst_rq_off_c <= burst_rq_off_c + c_average_pulse_off;
end if;
---------------------------------------------------------------------
-- GEN_PULSE_OFF
---------------------------------------------------------------------
-- Count the number of cycles of pulse OFF
-- Go to GEN_PULSE_ON state when new pulse arrives
-- If the maximum number of pulses per burst is reached, go to REJ_PULSE state
-- If the the burst time out is reached got to TIMEOUT state
---------------------------------------------------------------------
when GEN_PULSE_OFF =>
cumul_burst_time <= cumul_burst_time + 1;
-- If maximum number of consecutive pulses is reached start rejection phase
if (pulse_cnt = g_max_burst_len or cumul_burst_time >= g_burst_timeout) then
if (cumul_burst_time < burst_rq_off_c) then
burst_ctrl_rst <= '1';
end if;
elsif (pulse_train_in = '1' ) then
new_pulse <= true;
end if;
---------------------------------------------------------------------
-- REJ_PULSE
---------------------------------------------------------------------
-- Start pulse rejection until c_max_burst_rej time is reached
-- the go back to IDLE state
---------------------------------------------------------------------
when REJ_PULSE =>
if (cumul_burst_time >= burst_rq_off_c) then
burst_ctrl_rst <= '0';
else
cumul_burst_time <= cumul_burst_time + 1;
end if;
-- Error pulse is generated for one clock cycle each time a pulse arrives during rejection mode
burst_err_p_o <= '0';
if pulse_train_in_r_edge_p = '1' then
burst_err_p_o <= '1';
end if;
end case;
end if;
end process p_FSM_outputs;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
conv-common-gw-4b29f81745c3c0a760395b21be78b872bfc85060/modules/conv_burst_ctrl_v1.vhd 0000664 0000000 0000000 00000027267 13055247455 0027166 0 ustar 00root root 0000000 0000000 --==============================================================================
-- CERN (BE-CO-HT)
-- Burst mode control module
--==============================================================================
--
-- author: Denia Bouhired (denia.bouhired@cern.ch)
--
-- Date of creation: 19-09-2016
--
-- version: 1.0
--
-- description:
-- This module serves as a burst mode controller. When pulses of pre-defined length (250 ns) arrive, this module evaluates whether the module needs some "cool-off" time every burst_length number of pulses. Burst-length is the maximum number of pulses the board can handle at maximum frequency 2MHz and is determined through direct laboratory measurements on board prototypes. It is considered a pure hardware limitation. For version 1 this is set to absolute maximum of 1000 but the generic value can be changed for lower values.
-- dependencies:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 19-09-2016 Denia Bouhired File created.
--
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.conv_common_gw_pkg.all;
entity conv_burst_ctrl is
generic
(
-- Short pulse width, in number of clk_i cycles
-- Default short pulse width (20 MHz clock): 250 ns = 5 clk cycles
g_pwidth : natural range 2 to 40 := 5;
-- Duty cycle divider: D = 1/g_duty_cycle_div
g_duty_cycle_div : natural := 200;
-- Number of pulses allowed before decision is made on whether to continue burst
-- Maximum number of pulses that can be received at the worst case 2MHz scenario
g_max_burst_len : natural := 1000; -- Check every "g_eval_burst_len" pulses
-- Burst is evaluated after g_max_burst_len or after a timeout g_burst_timeout set to 1 s.
--g_cnt_size : natural := 32;
g_burst_timeout : natural := 200000 -- 20000000 corresponds to 1 second timeout
-- 60000 corresponds to 3ms timeout
);
port
(
-- Clock and active-low reset inputs
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Enable input, pulse generation is enabled when '1'
en_i : in std_logic;
pulse_burst_i : in std_logic;
pulse_burst_o : out std_logic;
-- Burst error output, pulses high for one clock cycle when a pulse arrives
-- within a burst rejection phase
burst_err_p_o : out std_logic
);
end entity conv_burst_ctrl;
architecture behav of conv_burst_ctrl is
--============================================================================
-- Type declarations
--============================================================================
type t_state is (
IDLE, --Idle state wait for pulse to arrive
GEN_PULSE_ON, --Continue generating pulses and counting them
GEN_PULSE_OFF, --And count pulse OFF time
REJ_PULSE --Reject pulses and start cool-off period
);
--============================================================================
-- Constant declarations
--============================================================================
-- This bit can be done by adding second counter to count pulse on time
constant c_average_pulse_off : natural := (g_duty_cycle_div)*g_pwidth; -- 250 ns * (200)
constant c_max_burst_rej : natural := g_max_burst_len*c_average_pulse_off; -- (250ns * (200)) *1000
--============================================================================
-- Function and procedure declarations
--============================================================================
--============================================================================
-- Signal declarations
--============================================================================
signal burst_ctrl_rst : std_logic;
-- Pulse burst trigger
signal pulse_train_in : std_logic;
--signal pulse_redge_p : std_logic;
--signal pulse_burst_sf : std_logic;
-- Pulse, pulse ON/OFF, burst length counters
signal pulse_cnt : unsigned(31 downto 0); -- Pulse counter
---signal cumul_pulse_on_c : unsigned(g_cnt_size-1 downto 0); -- Cumulative PULSE ON counter
---signal cumul_pulse_off_c : unsigned(g_cnt_size-1 downto 0); -- Cumulative PULSE OFF counter
signal cumul_burst_time : unsigned(31 downto 0); -- Cumulative burst time (ON and OFF)
signal burst_rq_off_c : unsigned(31 downto 0); -- Required rejection time for current burst
-- Flag new pulse
signal new_pulse : boolean;
--Flag burst rejection
signal rej_active : boolean;
-- FSM signal
signal state : t_state;
--==============================================================================
-- architecture begin
--==============================================================================
begin
-- Generate the pulse on rising edge of pulse_burst_i
p_pulse_redge: process(burst_ctrl_rst, pulse_burst_i)
begin
if (burst_ctrl_rst = '1') then
pulse_train_in <= '0';
elsif rising_edge(pulse_burst_i) then
if (en_i = '1' and not rej_active) then
pulse_train_in <= pulse_burst_i;
burst_err_p_o <= '0';
else
pulse_train_in <= '0';
burst_err_p_o <= '1';
end if;
else
pulse_train_in <= '0';
burst_err_p_o <= '0';
end if;
end process p_pulse_redge;
-- Synchronize the trigger in clk_i domain
-- cmp_sync_ffs : gc_sync_ffs
-- generic map
-- (
-- g_sync_edge => "positive"
-- )
-- port map
-- (
-- clk_i => clk_i,
-- rst_n_i => rst_n_i,
-- data_i => pulse_burst,
-- ppulse_o => pulse_redge_p
-- );
--pulse_redge_p <= pulse_burst;
process (clk_i)
begin
if rising_edge(clk_i) then
pulse_burst_o <= pulse_train_in;
end if;
end process;
--============================================================================
-- Burst length adjustment logic
--============================================================================
-- Generate FSM logic
p_burst_length: process(clk_i)
begin
if rising_edge (clk_i) then -- ***CHECK WHAT ELSE NEEDS TO BE RESET
if (rst_n_i = '0') then
state <= IDLE;
burst_ctrl_rst <= '1';
--pulse_burst_sf <= '0';
pulse_cnt <= (others => '0');
---cumul_pulse_on_c <= (others => '0');
---cumul_pulse_off_c <= (others => '0');
cumul_burst_time <= (others => '0');
burst_rq_off_c <= (others => '0');
new_pulse <= false;
rej_active <= false;
--burst_err_p_o <= '0';
elsif (en_i = '1') then
--pulse_burst_sf <= pulse_burst;
case state is
---------------------------------------------------------------------
-- IDLE
---------------------------------------------------------------------
-- Clear all values and go to pulse generation state when the
-- appropriate input arrives
---------------------------------------------------------------------
when IDLE =>
--pulse_burst_sf <= pulse_burst;
pulse_cnt <= (others => '0');
---cumul_pulse_on_c <= (others => '0');
---cumul_pulse_off_c <= (others => '0');
cumul_burst_time <= (others => '0');
burst_rq_off_c <= (others => '0');
burst_ctrl_rst <= '0';
rej_active <= false;
if (pulse_train_in = '1') then
new_pulse <= true;
state <= GEN_PULSE_ON;
---cumul_pulse_on_c <= cumul_pulse_on_c + 1;
cumul_burst_time <= cumul_burst_time + 1;
end if;
---------------------------------------------------------------------
-- GEN_PULSE_ON
---------------------------------------------------------------------
-- When a new pulse arrives increment the pulse ON cycle counter and the pulse ON counter
-- Got to GEN_PULSE_OFF state when the pulse is OFF
---------------------------------------------------------------------
when GEN_PULSE_ON =>
----cumul_burst_time <= cumul_pulse_on_c + cumul_pulse_off_c + 1;
cumul_burst_time <= cumul_burst_time + 1;
if (pulse_train_in = '1') then
---cumul_pulse_on_c <= cumul_pulse_on_c + 1;
if (new_pulse) then -- count only new pulses, once
pulse_cnt <= pulse_cnt + 1;
new_pulse <= false; -- A new pulse has already been counted
burst_rq_off_c <= burst_rq_off_c + c_average_pulse_off;
end if;
else
state <= GEN_PULSE_OFF;
---cumul_pulse_off_c <= cumul_pulse_off_c + 1;
end if;
---------------------------------------------------------------------
-- GEN_PULSE_OFF
---------------------------------------------------------------------
-- Count the number of cycles of pulse OFF
-- Go to GEN_PULSE_ON state when new pulse arrives
-- If the maximum number of pulses per burst is reached, go to REJ_PULSE state
-- If the the burst time out is reached got to TIMEOUT state
---------------------------------------------------------------------
when GEN_PULSE_OFF =>
----cumul_burst_time <= cumul_pulse_on_c + cumul_pulse_off_c + 1;
cumul_burst_time <= cumul_burst_time + 1;
if (pulse_train_in = '1' ) then
new_pulse <= true; --waiting for new pulse
state <= GEN_PULSE_ON;
---cumul_pulse_on_c <= cumul_pulse_on_c + 1;
-- If maximum number of consecutive pulses is reached start rejection phase
elsif (pulse_cnt = g_max_burst_len or cumul_burst_time >= g_burst_timeout) then
if (cumul_burst_time < burst_rq_off_c) then
rej_active <= true;
state <= REJ_PULSE;
end if;
else
---cumul_pulse_off_c <= cumul_pulse_off_c + 1;
end if;
---------------------------------------------------------------------
-- REJ_PULSE
---------------------------------------------------------------------
-- Start pulse rejection until c_max_burst_rej time is reached
-- the go back to IDLE state
---------------------------------------------------------------------
when REJ_PULSE =>
if (cumul_burst_time >= burst_rq_off_c) then
rej_active <= false;
state <= IDLE;
else
cumul_burst_time <= cumul_burst_time + 1;
end if;
when others =>
state <= IDLE;
end case;
end if;
end if;
end process p_burst_length;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
conv-common-gw-4b29f81745c3c0a760395b21be78b872bfc85060/modules/conv_dyn_burst_ctrl.vhd 0000664 0000000 0000000 00000026443 13055247455 0027425 0 ustar 00root root 0000000 0000000 --==============================================================================
-- CERN (BE-CO-HT)
-- Burst mode control module
-- Copyright CERN 2017
--==============================================================================
--
-- author: Denia Bouhired (denia.bouhired@cern.ch)
--
-- Date of creation: 19-09-2016
--
-- version: 1.0
--
-- Description:
-- This module serves as a burst mode controller. When pulses of
-- pre-defined length (250 ns or 1.2us) arrive, depending on the frequency, the
-- module will allow the pulse to go through for a pre-defined amount of
-- time, before going into pulse rejection mode. The rejection lasts for
-- the time it takes for the "temperature" to reach the upper limit
-- g_max_temp. For each frequency, the time of failure selected
-- corresponds to the time it takes to reach g_max_temp for pulses of a given
-- frequency.
-- The array of values representing the thermal properties at the pulse level
-- is given as the array of integers temp_decre_step. This array of values is
-- generated in pre-processing via python script (*link to be added*). These
-- values correspond to the thermal model of the board components. They are
-- different for short 250ns pulses and long 1.2us pulses.
-- Any modification to the board specification which would change the
-- high frequency operation behaviour, would require changing the 3
-- parameters g_1_pulse_temp_rise, g_max_temp and t_temp_decre_step. These
-- are generated using the Python file (*link to be added*).
-- dependencies:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.conv_common_gw_pkg.all;
----------------------------------------------------------------------------
-- ENTITY DECLARATION
----------------------------------------------------------------------------
entity conv_dyn_burst_ctrl is
generic
(
-- Fixed pulse width
g_pwidth : natural range 2 to 40 := 5;
-- Array of decrement values derived from the choses thermal model
-- The following t_temp_decre_step values correspond to "1s, 6.5s, 10s, 26s,
-- 36.66s and continuous" for pulsing for frequencies
-- 2MHz, 1.33MHz, 1MHz, 800kHz, 667 kHz and 571kHz respectively.
g_temp_decre_step : t_temp_decre_step :=
(0,0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0);
--Scaled temperature rise resulting from a single pulse.
g_1_pulse_temp_rise :in unsigned (19 downto 0) := x"01388"; --5000
-- Scaled maximum temperature ceiling for pulse inhibition
g_max_temp :in unsigned (39 downto 0) := x"02540BE400" --10^10
);
port
(
-- Clock and active-low reset inputs
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Enable input, high frequency repetition is enabled when '1'
en_i : in std_logic;
-- Asynchronous input pulse with rising and falling edges
pulse_burst_i : in std_logic;
pulse_r_edge_p_i : in std_logic;
pulse_f_edge_p_i : in std_logic;
-- Temp_rise is output for external probing
temp_rise_o : out unsigned (39 downto 0) ;
-- Dynamic temperature-controlled ouput pulse train.
pulse_burst_o : out std_logic;
-- Burst error output, pulses high for one clock cycle when a pulse arrives
-- within a burst rejection phase
burst_err_p_o : out std_logic
);
end entity conv_dyn_burst_ctrl;
----------------------------------------------------------------------------
-- ARCHITECTURE
----------------------------------------------------------------------------
architecture behav of conv_dyn_burst_ctrl is
type t_state is (
IDLE,
PULSE_REPEAT,
PULSE_REJECT
);
signal burst_ctrl_rst : std_logic;
signal temp_rise : unsigned (39 downto 0) ;
signal single_cycle_cnt : integer;
signal n_cycle_cnt : integer range 1 to g_temp_decre_step'LENGTH;
signal thermal_array_lgth :natural := 7;
signal thermal_res : natural; -- thermal resolution in clock cycles
signal state : t_state;
signal nxt_state : t_state;
signal s_pulse_reject, s_pulse_repeat : std_logic;
begin
thermal_array_lgth <= 7 when g_pwidth = 5 else 16;
thermal_res <= g_pwidth; --Resolution depends on i/p pulse width
-- Output from module depends on burst_ctrl_rst and en_i
---------------------------------------------------------
pulse_burst_o <= '0' when burst_ctrl_rst = '1' else pulse_burst_i and en_i;
temp_rise_o <= temp_rise;
-----------------------------------------------------------------------------
-- Finite State Machine FSM
-----------------------------------------------------------------------------
-- Finite State Machine to control pulse repetition as a function of rising
-- board temperature. The FSM relies on temp_rise counter for state transitions
-----------------------------------------------------------------------------
-- Process to trigger state transitions
----------------------------------------
p_fsm_transitions: process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
state <= IDLE;
elsif (en_i = '1') then
state <= nxt_state;
end if;
end if;
end process;
-- Process to define FSM states
--------------------------------
p_thermal_fsm_states : process (state, pulse_r_edge_p_i, pulse_f_edge_p_i,
n_cycle_cnt, temp_rise, en_i )
begin
case state is
-------------------------------------------------------------------------
-- The FSM is IDLE, when the board is reset
-------------------------------------------------------------------------
when IDLE =>
if en_i = '1' and pulse_r_edge_p_i = '1' then
nxt_state <= PULSE_REPEAT;
else
nxt_state <= IDLE;
end if;
-------------------------------------------------------------------------
-- PULSE_REPEAT pulses are repeated as long as the temperature is below
-- maximum g_max_temp.
-- While the temperature counter temp_rise is above 0, the time between
-- 2 pulses is used to decrement it, i.e. to cool down.
-------------------------------------------------------------------------
when PULSE_REPEAT =>
if temp_rise <= g_max_temp then
nxt_state <= PULSE_REPEAT;
else
nxt_state <= PULSE_REJECT;
end if;
-----------------------------------------------oo-----------------------
-- PULSE_REJECT applies when a new pulse causes temperature to exceed
-- maximum value
-- i.e. temp_rise >= g_max_temp.
------------------------------------------------------------------------
when PULSE_REJECT =>
if (pulse_f_edge_p_i = '1' and temp_rise <= g_max_temp) OR
temp_rise = 0 then
nxt_state <= PULSE_REPEAT;
else
nxt_state <= PULSE_REJECT;
end if;
when others =>
nxt_state <= IDLE;
end case;
end process p_thermal_fsm_states;
-- Process to define FSM outputs
--------------------------------
p_thermal_fsm_outputs : process (state, pulse_r_edge_p_i)
begin
-------------------------------------------------------------------------
-- In the idle state all outputs are reset
-------------------------------------------------------------------------
case state is
when IDLE =>
burst_ctrl_rst <= '0';
burst_err_p_o <= '0';
s_pulse_reject <= '0';
s_pulse_repeat <= '0';
--------------------------------------------------------------------------
-- In PULSE_REPEAT pulses the input pulse is copied to the output and
-- the state flag s_pulse_repeat is set
--------------------------------------------------------------------------
when PULSE_REPEAT =>
burst_err_p_o <= '0';
burst_ctrl_rst <= '0';
s_pulse_repeat <= '1';
s_pulse_reject <= '0';
---------------------------------------------------------------------------
-- PULSE_REJECT sets burst_ctrl_rst to 1 to cutoff the output and sets the
-- error pulse
---------------------------------------------------------------------------
when PULSE_REJECT =>
burst_err_p_o <= pulse_r_edge_p_i;
burst_ctrl_rst <= '1';
s_pulse_reject <= '1';
s_pulse_repeat <= '0';
when others =>
burst_ctrl_rst <= '0';
burst_err_p_o <= '0';
s_pulse_reject <= '0';
s_pulse_repeat <= '0';
end case;
end process p_thermal_fsm_outputs;
-- Process to count in n clk cycles steps
-- single_cycle_cnt counts clock cycles. When it reaches the thermal resolution
-- (pulse width dependent) it increments n_cycle_cnt by 1 and single_cycle_cnt
-- is reset to 1 again. n_cycle_cnt is reset to 1 only when a new pulse arrives
-- and pulse output inhibition is not active.
---------------------------------------------------------------------------
p_n_cycle_cnt : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
single_cycle_cnt <= 1;
n_cycle_cnt <= 1;
else
-- Reset counters in the event of a new pulse only
-- when pulse rejection is not active
if (pulse_r_edge_p_i = '1' and burst_ctrl_rst = '0') then --OR
--(pulse_f_edge_p_i = '1' and n_cycle_cnt /= 1) then
single_cycle_cnt <= 1;
n_cycle_cnt <= 1;
else
--count clk cycles
single_cycle_cnt <= single_cycle_cnt + 1;
if single_cycle_cnt = thermal_res then
if n_cycle_cnt < thermal_array_lgth then
-- increment every n=thermal_res clk cycles
n_cycle_cnt <= n_cycle_cnt + 1;
end if;
single_cycle_cnt <= 1;
end if;
end if;
end if;
end if;
end process p_n_cycle_cnt;
-- Process to output temperature rise. When a new pulse arrives,
-- temp_rise rises at the falling edge. Between pulses, temp_rise is
-- decremented according to the thermal model.
------------------------------------------------------------------------------
p_temp_rise : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
temp_rise <= (others => '0');
else
if s_pulse_repeat = '1' then
if pulse_f_edge_p_i ='1' then
temp_rise <= temp_rise + g_1_pulse_temp_rise;
else
if temp_rise >= g_temp_decre_step(n_cycle_cnt-1) then
temp_rise <= temp_rise - to_unsigned(g_temp_decre_step(n_cycle_cnt-1), 40);
else
temp_rise <= (others => '0');
end if;
end if;
elsif s_pulse_reject = '1' and temp_rise > 0 then
if temp_rise >= g_temp_decre_step(n_cycle_cnt-1) then
temp_rise <= temp_rise - to_unsigned(g_temp_decre_step(n_cycle_cnt-1), 40);
else
temp_rise <= (others => '0');
end if;
end if;
end if;
end if;
end process p_temp_rise;
end architecture behav; conv-common-gw-4b29f81745c3c0a760395b21be78b872bfc85060/modules/conv_dyn_burst_ctrl_long_pulse.vhd 0000664 0000000 0000000 00000021047 13055247455 0031647 0 ustar 00root root 0000000 0000000 --==============================================================================
-- CERN (BE-CO-HT)
-- Burst mode control module
--==============================================================================
--
-- author: Denia Bouhired (denia.bouhired@cern.ch)
--
-- Date of creation: 19-09-2016
--
-- version: 1.0
--
-- description:
-- This module serves as a burst mode controller. When pulses of pre-defined length (250 ns) arrive, this module evaluates whether the module needs some "cool-off" time every burst_length number of pulses. Burst-length is the maximum number of pulses the board can handle at maximum frequency 2MHz and is determined through direct laboratory measurements on board prototypes. It is considered a pure hardware limitation. For version 1 this is set to absolute maximum of 1000 but the generic value can be changed for lower values.
-- dependencies:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 19-09-2016 Denia Bouhired File created.
-- 11-01-2017 Denia Bouhired Small modifications to improve code.
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.conv_common_gw_pkg.all;
entity conv_dyn_burst_ctrl is
generic
(
-- Fixed pulse width set to 5 clock cycles = 5* 50ns = 250 ns
g_pwidth : natural range 2 to 40 := 5;
-- Scaled temperature rise resulting from single pulse. This number can be defined empirically or derived from temperature measurements on the board.
g_1_pulse_temp_rise :in unsigned (19 downto 0) := x"0A410";
-- Scaled maximum temperature ceiling before pulse inhibition is necessary to lower temperature
--g_max_temp :in unsigned (39 downto 0) := x"174876E800"
g_max_temp :in unsigned (39 downto 0) := x"00000186A0"--100000
);
port
(
-- Clock and active-low reset inputs
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Enable input, pulse generation is enabled when '1'
en_i : in std_logic;
--Input pulse burst or pulse train
pulse_burst_i : in std_logic;
--Dynamically controlled ouput pulse train.
pulse_burst_o : out std_logic;
-- output used for debugging. OUGHT TO BE DELETED
temp_rise_c : out unsigned (39 downto 0) ;
-- Burst error output, pulses high for one clock cycle when a pulse arrives
-- within a burst rejection phase
burst_err_p_o : out std_logic
);
end entity conv_dyn_burst_ctrl;
architecture behav of conv_dyn_burst_ctrl is
type t_temp_decre is array (0 to 14) of integer;
--============================================================================
-- Function and procedure declarations
--============================================================================
function f_temp_resolution (pwidth : natural) return natural is
begin
if pwidth = 5 then --250ns wide pulses
return 5;
else
return 24; --1.2us wide pulses
end if;
end function f_temp_resolution;
--============================================================================
-- Signal declarations
--============================================================================
--signal temp_decre : t_temp_decre := (0, 769, 31, 104, 14, 82,0,0);
signal temp_decre : t_temp_decre := (0,0,0,0,0,0,0,5750,100,79,13,12,4,5,13);
signal burst_ctrl_rst : std_logic;
signal pulse_train_in : std_logic;
signal temp_rise : unsigned (39 downto 0) ;
signal test : integer ;
signal temp_fall : unsigned (39 downto 0) ;
signal single_cycle_cnt : integer;
signal n_cycle_cnt : integer;
signal pulse_train_in_d0 : std_logic;
signal pulse_train_in_r_edge_p : std_logic;
signal pulse_train_in_f_edge_p : std_logic;
constant thermal_res : natural := f_temp_resolution (g_pwidth); -- thermal resolution in clock cycles
begin
-- Generate the pulse on rising edge of pulse_burst_i
p_pulse_redge: process (burst_ctrl_rst, pulse_burst_i)
begin
--if rising_edge(clk_i) then
--TO DOooo consider moving within else statement
if (burst_ctrl_rst = '1') then
if falling_edge(pulse_burst_i) then --pulse_burst_i) then -- wait for pulse to finish before cutoff
--TODO why not use falling edge 1-clk-cycle pulse
pulse_train_in <= '0';
end if;
elsif (en_i = '1') then
pulse_train_in <= pulse_burst_i; --re-activate output only if input line is off
end if;
--end if;
--end if;
end process p_pulse_redge;
pulse_burst_o <= pulse_train_in; --copy controlled input burst to output
temp_rise_c <= temp_rise; --TODO to delete as output is not really necessary
-- TODO is it necessary since pulse should already be synchronised to clock domain?/
p_pulse_redge_detect : process (clk_i) is
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
pulse_train_in_d0 <= '0';
pulse_train_in_r_edge_p <= '0';
elsif (en_i='1') then
pulse_train_in_d0 <= pulse_burst_i;
pulse_train_in_r_edge_p <= pulse_burst_i and (not pulse_train_in_d0);
pulse_train_in_f_edge_p <= (not pulse_burst_i) and pulse_train_in_d0;
end if;
end if;
end process p_pulse_redge_detect;
p_n_cycle_cnt : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
single_cycle_cnt <= 1;
n_cycle_cnt <= 1;
else
if pulse_train_in_r_edge_p = '1' then --and burst_ctrl_rst = '0' then
--reset counters in the event of a new pulse
single_cycle_cnt <= 1;
n_cycle_cnt <= 1;
elsif pulse_train_in = '0' then --TODO change condition of if statement, try with falling edge
single_cycle_cnt <= single_cycle_cnt+1;
if single_cycle_cnt = thermal_res then
if n_cycle_cnt < 15 then
n_cycle_cnt <= n_cycle_cnt + 1;
end if;
single_cycle_cnt <= 1;
--temp_fall <= to_unsigned(temp_decre(n_cycle_cnt), 40);
end if;
end if;
end if;
end if;
end process p_n_cycle_cnt;
p_thermal_sim : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
temp_rise <= (others => '0');
burst_ctrl_rst <= '1';
burst_err_p_o <= '0';
else
if (temp_rise) >= 0 and ((temp_rise) <= (g_max_temp)) then
burst_err_p_o <= '0';
if pulse_train_in_f_edge_p = '1' then --wait until pulse finishes before repetition
burst_ctrl_rst <= '0';
elsif pulse_train_in_r_edge_p = '1' then --new pulse
if burst_ctrl_rst = '1' then
burst_err_p_o <= '1';
--end if;
--if burst_ctrl_rst = '0' then -- temperature less than maximum
else
temp_rise <= temp_rise + g_1_pulse_temp_rise;
--else ;
end if;
--burst_err_p_o <= '0';
--elsif signed(temp_rise) /= 0 and pulse_train_in = '0' then
elsif (temp_rise) /= 0 then --and pulse_burst_i = '0' then --temperature fall between pulses
test <= temp_decre(n_cycle_cnt-1);
if temp_rise > temp_decre(n_cycle_cnt-1) then
temp_rise <= temp_rise - to_unsigned(temp_decre(n_cycle_cnt-1), 40);
else
temp_rise <= (others => '0');
end if;
end if;
--elsif (signed(temp_rise) > signed(g_max_temp)) and pulse_train_in = '0' then -- and
elsif ((temp_rise) > (g_max_temp)) then -- and pulse_burst_i = '0' then -- and (pulse_train_in_f_edge_p = '1') then
burst_ctrl_rst <= '1';
burst_err_p_o <= '0';
if pulse_train_in_r_edge_p = '1' then
burst_err_p_o <= '1';
end if;
temp_rise <= temp_rise - temp_decre(n_cycle_cnt-1);
end if;
end if;
end if;
end process p_thermal_sim;
end architecture behav; conv-common-gw-4b29f81745c3c0a760395b21be78b872bfc85060/modules/conv_man_trig.vhd 0000664 0000000 0000000 00000016571 13055247455 0026171 0 ustar 00root root 0000000 0000000 --==============================================================================
-- CERN (BE-CO-HT)
-- Pulse trigger for pulse converter boards
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2014-01-28
--
-- version: 1.0
--
-- description:
-- This module generates a pulse for the conv_pulse_gen module for manually
-- triggering a debug pulse on a channel output. It works in conjunction
-- with the converter board registers component (conv_regs), from where it
-- obtains the value of the MPT (manual pulse trigger) field in the control
-- register.
--
-- To manually trigger a pulse, a magic sequence of numbers (0xde, 0xad, 0xbe,
-- 0xef) should first be sent to the MPT field, followed by the channel number
-- to send the pulse on. When the channel number is sent, a single pulse is
-- generated by the conv_pulse_gen component at the output.
--
-- The conv_man_trig module checks to see whether the proper magic sequence
-- is written the the MPT field using a simple FSM. The FSM advances when
-- the MPT field is written, if the MPT field corresponds to the proper byte
-- in the magic sequence. If at any time during the magic sequence the value
-- of the MPT field does not correspond to the expected value, the FSM returns
-- to IDLE.
--
-- After the magic sequence is received, the FSM waits for the channel number
-- to be written to the MPT. If a valid channel number is input, a pulse is
-- generated on this channel. The check of whether a valid number is input is
-- based on the g_nr_ttl_chan generic. Should an invalid channel number be
-- input, no error is reported and no pulse is generated.
--
-- The output trigger pulse is extended within the last state of the FSM, to
-- account for when the glitch filter of the conv_pulse_gen component is on.
-- To extend the pulse by an appropriate number of clock cycles, the length
-- of the conv_pulse_gen glitch filter should be input via the g_gf_len.
--
-- dependencies:
-- genram_pkg : git://ohwr.org/hdl-core-lib/general-cores.git
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2014-01-28 Theodor Stana File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.genram_pkg.all;
entity conv_man_trig is
generic
(
-- Number of conversion channels
g_nr_chan : positive := 6;
-- Length of pulse in clk_i cycles generated at trig_o output
g_pwidth : positive := 1
);
port
(
-- Clock, active-low inputs
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Control inputs from conv_regs
reg_ld_i : in std_logic;
reg_i : in std_logic_vector(7 downto 0);
-- Trigger output, g_pwidth long
trig_o : out std_logic_vector(g_nr_chan downto 1)
);
end entity conv_man_trig;
architecture behav of conv_man_trig is
--============================================================================
-- Type declarations
--============================================================================
-- Type for the "password" array
type t_pass_arr is array(integer range <>) of std_logic_vector(7 downto 0);
-- FSM type
type t_state is
(
IDLE,
PASS1,
PASS2,
PASS3,
GET_CHAN,
GEN
);
--============================================================================
-- Constant declarations
--============================================================================
constant c_pass_arr : t_pass_arr(0 to 3) := (x"de", x"ad", x"be", x"ef");
--============================================================================
-- Function and procedures declaration
--============================================================================
procedure f_change_state (
signal ld : in std_logic;
signal pass : in std_logic_vector(7 downto 0);
constant idx : in integer;
signal state : out t_state;
constant nstate : in t_state
) is
begin
if (ld = '1') then
if (pass = c_pass_arr(idx)) then
state <= nstate;
else
state <= IDLE;
end if;
end if;
end procedure f_change_state;
--============================================================================
-- Signal declarations
--============================================================================
-- Signal for the current state of the FSM
signal state : t_state;
-- Counter to create a pulse with width g_pwidth
signal cnt : unsigned(f_log2_size(g_pwidth)-1 downto 0);
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- FSM logic
--============================================================================
p_fsm : process (clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
state <= IDLE;
cnt <= (others => '0');
trig_o <= (others => '0');
else
case state is
when IDLE =>
trig_o <= (others => '0');
f_change_state(reg_ld_i, reg_i, 0, state, PASS1);
when PASS1 =>
f_change_state(reg_ld_i, reg_i, 1, state, PASS2);
when PASS2 =>
f_change_state(reg_ld_i, reg_i, 2, state, PASS3);
when PASS3 =>
f_change_state(reg_ld_i, reg_i, 3, state, GET_CHAN);
when GET_CHAN =>
if (reg_ld_i = '1') then
for i in 1 to g_nr_chan loop
if (i = to_integer(unsigned(reg_i))) then
trig_o(i) <= '1';
end if;
end loop;
cnt <= (others => '0');
state <= GEN;
end if;
when GEN =>
cnt <= cnt + 1;
if (cnt = g_pwidth-1) then
state <= IDLE;
end if;
when others =>
state <= IDLE;
end case;
end if;
end if;
end process p_fsm;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
conv-common-gw-4b29f81745c3c0a760395b21be78b872bfc85060/modules/conv_pulse_gen.vhd 0000664 0000000 0000000 00000037776 13055247455 0026364 0 ustar 00root root 0000000 0000000 --==============================================================================
-- CERN (BE-CO-HT)
-- Pulse generator with trigger
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-03-01
--
-- version: 2.0
--
-- description:
-- This module generates a constant-width pulse. The width is set using the
-- g_pwidth generic, given in number of clk_i cycles. With a clk_i period of
-- 50 ns, the output pulse width is by default 50*24=1.2 us.
--
-- The module is designed to work with an external glitch filter. Enabling
-- this glitch filter will result in jitter on the leading edge of the
-- output pulse signal. This jitter can be avoided by bypassing the glitch
-- filter; this is done via the gf_en_n_i input.
--
-- Regardless of whether the glitch filter is enabled, the input trigger signal
-- is extended or cut to g_pwidth, if it is shorter or respectively longer than
-- g_pwidth. At the end of the pulse, a rejection phase is implemented in order
-- to avoid too many pulses arriving on the input. This is to safeguard the
-- blocking output stage of the CONV-TTL-BLO boards. The isolation phase limits
-- the input pulse to 1/500 duty cycle.
--
-- dependencies:
-- none
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 01-03-2013 Theodor Stana File created.
-- 02-08-2013 Theodor Stana Implemented rejection phase.
-- 17-02-2014 Theodor Stana Moved the glitch filter to outside the
-- module.
-- 04-03-2014 Theodor Stana Added first pulse inhibit on glitch-filtered
-- side.
-- 24-07-2014 Theodor Stana Added g_with_fixed_pwidth generic and
-- subsequent logic.
-- 19-12-2016 Denia Bouhired Small modification to FSM to allow for very short 250ns pulses.
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
entity conv_pulse_gen is
generic
(
-- This generic enables elaboration of the fixed pulse width logic
g_with_fixed_pwidth : boolean;
-- Pulse width, in number of clk_i cycles
-- Default pulse width (20 MHz clock): 1.2 us
-- Minimum allowable pulse width (20 MHz clock): 1 us
-- Maximum allowable pulse width (20 MHz clock): 2 us
g_pwidth : natural range 2 to 40 := 24;
-- Duty cycle divider: D = 1/g_duty_cycle_div
g_duty_cycle_div : natural := 5
);
port
(
-- Clock and active-low reset inputs
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Glitch filter enable input
-- '1' - Glitch filter disabled (glitch-sensitive, no output jitter)
-- '0' - Glitch filter enabled (glitch-insensitive, with output jitter)
gf_en_n_i : in std_logic;
-- Enable input, pulse generation is enabled when '1'
en_i : in std_logic;
-- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays.
trig_a_i : in std_logic;
-- Pulse error output, pulses high for one clock cycle when a pulse arrives
-- within a pulse period
pulse_err_p_o : out std_logic;
-- Pulse output, active-high
-- latency:
-- glitch filter disabled: none
-- glitch filter enabled: glitch filter length + 5 clk_i cycles
pulse_o : out std_logic;
pulse_r_edge_p_o : out std_logic; --synced 1 cycle-long r edge output
pulse_f_edge_p_o : out std_logic
);
end entity conv_pulse_gen;
architecture behav of conv_pulse_gen is
--============================================================================
-- Type declarations
--============================================================================
type t_state is (
IDLE, -- idle state, wait for pulse
GEN_GF_OFF, -- pulse generation, glitch filter off
REJ_GF_OFF, -- pulse rejection, glitch filter off
GEN_GF_ON, -- pulse generation, glitch filter on
REJ_GF_ON -- pulse rejection, glitch filter on
);
--============================================================================
-- Constant declarations
--============================================================================
-- Max value of pulse counter for pulse width and pulse rejection width.
-- glitch filter OFF:
-- generate:
-- * g_pwidth-1: counter starts from 0
-- * g_pwidth-4: three-cycle delay through synchronizer
-- * g_pwidth-5: reset signal applied in REJ_GF_OFF state
-- reject:
-- * g_duty_cycle_div*g_pwidth: D duty cycle
-- * g_duty_cycle_div*g_pwidth-5: 5-cycle delay added from the generate phase
-- glitch filter ON:
-- generate:
-- * g_pwidth-1: counter starts from 0
-- reject:
-- * g_duty_cycle_div*g_pwidth: D duty cycle
-- * g_duty_cycle_div*g_pwidth-2: need one cycle less to allow for true 1/D
-- duty cycle,
-- since the FSM needs to go through IDLE to accept a pulse
constant c_max_gen_gf_off : natural := g_pwidth-5;
constant c_max_rej_gf_off : natural := g_duty_cycle_div*g_pwidth - 6;
constant c_max_gen_gf_on : natural := g_pwidth-1;
constant c_max_rej_gf_on : natural := g_duty_cycle_div*g_pwidth - 2;
--============================================================================
-- Function and procedure declarations
--============================================================================
function f_log2_size (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 64 bits
if (2**I >= A) then
return(I);
end if;
end loop;
return(63);
end function f_log2_size;
--============================================================================
-- Signal declarations
--============================================================================
-- Trigger signals
signal pulse_gf_off_d0 : std_logic;
signal pulse_gf_off_d1 : std_logic;
signal pulse_gf_off_d2 : std_logic;
signal gen_edge_gf_off_n : std_logic;
signal trig_gf_on : std_logic;
signal trig_gf_on_d0 : std_logic;
signal trig_gf_on_r_edge_p : std_logic;
signal trig_gf_on_f_edge_p : std_logic;
-- Pulse output signals
signal pulse_gf_on : std_logic;
signal pulse_gf_off : std_logic;
signal pulse_gf_off_rst : std_logic;
signal pulse_gf_off_r_edge_p : std_logic;
signal pulse_gf_off_f_edge_p : std_logic;
-- Pulse length counter
signal pulse_cnt : unsigned(f_log2_size(g_duty_cycle_div*g_pwidth)-1 downto 0);
-- FSM signal
signal state : t_state;
--==============================================================================
-- architecture begin
--==============================================================================
begin
gen_without_fixed_pwidth : if (g_with_fixed_pwidth = false) generate
pulse_o <= trig_a_i;
pulse_err_p_o <= '0';
end generate gen_without_fixed_pwidth;
gen_with_fixed_pwidth : if (g_with_fixed_pwidth = true) generate
--============================================================================
-- Output logic
--============================================================================
pulse_o <= pulse_gf_off when (gf_en_n_i = '1') else
pulse_gf_on;
--============================================================================
-- Pulse generation logic
--============================================================================
-- Generate the pulse on rising edge of trig_a_i
p_pulse_gf_off: process(pulse_gf_off_rst, trig_a_i)
begin
if (pulse_gf_off_rst = '1') then
pulse_gf_off <= '0';
elsif rising_edge(trig_a_i) then
if (en_i = '1') and (gf_en_n_i = '1') then
pulse_gf_off <= '1';
end if;
end if;
end process p_pulse_gf_off;
-- and synchronize the trigger in clk_i domain
-- p_sync_pulse_gf_off: process (clk_i) is
-- begin
-- if rising_edge(clk_i) then
-- if (rst_n_i = '0') then
-- pulse_gf_off_d0 <= '0';
-- pulse_gf_off_d1 <= '0';
-- pulse_gf_off_d2 <= '0';
-- pulse_gf_off_r_edge_p <= '0';
-- elsif (en_i = '1') and (gf_en_n_i = '1') then
-- pulse_gf_off_d0 <= pulse_gf_off;
-- pulse_gf_off_d1 <= pulse_gf_off_d0;
-- pulse_gf_off_d2 <= pulse_gf_off_d1;
-- pulse_gf_off_r_edge_p <= pulse_gf_off_d1 and (not pulse_gf_off_d2);
-- end if;
-- end if;
-- end process p_sync_pulse_gf_off;
gen_edge_gf_off_n <= rst_n_i or en_i or gf_en_n_i;
-- and synchronize the trigger in clk_i domain using sync_ffs general core
cmp_gc_sync_ffs : gc_sync_ffs
generic map
(
g_sync_edge => "positive"
)
port map(
clk_i => clk_i, -- clock from the destination clock domain
rst_n_i => gen_edge_gf_off_n, -- reset is acomibnation of rst_n_i,
-- en_i and gf_en_n_i
data_i => pulse_gf_off, -- async input
npulse_o => pulse_gf_off_f_edge_p,-- negative edge detect output
ppulse_o => pulse_gf_off_r_edge_p-- positive edge detect output
);
-- Trigger signal with glitch filter ON is input signal
trig_gf_on <= '0' when rst_n_i = '0' else trig_a_i ;
-- Rising edge detector for the trigger signal when glitch filter is ON
p_trig_gf_on : process (clk_i) is
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
trig_gf_on_d0 <= '0';
trig_gf_on_r_edge_p <= '0';
else
trig_gf_on_d0 <= trig_gf_on;
trig_gf_on_r_edge_p <= trig_gf_on and (not trig_gf_on_d0);
trig_gf_on_f_edge_p <= (not trig_gf_on) and trig_gf_on_d0;
end if;
end if;
end process p_trig_gf_on;
pulse_r_edge_p_o <= pulse_gf_off_r_edge_p when gf_en_n_i = '1' else trig_gf_on_r_edge_p;
pulse_f_edge_p_o <= pulse_gf_off_f_edge_p when gf_en_n_i = '1' else trig_gf_on_f_edge_p;
--============================================================================
-- Pulse width adjustment logic
--============================================================================
-- Generate the FSM logic
p_pulse_width: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
state <= IDLE;
pulse_gf_off_rst <= '1';
pulse_gf_on <= '0';
pulse_cnt <= (others => '0');
pulse_err_p_o <= '0';
--first_p <= '1';
elsif (en_i = '1') then
-- State machine logic
case state is
---------------------------------------------------------------------
-- IDLE
---------------------------------------------------------------------
-- Clear all values and go to pulse generation state when the
-- appropriate input arrives
---------------------------------------------------------------------
when IDLE =>
pulse_cnt <= (others => '0');
pulse_gf_off_rst <= '0';
pulse_err_p_o <= '0';
if (gf_en_n_i = '1') then
if (pulse_gf_off_r_edge_p = '1') then
state <= GEN_GF_OFF;
end if;
else
if (trig_gf_on_r_edge_p = '1') then
state <= GEN_GF_ON;
end if;
end if;
-- Pulse error assignment
-- This has been added for special cases whre rising edge occurs
-- on state transition
if (trig_gf_on_f_edge_p = '1' ) then
pulse_err_p_o <= '1';
end if;
---------------------------------------------------------------------
-- GEN_GF_OFF
--------------------------c-------------------------------------------
-- Extend the generated pulse to the required pulse width.
---------------------------------------------------------------------
when GEN_GF_OFF =>
-- Pulse logic and state change
pulse_cnt <= pulse_cnt + 1;
if pulse_cnt = c_max_gen_gf_off then
state <= REJ_GF_OFF;
end if;
if c_max_gen_gf_off = 0 then
state <= REJ_GF_OFF;
pulse_gf_off_rst <= '1';
end if;
-- Pulse error assignment
pulse_err_p_o <= '0';
if (trig_gf_on_r_edge_p = '1') then
pulse_err_p_o <= '1';
end if;
---------------------------------------------------------------------
-- REJ_GF_OFF
---------------------------------------------------------------------
-- Cut and reject input pulses, to safeguard the output transformers.
---------------------------------------------------------------------
when REJ_GF_OFF =>
-- Pulse logic and state change
pulse_cnt <= pulse_cnt + 1;
if pulse_cnt = c_max_rej_gf_off then
state <= IDLE;
pulse_gf_off_rst <= '0';
else
pulse_gf_off_rst <= '1';
end if;
-- Pulse error assignment
pulse_err_p_o <= '0';
if (trig_gf_on_r_edge_p = '1') then
pulse_err_p_o <= '1';
end if;
---------------------------------------------------------------------
-- GEN_GF_ON
---------------------------------------------------------------------
-- Start generating the output pulse with the required width.
---------------------------------------------------------------------
when GEN_GF_ON =>
-- Pulse logic and state change
pulse_cnt <= pulse_cnt + 1;
pulse_gf_on <= '1';
if (pulse_cnt = c_max_gen_gf_on) then
state <= REJ_GF_ON;
end if;
-- Pulse error assignment
pulse_err_p_o <= '0';
if (trig_gf_on_r_edge_p = '1') then
pulse_err_p_o <= '1';
end if;
---------------------------------------------------------------------
-- REJ_GF_ON
---------------------------------------------------------------------
-- Stop generating the output pulse and reject incoming pulses.
---------------------------------------------------------------------
when REJ_GF_ON =>
-- Pulse logic and state change
pulse_gf_on <= '0';
pulse_cnt <= pulse_cnt + 1;
if (pulse_cnt = c_max_rej_gf_on) then
state <= IDLE;
end if;
-- Pulse error assignment
pulse_err_p_o <= '0';
if (trig_gf_on_r_edge_p = '1') then
pulse_err_p_o <= '1';
end if;
when others =>
state <= IDLE;
end case;
end if;
end if;
end process p_pulse_width;
end generate gen_with_fixed_pwidth;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
conv-common-gw-4b29f81745c3c0a760395b21be78b872bfc85060/modules/conv_pulse_timetag.vhd 0000664 0000000 0000000 00000017215 13055247455 0027227 0 ustar 00root root 0000000 0000000 --==============================================================================
-- CERN (BE-CO-HT)
-- Pulse time-tagging core
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2014-02-04
--
-- version: 1.0
--
-- description:
-- This module contains the internal timetag counter, counting on an 8 ns
-- clock. When a pulse arrives on the input, it triggers the writing of a
-- timetag to a FIFO memory external to the module.
--
-- dependencies:
-- gencores_pkg : git://ohwr.org/hdl-core-lib/general-cores.git
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2014-02-04 Theodor Stana File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
entity conv_pulse_timetag is
generic
(
-- Frequency in Hz of the clk_i signal
g_clk_rate : positive := 125000000;
-- Number of repetition channels
g_nr_chan : positive := 6
);
port
(
-- Clock and active-low reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Asynchronous pulse input
pulse_a_i : in std_logic_vector(g_nr_chan-1 downto 0);
-- Time inputs from White Rabbit
wr_tm_cycles_i : in std_logic_vector(27 downto 0);
wr_tm_tai_i : in std_logic_vector(39 downto 0);
wr_tm_valid_i : in std_logic;
-- Timing inputs from Wishbone-mapped registers
wb_tm_tai_l_i : in std_logic_vector(31 downto 0);
wb_tm_tai_l_ld_i : in std_logic;
wb_tm_tai_h_i : in std_logic_vector( 7 downto 0);
wb_tm_tai_h_ld_i : in std_logic;
-- Timing outputs
tm_cycles_o : out std_logic_vector(27 downto 0);
tm_tai_o : out std_logic_vector(39 downto 0);
tm_wrpres_o : out std_logic;
chan_p_o : out std_logic_vector(g_nr_chan-1 downto 0);
-- Ring buffer I/O
buf_wr_req_p_o : out std_logic
);
end entity conv_pulse_timetag;
architecture behav of conv_pulse_timetag is
--============================================================================
-- Signal declarations
--============================================================================
signal cycles_cnt : unsigned(27 downto 0);
signal cycles_tick : std_logic;
signal tai_cnt : unsigned(39 downto 0);
signal tai_l_ld : std_logic;
signal tai_h_ld : std_logic;
signal pulse_redge_p : std_logic_vector(g_nr_chan-1 downto 0);
signal pulse_redge_p_d0 : std_logic_vector(g_nr_chan-1 downto 0);
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Time counter logic
--============================================================================
-- The Wishbone bus may be in a different clock domain than the time tag core,
-- so first we need to synchronize the LD signals
cmp_sync_l_ld : gc_sync_ffs
port map
(
clk_i => clk_i,
rst_n_i => rst_n_i,
data_i => wb_tm_tai_l_ld_i,
ppulse_o => tai_l_ld
);
cmp_sync_h_ld : gc_sync_ffs
port map
(
clk_i => clk_i,
rst_n_i => rst_n_i,
data_i => wb_tm_tai_h_ld_i,
ppulse_o => tai_h_ld
);
-- Generate the counters
p_cycle_cnt : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
cycles_cnt <= (others => '0');
cycles_tick <= '0';
else
cycles_cnt <= cycles_cnt + 1;
cycles_tick <= '0';
-- TAI counter loaded from Wishbone
if tai_l_ld = '1' or tai_h_ld = '1' then
cycles_cnt <= (others => '0');
-- Tick and reset on second
elsif cycles_cnt = g_clk_rate-1 then
cycles_cnt <= (others => '0');
cycles_tick <= '1';
end if;
end if;
end if;
end process p_cycle_cnt;
p_tai_cnt : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
tai_cnt <= (others => '0');
-- Load from Wishbone
elsif tai_l_ld = '1' then
tai_cnt(31 downto 0) <= unsigned(wb_tm_tai_l_i);
elsif tai_h_ld = '1' then
tai_cnt(39 downto 32) <= unsigned(wb_tm_tai_h_i);
-- Increment on cycles second tick
elsif cycles_tick = '1' then
tai_cnt <= tai_cnt + 1;
end if;
end if;
end process p_tai_cnt;
--============================================================================
-- Control logic for the FIFO
--============================================================================
-- First, synchronize the pulse inputs in the clk_i domain
gen_sync_chains : for i in 0 to g_nr_chan-1 generate
cmp_pulse_sync : gc_sync_ffs
generic map
(
g_sync_edge => "positive"
)
port map
(
clk_i => clk_i,
rst_n_i => '1',
data_i => pulse_a_i(i),
ppulse_o => pulse_redge_p(i)
);
end generate gen_sync_chains;
-- Set the control signals to the ring buffer on the rising edge of any
-- pulse channel
p_buf_ctrl : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
buf_wr_req_p_o <= '0';
else
buf_wr_req_p_o <= '0';
if not (pulse_redge_p = (pulse_redge_p'range => '0')) then
buf_wr_req_p_o <= '1';
end if;
end if;
end if;
end process p_buf_ctrl;
-- And delay the pulse rising edge for sampling (this is due to the delayed
-- setting of the write signal to the FIFO)
p_dly_pulse : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
pulse_redge_p_d0 <= (others => '0');
else
pulse_redge_p_d0 <= pulse_redge_p;
end if;
end if;
end process p_dly_pulse;
--============================================================================
-- Output logic
--============================================================================
-- Multiplex the timing outputs between WR and internal counters
tm_cycles_o <= wr_tm_cycles_i when wr_tm_valid_i = '1' else
std_logic_vector(cycles_cnt);
tm_tai_o <= wr_tm_tai_i when wr_tm_valid_i = '1' else
std_logic_vector(tai_cnt);
tm_wrpres_o <= wr_tm_valid_i;
chan_p_o <= pulse_redge_p_d0;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
conv-common-gw-4b29f81745c3c0a760395b21be78b872bfc85060/modules/conv_regs.h 0000664 0000000 0000000 00000035515 13055247455 0024776 0 ustar 00root root 0000000 0000000 /*
Register definitions for slave core: Converter board registers
* File : conv_regs.h
* Author : auto-generated by wbgen2 from conv_regs.wb
* Created : 02/06/17 15:05:15
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_CONV_REGS_WB
#define __WBGEN2_REGDEFS_CONV_REGS_WB
#include
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<