main pll bandwidths: 30Hz (default) and 5Hz, 10Hz (commented out), increased fractional bitsd

49447882 · Maciej Lipinski · f3c60778 · 49447882 · 49447882
Commit 49447882 authored Oct 06, 2015 by Maciej Lipinski
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Showing with 14 additions and 3 deletions

spll_defs.h include/spll_defs.h +1 -1

spll_main.c softpll/spll_main.c +13 -2

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--- a/include/spll_defs.h
+++ b/include/spll_defs.h
@@ -31,7 +31,7 @@ WARNING: These parameters must be in sync with the generics of the HDL instantia
 #define HPLL_N 14

 /* Fractional bits in PI controller coefficients */
-#define PI_FRACBITS 12
+#define PI_FRACBITS 16

 /* Max. allowed number of reference channels. Can be used to tweak memory usage. */
 #define MAX_CHAN_REF	BOARD_MAX_CHAN_REF /* Depends on wrc/wrs */

--- a/softpll/spll_main.c
+++ b/softpll/spll_main.c
@@ -31,8 +31,19 @@ void mpll_init(struct spll_main_state *s, int id_ref,
 	s->pi.anti_windup = 1;
 	s->pi.bias = 30000;
 #if defined(CONFIG_WR_SWITCH)
-	s->pi.kp = 1100;		// / 2;
-	s->pi.ki = 30;			// / 2;
+
+// 	/*bandwidth =  5Hz */
+	s->pi.kp = 2400;		// / 2;
+	s->pi.ki = 8;			// / 2;
+	
+// 	/*bandwidth =  10Hz */
+// 	s->pi.kp = 7000;		// / 2;
+// 	s->pi.ki = 16;			// / 2;
+// 	
+	/*bandwidth =  30Hz */
+// 	s->pi.kp = 1100;		// / 2;
+// 	s->pi.ki = 30;			// / 2;
+
 #elif defined(CONFIG_WR_NODE)
 	s->pi.kp = 1100;		// / 2;
 	s->pi.ki = 30;			// / 2;