From 14d314d97dbb228465e95c17c9c5050f6146d422 Mon Sep 17 00:00:00 2001
From: Alessandro Rubini <rubini@gnudd.com>
Date: Tue, 19 Feb 2013 16:34:20 +0100
Subject: [PATCH] softpll: some checkpatch fixes, no tech change
Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
---
softpll/softpll_ng.c | 26 +++++++++++++++-------
softpll/softpll_ng.h | 4 ++--
softpll/spll_common.h | 49 ++++++++++++++++++++++-------------------
softpll/spll_debug.h | 17 +++++++-------
softpll/spll_external.h | 32 ++++++++++++++++-----------
softpll/spll_helper.h | 18 ++++++++-------
softpll/spll_main.h | 27 +++++++++++++----------
7 files changed, 99 insertions(+), 74 deletions(-)
diff --git a/softpll/softpll_ng.c b/softpll/softpll_ng.c
index 26b108c..38b0064 100644
--- a/softpll/softpll_ng.c
+++ b/softpll/softpll_ng.c
@@ -16,8 +16,11 @@ volatile int irq_count = 0;
static volatile struct SPLL_WB *SPLL;
static volatile struct PPSG_WB *PPSG;
-/* The includes below contain code (not only declarations) to enable the compiler
- to inline functions where necessary and save some CPU cycles */
+/*
+ * The includes below contain code (not only declarations) to enable
+ * the compiler to inline functions where necessary and save some CPU
+ * cycles
+ */
#include "spll_defs.h"
#include "spll_common.h"
@@ -67,7 +70,10 @@ struct softpll_state {
static volatile struct softpll_state softpll;
-static volatile int ptracker_mask = 0; /* fixme: should be done by spll_init() but spll_init is called to switch modes (and we won't like messing around with ptrackers there) */
+static volatile int ptracker_mask = 0;
+/* fixme: should be done by spll_init() but spll_init is called to
+ * switch modes (and we won't like messing around with ptrackers
+ * there) */
void _irq_entry()
{
@@ -124,7 +130,8 @@ void _irq_entry()
break;
case SEQ_WAIT_HELPER:
- if (softpll.helper.ld.locked && !softpll.helper_locked) {
+ if (softpll.helper.ld.locked
+ && !softpll.helper_locked) {
softpll.helper_locked = 1;
if (softpll.mode == SPLL_MODE_SLAVE)
@@ -307,7 +314,8 @@ void spll_init(int mode, int slave_ref_channel, int align_pps)
softpll.seq_state = SEQ_CLEAR_DACS;
spll_resync_dmtd_counter(slave_ref_channel);
- while (!spll_check_dmtd_resync(slave_ref_channel)) ;
+ while (!spll_check_dmtd_resync(slave_ref_channel))
+ ;
helper_init(&softpll.helper, slave_ref_channel);
mpll_init(&softpll.mpll, slave_ref_channel, n_chan_ref);
@@ -424,7 +432,7 @@ void spll_set_phase_shift(int channel, int32_t value_picoseconds)
set_phase_shift(channel, value_picoseconds);
}
-void spll_get_phase_shift(int channel, int32_t * current, int32_t * target)
+void spll_get_phase_shift(int channel, int32_t *current, int32_t *target)
{
volatile struct spll_main_state *st =
(!channel ? &softpll.mpll : &softpll.aux[channel - 1]);
@@ -435,7 +443,7 @@ void spll_get_phase_shift(int channel, int32_t * current, int32_t * target)
*target = to_picos(st->phase_shift_target * div);
}
-int spll_read_ptracker(int channel, int32_t * phase_ps, int *enabled)
+int spll_read_ptracker(int channel, int32_t *phase_ps, int *enabled)
{
volatile struct spll_ptracker_state *st = &softpll.ptrackers[channel];
int phase = st->phase_val;
@@ -467,7 +475,9 @@ void spll_show_stats()
{
if (softpll.mode > 0)
TRACE_DEV
- ("Irq_count %d Sequencer_state %d mode %d Alignment_state %d HL%d EL%d ML%d HY=%d MY=%d DelCnt=%d\n",
+ ("Irq_count %d Sequencer_state %d mode %d "
+ "Alignment_state %d HL%d EL%d ML%d HY=%d "
+ "MY=%d DelCnt=%d\n",
irq_count, softpll.seq_state, softpll.mode,
softpll.ext.realign_state, softpll.helper.ld.locked,
softpll.ext.ld.locked, softpll.mpll.ld.locked,
diff --git a/softpll/softpll_ng.h b/softpll/softpll_ng.h
index a876eb4..e3d3939 100644
--- a/softpll/softpll_ng.h
+++ b/softpll/softpll_ng.h
@@ -20,9 +20,9 @@ void spll_start_channel(int channel);
void spll_stop_channel(int channel);
int spll_check_lock(int channel);
void spll_set_phase_shift(int channel, int32_t value_picoseconds);
-void spll_get_phase_shift(int channel, int32_t * current, int32_t * target);
+void spll_get_phase_shift(int channel, int32_t *current, int32_t *target);
void spll_enable_ptracker(int ref_channel, int enable);
-int spll_read_ptracker(int channel, int32_t * phase_ps, int *enabled);
+int spll_read_ptracker(int channel, int32_t *phase_ps, int *enabled);
void spll_get_num_channels(int *n_ref, int *n_out);
int spll_shifter_busy(int channel);
int spll_get_delock_count();
diff --git a/softpll/spll_common.h b/softpll/spll_common.h
index 3b7c458..8d2302f 100644
--- a/softpll/spll_common.h
+++ b/softpll/spll_common.h
@@ -9,8 +9,8 @@ spll_common.h - common data structures and functions
*/
-/* Number of reference/output channels. Currently we support only one SoftPLL instantiation per project,
- so these can remain static. */
+/* Number of reference/output channels. Currently we support only one
+ SoftPLL instantiation per project, so these can remain static. */
static int n_chan_ref, n_chan_out;
/* PI regulator state */
@@ -40,9 +40,9 @@ typedef struct {
int y_d;
} spll_lowpass_t;
-/* Processes a single sample (x) with PI control algorithm (pi). Returns the value (y) to
- drive the actuator. */
-static inline int pi_update(spll_pi_t * pi, int x)
+/* Processes a single sample (x) with PI control algorithm
+ (pi). Returns the value (y) to drive the actuator. */
+static inline int pi_update(spll_pi_t *pi, int x)
{
int i_new, y;
pi->x = x;
@@ -50,9 +50,10 @@ static inline int pi_update(spll_pi_t * pi, int x)
y = ((i_new * pi->ki + x * pi->kp) >> PI_FRACBITS) + pi->bias;
- /* clamping (output has to be in <y_min, y_max>) and anti-windup:
- stop the integrator if the output is already out of range and the output
- is going further away from y_min/y_max. */
+ /* clamping (output has to be in <y_min, y_max>) and
+ anti-windup: stop the integrator if the output is already
+ out of range and the output is going further away from
+ y_min/y_max. */
if (y < pi->y_min) {
y = pi->y_min;
if ((pi->anti_windup && (i_new > pi->integrator))
@@ -71,21 +72,22 @@ static inline int pi_update(spll_pi_t * pi, int x)
}
/* initializes the PI controller state. Currently almost a stub. */
-static inline void pi_init(spll_pi_t * pi)
+static inline void pi_init(spll_pi_t *pi)
{
pi->integrator = 0;
}
-/* Lock detector state machine. Takes an error sample (y) and checks if it's withing an acceptable range
- (i.e. <-ld.threshold, ld.threshold>. If it has been inside the range for (ld.lock_samples) cyckes, the
- FSM assumes the PLL is locked.
+/* Lock detector state machine. Takes an error sample (y) and checks
+ if it's withing an acceptable range (i.e. <-ld.threshold,
+ ld.threshold>. If it has been inside the range for
+ (ld.lock_samples) cyckes, the FSM assumes the PLL is locked.
Return value:
0: PLL not locked
1: PLL locked
-1: PLL just got out of lock
*/
-static inline int ld_update(spll_lock_det_t * ld, int y)
+static inline int ld_update(spll_lock_det_t *ld, int y)
{
if (abs(y) <= ld->threshold) {
if (ld->lock_cnt < ld->lock_samples)
@@ -108,19 +110,19 @@ static inline int ld_update(spll_lock_det_t * ld, int y)
return ld->locked;
}
-static void ld_init(spll_lock_det_t * ld)
+static void ld_init(spll_lock_det_t *ld)
{
ld->locked = 0;
ld->lock_cnt = 0;
}
-static void lowpass_init(spll_lowpass_t * lp, int alpha)
+static void lowpass_init(spll_lowpass_t *lp, int alpha)
{
lp->y_d = 0x80000000;
lp->alpha = alpha;
}
-static int lowpass_update(spll_lowpass_t * lp, int x)
+static int lowpass_update(spll_lowpass_t *lp, int x)
{
if (lp->y_d == 0x80000000) {
lp->y_d = x;
@@ -134,14 +136,15 @@ static int lowpass_update(spll_lowpass_t * lp, int x)
/* Enables/disables DDMTD tag generation on a given (channel).
-Channels (0 ... n_chan_ref - 1) are the reference channels (e.g. transceivers' RX clocks
- or a local reference)
+Channels (0 ... n_chan_ref - 1) are the reference channels
+ (e.g. transceivers' RX clocks or a local reference)
-Channels (n_chan_ref ... n_chan_out + n_chan_ref-1) are the output channels (local voltage
- controlled oscillators). One output (usually the first one) is always used to drive the
- oscillator which produces the reference clock for the transceiver. Other outputs can be
- used to discipline external oscillators (e.g. on FMCs).
-
+Channels (n_chan_ref ... n_chan_out + n_chan_ref-1) are the output
+ channels (local voltage controlled oscillators). One output
+ (usually the first one) is always used to drive the oscillator
+ which produces the reference clock for the transceiver. Other
+ outputs can be used to discipline external oscillators
+ (e.g. on FMCs).
*/
static void spll_enable_tagger(int channel, int enable)
diff --git a/softpll/spll_debug.h b/softpll/spll_debug.h
index b3f160f..4ae0eef 100644
--- a/softpll/spll_debug.h
+++ b/softpll/spll_debug.h
@@ -7,13 +7,14 @@ Licensed under LGPL 2.1.
spll_debug.h - debugging/diagnostic interface
-The so-called debug inteface is a large, interrupt-driven FIFO which passes
-various realtime parameters (e.g. error value, tags, DAC drive) to an external
-application where they are further analyzed. It's very useful for optimizing PI coefficients
-and/or lock thresholds.
-
-The data is organized as a stream of samples, where each sample can store a number of parameters.
-For example, a stream samples with Y and ERR parameters can be used to evaluate the impact of
+The so-called debug inteface is a large, interrupt-driven FIFO which
+passes various realtime parameters (e.g. error value, tags, DAC drive)
+to an external application where they are further analyzed. It's very
+useful for optimizing PI coefficients and/or lock thresholds.
+
+The data is organized as a stream of samples, where each sample can
+store a number of parameters. For example, a stream samples with Y
+and ERR parameters can be used to evaluate the impact of
integral/proportional gains on the response of the system.
*/
@@ -40,7 +41,7 @@ what: type of the parameter and its' source. For example,
- DBG_ERR | DBG_HELPER means that (value) contains the phase error of the helper PLL.
- DBG_EVENT indicates an asynchronous event. (value) must contain the event type (DBG_EVT_xxx)
-last: when non-zero, indicates the last parameter in a sample.
+last: when non-zero, indicates the last parameter in a sample.
*/
static inline void spll_debug(int what, int value, int last)
diff --git a/softpll/spll_external.h b/softpll/spll_external.h
index 2eb4b77..53c5c1b 100644
--- a/softpll/spll_external.h
+++ b/softpll/spll_external.h
@@ -6,11 +6,13 @@
/* Alignment FSM states */
-/* 1st alignment stage, done before starting the ext channel PLL: alignment of the rising edge
- of the external clock (10 MHz), with the rising edge of the local reference (62.5/125 MHz)
- and the PPS signal. Because of non-integer ratio (6.25 or 12.5), the PLL must know which edges
- shall be kept at phase==0. We align to the edge of the 10 MHz clock which comes right after the edge
- of the PPS pulse (see drawing below):
+/* 1st alignment stage, done before starting the ext channel PLL:
+ alignment of the rising edge of the external clock (10 MHz), with
+ the rising edge of the local reference (62.5/125 MHz) and the PPS
+ signal. Because of non-integer ratio (6.25 or 12.5), the PLL must
+ know which edges shall be kept at phase==0. We align to the edge of
+ the 10 MHz clock which comes right after the edge of the PPS pulse
+ (see drawing below):
PLL reference (62.5 MHz) ____|^^^^|____|^^^^|____|^^^^|____|^^^^|____|^^^^|____|^^^^|____|^^^^|____|^^^^|____|^^^^|____|^^^^|____|^^^^|____|
External clock (10 MHz) ^^^^^^^^^|________________________|^^^^^^^^^^^^^^^^^^^^^^^^^|________________________|^^^^^^^^^^^^^^^^^^^^^^^^^|___
@@ -19,8 +21,10 @@ External PPS ___________|^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
#define REALIGN_STAGE1 1
#define REALIGN_STAGE1_WAIT 2
-/* 2nd alignment stage, done after the ext channel PLL has locked. We make sure that the switch's internal PPS signal
- is produced exactly on the edge of PLL reference in-phase with 10 MHz clock edge, which has come right after the PPS input
+/* 2nd alignment stage, done after the ext channel PLL has locked. We
+ make sure that the switch's internal PPS signal is produced exactly
+ on the edge of PLL reference in-phase with 10 MHz clock edge, which
+ has come right after the PPS input
PLL reference (62.5 MHz) ____|^^^^|____|^^^^|____|^^^^|____|^^^^|____|^^^^|____|^^^^|____|^^^^|____|^^^^|____|^^^^|____|^^^^|____|^^^^|____|
External clock (10 MHz) ^^^^^^^^^|________________________|^^^^^^^^^^^^^^^^^^^^^^^^^|________________________|^^^^^^^^^^^^^^^^^^^^^^^^^|___
@@ -35,7 +39,8 @@ Internal PPS __________________________________|^^^^^^^^^|________
/* Error state - PPS signal missing or of bad frequency */
#define REALIGN_PPS_INVALID 5
-/* Realignment is disabled (i.e. the switch inputs only the reference frequency, but not time) */
+/* Realignment is disabled (i.e. the switch inputs only the reference
+ * frequency, but not time) */
#define REALIGN_DISABLED 6
/* Realignment done */
@@ -77,10 +82,10 @@ static void external_init(volatile struct spll_external_state *s, int ext_ref,
s->realign_clocks = realign_clocks;
s->realign_state = (realign_clocks ? REALIGN_STAGE1 : REALIGN_DISABLED);
- pi_init((spll_pi_t *) & s->pi);
- ld_init((spll_lock_det_t *) & s->ld);
- lowpass_init((spll_lowpass_t *) & s->lp_short, 4000);
- lowpass_init((spll_lowpass_t *) & s->lp_long, 300);
+ pi_init((spll_pi_t *)&s->pi);
+ ld_init((spll_lock_det_t *)&s->ld);
+ lowpass_init((spll_lowpass_t *)&s->lp_short, 4000);
+ lowpass_init((spll_lowpass_t *)&s->lp_long, 300);
}
static inline void realign_fsm(struct spll_external_state *s)
@@ -164,7 +169,8 @@ static int external_update(struct spll_external_state *s, int tag, int source)
y2 = lowpass_update(&s->lp_short, y);
ylt = lowpass_update(&s->lp_long, y);
- if (!(SPLL->ECCR & SPLL_ECCR_EXT_REF_PRESENT)) { /* no reference? de-lock now */
+ if (!(SPLL->ECCR & SPLL_ECCR_EXT_REF_PRESENT)) {
+ /* no reference? de-lock now */
ld_init(&s->ld);
y2 = 32000;
}
diff --git a/softpll/spll_helper.h b/softpll/spll_helper.h
index a108c19..3576a3a 100644
--- a/softpll/spll_helper.h
+++ b/softpll/spll_helper.h
@@ -1,7 +1,8 @@
/* State of the Helper PLL producing a clock (clk_dmtd_i) which is
- slightly offset in frequency from the recovered/reference clock (clk_rx_i or clk_ref_i), so the
- Main PLL can use it to perform linear phase measurements.
+ slightly offset in frequency from the recovered/reference clock
+ (clk_rx_i or clk_ref_i), so the Main PLL can use it to perform
+ linear phase measurements.
*/
#define SPLL_LOCKED 1
@@ -9,7 +10,8 @@
#define HELPER_TAG_WRAPAROUND 100000000
-/* Maximum abs value of the phase error. If the error is bigger, it's clamped to this value. */
+/* Maximum abs value of the phase error. If the error is bigger, it's
+ * clamped to this value. */
#define HELPER_ERROR_CLAMP 150000
struct spll_helper_state {
@@ -29,7 +31,7 @@ static void helper_init(volatile struct spll_helper_state *s, int ref_channel)
s->pi.y_min = 5;
s->pi.y_max = (1 << DAC_BITS) - 5;
s->pi.kp = (int)(0.3 * 32.0 * 16.0); // / 2;
- s->pi.ki = (int)(0.03 * 32.0 * 3.0); // / 2;
+ s->pi.ki = (int)(0.03 * 32.0 * 3.0); // / 2;
s->pi.anti_windup = 1;
@@ -78,14 +80,14 @@ static int helper_update(volatile struct spll_helper_state *s, int tag,
s->p_setpoint += (1 << HPLL_N);
s->tag_d0 = tag;
- y = pi_update((spll_pi_t *) & s->pi, err);
+ y = pi_update((spll_pi_t *)&s->pi, err);
SPLL->DAC_HPLL = y;
spll_debug(DBG_SAMPLE_ID | DBG_HELPER, s->sample_n++, 0);
spll_debug(DBG_Y | DBG_HELPER, y, 0);
spll_debug(DBG_ERR | DBG_HELPER, err, 1);
- if (ld_update((spll_lock_det_t *) & s->ld, err))
+ if (ld_update((spll_lock_det_t *)&s->ld, err))
return SPLL_LOCKED;
}
return SPLL_LOCKING;
@@ -102,8 +104,8 @@ static void helper_start(volatile struct spll_helper_state *s)
s->sample_n = 0;
s->tag_d0 = -1;
- pi_init((spll_pi_t *) & s->pi);
- ld_init((spll_lock_det_t *) & s->ld);
+ pi_init((spll_pi_t *)&s->pi);
+ ld_init((spll_lock_det_t *)&s->ld);
spll_enable_tagger(s->ref_src, 1);
spll_debug(DBG_EVENT | DBG_HELPER, DBG_EVT_START, 1);
diff --git a/softpll/spll_main.h b/softpll/spll_main.h
index e389452..1dcef13 100644
--- a/softpll/spll_main.h
+++ b/softpll/spll_main.h
@@ -49,8 +49,8 @@ static void mpll_init(volatile struct spll_main_state *s, int id_ref,
s->id_out = id_out;
s->dac_index = id_out - n_chan_ref;
- pi_init((spll_pi_t *) & s->pi);
- ld_init((spll_lock_det_t *) & s->ld);
+ pi_init((spll_pi_t *)&s->pi);
+ ld_init((spll_lock_det_t *)&s->ld);
}
static void mpll_start(volatile struct spll_main_state *s)
@@ -68,8 +68,8 @@ static void mpll_start(volatile struct spll_main_state *s)
s->phase_shift_current = 0;
s->sample_n = 0;
- pi_init((spll_pi_t *) & s->pi);
- ld_init((spll_lock_det_t *) & s->ld);
+ pi_init((spll_pi_t *)&s->pi);
+ ld_init((spll_lock_det_t *)&s->ld);
spll_enable_tagger(s->id_ref, 1);
spll_enable_tagger(s->id_out, 1);
@@ -146,9 +146,13 @@ static int mpll_update(volatile struct spll_main_state *s, int tag, int source)
#ifndef WITH_SEQUENCING
- /* Hack: the PLL is locked, so the tags are close to each other. But when we start phase shifting, after reaching
- full clock period, one of the reference tags will flip before the other, causing a suddent 2**HPLL_N jump in the error.
- So, once the PLL is locked, we just mask out everything above 2**HPLL_N.
+ /* Hack: the PLL is locked, so the tags are close to
+ each other. But when we start phase shifting, after
+ reaching full clock period, one of the reference
+ tags will flip before the other, causing a suddent
+ 2**HPLL_N jump in the error. So, once the PLL is
+ locked, we just mask out everything above
+ 2**HPLL_N.
Proper solution: tag sequence numbers */
if (s->ld.locked) {
@@ -159,10 +163,9 @@ static int mpll_update(volatile struct spll_main_state *s, int tag, int source)
#endif
- y = pi_update((spll_pi_t *) & s->pi, err);
- SPLL->DAC_MAIN =
- SPLL_DAC_MAIN_VALUE_W(y) | SPLL_DAC_MAIN_DAC_SEL_W(s->
- dac_index);
+ y = pi_update((spll_pi_t *)&s->pi, err);
+ SPLL->DAC_MAIN = SPLL_DAC_MAIN_VALUE_W(y)
+ | SPLL_DAC_MAIN_DAC_SEL_W(s->dac_index);
spll_debug(DBG_MAIN | DBG_REF, s->tag_ref + s->adder_ref, 0);
spll_debug(DBG_MAIN | DBG_TAG, s->tag_out + s->adder_out, 0);
@@ -189,7 +192,7 @@ static int mpll_update(volatile struct spll_main_state *s, int tag, int source)
s->adder_ref--;
}
}
- if (ld_update((spll_lock_det_t *) & s->ld, err))
+ if (ld_update((spll_lock_det_t *)&s->ld, err))
return SPLL_LOCKED;
}
--
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