Commit b9db4939 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

wip

parent 660ec751
......@@ -19,4 +19,5 @@ files = [ "rv_cpu.v",
"rv_timer.v",
"rv_exceptions.v",
"urv_iram.v",
"../sim/rv_icache_model.sv"];
"xrv_core.vhd" ];
# "../sim/rv_icache_model.sv"];
......@@ -209,9 +209,6 @@ module rv_cpu
.d_w_rs1_bypass_i(d_w_rs1_bypass),
.d_w_rs2_bypass_i(d_w_rs2_bypass),
.x_load_hazard_o(d2x_load_hazard),
.x_valid_o(d2x_valid),
.x_pc_o(d2x_pc),
.x_rs1_o(d2x_rs1),
......@@ -325,7 +322,6 @@ module rv_cpu
.d_csr_imm_i ( d2x_csr_imm ),
.d_csr_sel_i (d2x_csr_sel),
.d_load_hazard_i(d2x_load_hazard),
.d_pc_i(d2x_pc),
.d_rd_i(d2x_rd),
.d_fun_i(d2x_fun),
......@@ -359,7 +355,6 @@ module rv_cpu
.f_branch_take_o (x2f_bra),
.w_load_hazard_o(x2w_load_hazard),
// Writeback stage I/F
.w_fun_o(x2w_fun),
.w_load_o(x2w_load),
......@@ -398,7 +393,6 @@ module rv_cpu
.x_fun_i(x2w_fun),
.x_load_i(x2w_load),
.x_load_hazard_i(x2w_load_hazard),
.x_store_i(x2w_store),
.x_valid_i(x2w_valid),
......
......@@ -43,7 +43,6 @@ module rv_exec
input d_valid_i,
input d_load_hazard_i,
input [4:0] d_opcode_i,
input d_shifter_sign_i,
......@@ -76,7 +75,6 @@ module rv_exec
output reg [31:0] f_branch_target_o,
output f_branch_take_o,
output w_load_hazard_o,
input irq_i,
......@@ -242,13 +240,8 @@ module rv_exec
end
wire [32:0] alu_addsub_op1 = {d_is_signed_alu_op_i ? alu_op1[31] : 1'b0, alu_op1 };
wire [32:0] alu_addsub_op2 = {d_is_signed_alu_op_i ? alu_op2[31] : 1'b0, alu_op2 };
reg [32:0] alu_addsub_result;
......@@ -338,6 +331,7 @@ module rv_exec
case (d_rd_source_i)
`RD_SOURCE_ALU: rd_value <= alu_result;
`RD_SOURCE_CSR: rd_value <= rd_csr;
// `RD_SOURCE_DIVIDE: rd_value <= rd_divide;
default: rd_value <= 32'hx;
endcase // case (x_rd_source_i)
......@@ -432,17 +426,10 @@ module rv_exec
always@(posedge clk_i)
if (rst_i) begin
// f_branch_target_o <= 0;
f_branch_take <= 0;
// w_rd_write_o <= 0;
// w_rd_o <= 0;
// w_fun_o <= 0;
w_load_o <= 0;
w_store_o <= 0;
// w_dm_addr_o <= 0;
// w_rd_source_o <= 0;
w_valid_o <= 0;
end else if (!x_stall_i) begin
f_branch_target_o <= branch_target;
f_branch_take <= branch_take && !x_kill_i && d_valid_i;
......@@ -459,7 +446,6 @@ module rv_exec
assign f_branch_take_o = f_branch_take;
always@*
if(f_branch_take)
x_stall_req_o <= 0;
......@@ -470,8 +456,6 @@ module rv_exec
else
x_stall_req_o <= 0;
assign w_load_hazard_o = d_load_hazard_i;
endmodule
......
......@@ -35,7 +35,6 @@ module rv_writeback
input x_load_i,
input x_store_i,
input x_load_hazard_i,
input [31:0] x_dm_addr_i,
input [4:0] x_rd_i,
input [31:0] x_rd_value_i,
......
......@@ -91,6 +91,19 @@ module urv_iram
`RAM_INST(64K_30, RAMB16_S1_S1, 15:2, 30, 3)
`RAM_INST(64K_31, RAMB16_S1_S1, 15:2, 31, 3)
end // if (g_size == 65536)
if(g_size == 16384) begin
`RAM_INST(16K_0, RAMB16_S4_S4, 13:2, 3:0, 0)
`RAM_INST(16K_1, RAMB16_S4_S4, 13:2, 7:4, 0)
`RAM_INST(16K_2, RAMB16_S4_S4, 13:2, 11:8, 1)
`RAM_INST(16K_3, RAMB16_S4_S4, 13:2, 15:12, 1)
`RAM_INST(16K_4, RAMB16_S4_S4, 13:2, 19:16, 2)
`RAM_INST(16K_5, RAMB16_S4_S4, 13:2, 23:20, 2)
`RAM_INST(16K_6, RAMB16_S4_S4, 13:2, 27:24, 3)
`RAM_INST(16K_7, RAMB16_S4_S4, 13:2, 31:28, 3)
end
end else begin // if (!g_simulation)
// synthesis translate_off
......
......@@ -29,8 +29,7 @@ entity xrv_core is
g_internal_ram_size : integer := 65536;
g_internal_ram_init_file : string := "";
g_simulation : boolean := false;
g_address_bits : integer := 32;
g_wishbone_start : unsigned(31 downto 0) := x"00020000"
g_address_bits : integer := 32
);
port (
......@@ -100,6 +99,7 @@ architecture wrapper of xrv_core is
qb_o :out std_logic_vector(31 downto 0)
);
end component;
signal cpu_rst, cpu_rst_d : std_logic;
......
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