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hdl-core-lib
urv-core
Commits
a9fae1ac
Commit
a9fae1ac
authored
May 26, 2015
by
Tomasz Wlostowski
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simplify mem address generation
parent
18f2be72
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4 changed files
with
28 additions
and
27 deletions
+28
-27
main.sv
main.sv
+19
-12
rv_cpu.v
rv_cpu.v
+0
-3
rv_exec.v
rv_exec.v
+3
-7
rv_predecode.v
rv_predecode.v
+6
-5
No files found.
main.sv
View file @
a9fae1ac
...
...
@@ -222,7 +222,18 @@ module main;
endfunction
// s_hex
reg
[
31
:
0
]
dm_addr_d0
;
integer
f_console
,
f_exec_log
;
initial
begin
f_console
=
$
fopen
(
"console.txt"
,
"wb"
)
;
f_exec_log
=
$
fopen
(
"exec_log.txt"
,
"wb"
)
;
#
500u
s
;
// $fclose(f_console);
end
always
@
(
posedge
clk
)
begin
...
...
@@ -230,8 +241,11 @@ module main;
begin
dm_addr_d0
<=
dm_addr
;
if
(
dm_write
)
if
(
dm_write
)
begin
$
display
(
"DM Write addr %x data %x"
,
dm_addr
,
dm_data_s
)
;
$
fwrite
(
f_exec_log
,
"DM Write addr %x data %x
\n
"
,
dm_addr
,
dm_data_s
)
;
end
if
(
DUT
.
writeback
.
x_load_i
&&
DUT
.
writeback
.
rf_rd_write_o
)
begin
/* -----\/----- EXCLUDED -----\/-----
...
...
@@ -244,27 +258,19 @@ module main;
$
display
(
"DM Load addr %x data %x -> %s"
,
dm_addr_d0
,
DUT
.
writeback
.
rf_rd_value_o
,
decode_regname
(
DUT
.
writeback
.
x_rd_i
))
;
$
fwrite
(
f_exec_log
,
"DM Load addr %x data %x -> %s
\n
"
,
dm_addr_d0
,
DUT
.
writeback
.
rf_rd_value_o
,
decode_regname
(
DUT
.
writeback
.
x_rd_i
))
;
end
end
end
integer
f_console
;
initial
begin
f_console
=
$
fopen
(
"console.txt"
,
"wb"
)
;
#
500u
s
;
// $fclose(f_console);
end
always
@
(
posedge
clk
)
if
(
dm_write
&&
dm_addr
==
'h100000
)
begin
$
display
(
"
\n
****** TX '%c'
\n
"
,
dm_data_s
[
7
:
0
])
;
// byte x = dm_data_s[7:0]
;
$
fwrite
(
f_exec_log
,
"
\n
****** TX '%c'
\n
"
,
dm_data_s
[
7
:
0
])
;
$
fwrite
(
f_console
,
"%c"
,
dm_data_s
[
7
:
0
])
;
$
fflush
(
f_console
)
;
...
...
@@ -359,9 +365,10 @@ module main;
endcase
// case (d2x_opcode)
$
display
(
"%08x: %-8s %-3s %s"
,
DUT
.
execute
.
d_pc_i
,
opc
,
fun
,
args
)
;
$
fwrite
(
f_exec_log
,
"%08x: %-8s %-3s %s
\n
"
,
DUT
.
execute
.
d_pc_i
,
opc
,
fun
,
args
)
;
end
...
...
rv_cpu.v
View file @
a9fae1ac
...
...
@@ -158,10 +158,7 @@ module rv_cpu
wire
[
31
:
0
]
rf_bypass_rd_value
=
x2w_rd_value
;
//x2w_rd_value;
wire
rf_bypass_rd_write
=
rf_rd_write
&&
!
x2w_load
;
// x2w_rd_write && !w_stall;
rv_regfile
regfile
(
...
...
rv_exec.v
View file @
a9fae1ac
...
...
@@ -30,7 +30,7 @@ module rv_exec
input
x_stall_i
,
input
x_kill_i
,
output
x_stall_req_o
,
w_stall_req_i
,
input
w_stall_req_i
,
input
[
31
:
0
]
d_pc_i
,
...
...
@@ -230,12 +230,8 @@ module rv_exec
// generate load/store address
always
@*
begin
case
(
d_opcode_i
)
`OPC_LOAD
:
dm_addr
<=
rs1
+
d_imm_i
;
`OPC_STORE
:
dm_addr
<=
rs1
+
d_imm_i
;
default:
dm_addr
<=
32
'
hx
;
endcase
// case (d_opcode_i)
dm_addr
<=
rs1
+
$
signed
(
d_imm_i
[
11
:
0
])
;
end
// generate store value/select
...
...
rv_predecode.v
View file @
a9fae1ac
...
...
@@ -52,7 +52,7 @@ module rv_decode
output
reg
[
4
:
0
]
x_shamt_o
,
output
reg
[
2
:
0
]
x_fun_o
,
output
reg
[
4
:
0
]
x_opcode_o
,
output
[
4
:
0
]
x_opcode_o
,
output
reg
x_shifter_sign_o
,
output
reg
[
31
:
0
]
x_imm_o
,
...
...
@@ -69,12 +69,13 @@ module rv_decode
reg
[
4
:
0
]
x_rs1
;
reg
[
4
:
0
]
x_rs2
;
reg
[
4
:
0
]
x_rd
;
reg
[
4
:
0
]
x_opcode
;
assign
x_rs1_o
=
x_rs1
;
assign
x_rs2_o
=
x_rs2
;
assign
x_rd_o
=
x_rd
;
assign
x_opcode_o
=
x_opcode
;
always
@*
if
(
d_stall_i
)
begin
...
...
@@ -99,7 +100,7 @@ module rv_decode
always
@
(
posedge
clk_i
)
if
(
!
d_stall_i
)
x_load_hazard_o
<=
(
(
f_rs1
==
x_rd
)
||
(
f_rs2
==
x_rd
)
)
&&
(
!
d_kill_i
)
&&
(
d
_opcode
==
`OPC_LOAD
)
;
x_load_hazard_o
<=
(
(
f_rs1
==
x_rd
)
||
(
f_rs2
==
x_rd
)
)
&&
(
!
d_kill_i
)
&&
(
x
_opcode
==
`OPC_LOAD
)
;
always
@
(
posedge
clk_i
)
...
...
@@ -108,7 +109,7 @@ module rv_decode
x_rs1
<=
f_rs1
;
x_rs2
<=
f_rs2
;
x_rd
<=
f_ir_i
[
11
:
7
]
;
x_opcode
_o
<=
d_opcode
;
x_opcode
<=
d_opcode
;
x_shamt_o
<=
f_ir_i
[
24
:
20
]
;
end
...
...
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