Commit 1cf413e9 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

added top level for the SPEC & some missing files

parent 014209e9
[submodule "ip_cores/general-cores"]
path = ip_cores/general-cores
url = git://ohwr.org/hdl-core-lib/general-cores.git
general-cores @ 97bc7197
Subproject commit 97bc71975252b32cf8a47ba895f7010734f015e5
/*
uRV - a tiny and dumb RISC-V core
Copyright (c) 2015 CERN
Author: Tomasz Włostowski <tomasz.wlostowski@cern.ch>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 3.0 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library.
*/
// Platform definition. Currently supported ones are:
// SPARTAN6 - Xilinx Spartan-6 FPGA
// GENERIC - Generic, HW-independent
`define URV_PLATFORM_SPARTAN6 1
......@@ -302,3 +302,95 @@ module urv_iram
end // else: !if(!g_simulation)
`endif
`ifdef URV_PLATFORM_ALTERA
module urv_iram
#(
parameter g_size = 65536,
parameter g_init_file = "",
parameter g_simulation = 0
)
(
input clk_i,
input ena_i,
input wea_i,
input [31:0] aa_i,
input [3:0] bwea_i,
input [31:0] da_i,
output [31:0] qa_o,
input enb_i,
input web_i,
input [31:0] ab_i,
input [3:0] bweb_i,
input [31:0] db_i,
output [31:0] qb_o
);
localparam g_addr_width = $clogb2(g_size);
altsyncram
ram (
.address_a (aa_i[g_addr_width+1:2]),
.address_b (aa_i[g_addr_width+1:2]),
.byteena_a (bwea_i),
.byteena_b (bweb_i),
.clock0 (clk_i),
.data_a (da_i),
.data_b (db_i),
.wren_a (wea_i),
.wren_b (web_i),
.q_a (qa_o),
.q_b (qb_o),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.byteena_reg_b = "CLOCK0",
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.init_file = g_init_file,
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 16384,
altsyncram_component.numwords_b = 16384,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M9K",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_WITH_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_WITH_NBE_READ",
altsyncram_component.widthad_a = 16,
altsyncram_component.widthad_b = 16,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 4,
altsyncram_component.width_byteena_b = 4,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule // urv_iram
`endif // `ifdef URV_PLATFORM_ALTERA
......@@ -111,6 +111,44 @@ module urv_mult18x18
endmodule // urv_mult18x18
`endif // `ifdef URV_PLATFORM_GENERIC
`ifdef URV_PLATFORM_ALTERA
module urv_mult18x18
(
input clk_i,
input rst_i,
input stall_i,
input [17:0] x_i,
input [17:0] y_i,
output [35:0] q_o
);
lpm_mult multiplier (
.clock (clk_i),
.dataa (x_i),
.datab (y_i),
.result (q_o),
.aclr (1'b0),
.clken (!stall_i),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=5",
lpm_mult_component.lpm_pipeline = 1,
lpm_mult_component.lpm_representation = "SIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 18,
lpm_mult_component.lpm_widthb = 18,
lpm_mult_component.lpm_widthp = 36;
endmodule // urv_mult18x18
`endif
module urv_multiply
(
......
......@@ -46,8 +46,6 @@ module urv_writeback
input [31:0] x_multiply_rd_value_i,
input [1:0] x_rd_source_i,
output reg [31:0] x_bypass_o,
input [31:0] dm_data_l_i,
input dm_load_done_i,
input dm_store_done_i,
......@@ -123,10 +121,6 @@ module urv_writeback
rf_rd_write <= x_rd_write_i & x_valid_i;
always@(posedge clk_i)
if( rf_rd_write )
x_bypass_o <= rf_rd_value;
assign rf_rd_write_o = rf_rd_write;
assign rf_rd_value_o = rf_rd_value;
assign rf_rd_o = x_rd_i;
......
This diff is collapsed.
sim_tool = "modelsim"
top_module="main"
syn_device="xc6slx150t"
action = "simulation"
target = "xilinx"
include_dirs=["../../rtl"]
vcom_opt="-mixedsvvh l"
files = [ "main.sv" ];
modules = {"local" : [ "../../rtl" ] }
\ No newline at end of file
......@@ -4,7 +4,7 @@ files = ["spec_top.vhd",
fetchto = "../../ip_cores"
files = ["../../rtl/xrv_core.vhd", "spec_top.vhd", "reset_gen.vhd", "spec_top.ucf" ];
files = [ "spec_top.vhd", "reset_gen.vhd", "spec_top.ucf" ];
modules = {
"local" : ["../../rtl/", "../../ip_cores/general-cores" ]
......
......@@ -64,7 +64,7 @@ architecture rtl of spec_top is
rst_n_o : out std_logic);
end component;
component xrv_core is
component xurv_core is
generic (
g_internal_ram_size : integer;
g_internal_ram_init_file : string;
......@@ -80,7 +80,7 @@ architecture rtl of spec_top is
dwb_i : in t_wishbone_master_in;
host_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
host_slave_o : out t_wishbone_slave_out);
end component xrv_core;
end component xurv_core;
constant c_cnx_slave_ports : integer := 1;
constant c_cnx_master_ports : integer := 2;
......@@ -133,7 +133,7 @@ begin -- rtl
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 8,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 7, -- 62.5 MHz
CLKOUT0_DIVIDE => 10, -- 62.5 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 8, -- not used
......@@ -174,7 +174,7 @@ begin -- rtl
rst_n_o => rst_n_sys);
U_CPU: xrv_core
U_CPU: xurv_core
generic map (
g_internal_ram_size => g_riscv_mem_size,
g_internal_ram_init_file => g_riscv_firmware,
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment