Commit 08a9b8d4 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

load interlock seems to work

parent 2512ebf0
......@@ -61,6 +61,17 @@ module rv_cpu
wire f_stall_req;
wire [31:0] d2x_pc;
wire [4:0] rf_rs1, d2x_rs1;
wire [4:0] rf_rs2, d2x_rs2;
wire [4:0] d2x_rd;
wire [4:0] d2x_shamt;
wire [2:0] d2x_fun;
wire [4:0] d2x_opcode;
wire d2x_shifter_sign;
wire [31:0] d2x_imm_i, d2x_imm_s, d2x_imm_u, d2x_imm_b, d2x_imm_j;
wire f_load_hazard;
rv_fetch fetch
(
......@@ -69,6 +80,10 @@ module rv_cpu
.im_addr_o(im_addr_o),
.im_data_i(im_data_i),
.im_valid_i(im_valid_i),
.rf_rs1_o(rf_rs1),
.rf_rs2_o(rf_rs2),
.f_load_hazard_o(f_load_hazard),
.f_stall_i(f_stall),
.f_kill_i(f_kill),
......@@ -82,33 +97,18 @@ module rv_cpu
.x_bra_i(x2f_bra)
);
wire [31:0] d2x_pc;
wire [4:0] rf_rs1, d2x_rs1;
wire [4:0] rf_rs2, d2x_rs2;
wire [4:0] d2x_rd;
wire [4:0] d2x_shamt;
wire [2:0] d2x_fun;
wire [4:0] d2x_opcode;
wire d2x_shifter_sign;
wire [31:0] d2x_imm_i, d2x_imm_s, d2x_imm_u, d2x_imm_b, d2x_imm_j;
rv_predecode decode
(
.clk_i(clk_i),
.rst_i(rst_i),
.im_data_i(im_data_i),
.f_stall_i(f_stall),
.f_ir_i(f2d_ir),
.f_pc_i(f2d_pc),
.x_pc_o(d2x_pc),
.rf_rs1_o(rf_rs1),
.rf_rs2_o(rf_rs2),
.x_rs1_o(d2x_rs1),
.x_rs2_o(d2x_rs2),
......@@ -166,7 +166,7 @@ module rv_cpu
.x_rs1_value_o(x_rs1_value),
.x_rs2_value_o(x_rs2_value),
.w_rd_i(rf_rd),
.w_rd_value_i(rf_rd_value),
.w_rd_store_i(rf_rd_write),
......@@ -268,24 +268,23 @@ module rv_cpu
x2f_bra_d0 <= x2f_bra;
// load to Rd in W stage while Rs1/Rs2==RD in fetch stage: assert interlock
reg interlock_load;
reg interlock_load_d0 = 0;
reg interlock_load, interlock_load_d0 = 0;
always@*
interlock_load <= x_load_comb && ((d2x_rd == rf_rs1) || (d2x_rd == rf_rs2));
interlock_load <= f_load_hazard && x_load_comb;
always@(posedge clk_i)
interlock_load_d0 <= interlock_load;
if(interlock_load_d0)
interlock_load_d0 <= 0;
else
interlock_load_d0 <= interlock_load;
assign f_stall = x_stall_req || w_stall_req || (interlock_load && !interlock_load_d0);
assign x_stall = x_stall_req || w_stall_req;
// || (interlock_load && !interlock_load_d0);
// || (!f2d_ir_valid);
assign w_stall = 0;
//x_stall_req;
assign x_stall = x_stall_req || w_stall_req || (interlock_load && !interlock_load_d0);
assign w_stall = 0;
assign x_kill = x2f_bra || x2f_bra_d0;
assign f_kill = x2f_bra ;
......
......@@ -29,7 +29,8 @@ module rv_exec
input x_stall_i,
input x_kill_i,
output x_stall_req_o,
output x_stall_req_o,
input [31:0] d_pc_i,
input [4:0] d_rd_i,
......@@ -312,7 +313,8 @@ module rv_exec
w_dm_addr_o <= 0;
end else if (!x_stall_i) begin
end
else begin //if (!x_stall_i) begin
f_branch_target_o <= branch_target;
f_branch_take_o <= branch_take && !x_kill_i && d_valid_i;
......@@ -320,25 +322,29 @@ module rv_exec
// if(!shifter_stall_req)
w_rd_value_o <= rd_value;
w_rd_write_o <= rd_write && !x_kill_i && d_valid_i;
w_fun_o <= d_fun_i;
w_load_o <= is_load;
w_load_o <= is_load;
w_store_o <= is_store;
w_dm_addr_o <= dm_addr;
end else begin // if (!x_stall_i)
f_branch_take_o <= 0;
w_rd_write_o <= 0;
w_load_o <= 0;
w_store_o <= 0;
end
// end else begin // if (!x_stall_i)
// f_branch_take_o <= 0;
// w_rd_write_o <= 0;
// w_load_o <= 0;
// w_store_o <= 0;
// end
end // else: !if(rst_i)
assign x_stall_req_o = shifter_stall_req || ((is_store || is_load) && !dm_ready_i);
assign x_load_o = is_load;
assign x_load_o = is_load;
......
......@@ -31,8 +31,12 @@ module rv_fetch
input f_stall_i,
input f_kill_i,
output reg [4:0] rf_rs1_o,
output reg [4:0] rf_rs2_o,
output reg f_load_hazard_o,
output [31:0] f_ir_o,
output reg [31:0] f_pc_o,
output reg [31:0] f_pc_plus_4_o,
......@@ -44,12 +48,30 @@ module rv_fetch
);
reg [31:0] pc;
reg [31:0] ir, ir_d0;
reg [31:0] ir;
reg rst_d;
wire [4:0] rs1_mem = im_data_i[19:15];
wire [4:0] rs2_mem = im_data_i[24:20];
wire [4:0] rd = ir [11:7];
always@*
if(!f_stall_i)
begin
rf_rs1_o <= im_data_i [19:15];
rf_rs2_o <= im_data_i [24:20];
end else begin
rf_rs1_o <= ir[19:15];
rf_rs2_o <= ir[24:20];
end
reg im_valid_d0;
// wire [31:0] pc_next = (x_bra_i ? x_pc_bra_i : ( ( f_stall_i || !im_valid_i ) ? pc : pc + 4));
always@*
f_load_hazard_o <= ( (rs1_mem == rd) || (rs2_mem == rd) ) && !f_kill_i;
reg [31:0] pc_next;
......@@ -77,8 +99,6 @@ module rv_fetch
end else begin
rst_d <= 1;
if (!f_stall_i) begin
pc <= pc_next;
......@@ -86,19 +106,12 @@ module rv_fetch
if(im_valid_i) begin
ir <= im_data_i; // emit nop
ir_d0 <= ir;
f_valid_o <= (rst_d && !f_kill_i);
end else begin// if (i_valid_i)
f_valid_o <= 0;
end
end else begin // if (!f_stall_i)
// f_stall_req_o <= 0;
end // else: !if(!f_stall_i)
end
end // else: !if(rst_i)
......
......@@ -25,44 +25,41 @@
module rv_predecode
(
input clk_i,
input rst_i,
input clk_i,
input rst_i,
input [31:0] im_data_i,
input [31:0] f_ir_i,
input [31:0] f_pc_i,
input f_stall_i,
input [31:0] im_data_i,
input [31:0] f_ir_i,
input [31:0] f_pc_i,
output [31:0] x_pc_o,
output [31:0] x_pc_o,
output [4:0] rf_rs1_o,
output [4:0] rf_rs2_o,
output [4:0] rf_rs1_o,
output [4:0] rf_rs2_o,
output [4:0] x_rs1_o,
output [4:0] x_rs2_o,
output [4:0] x_rs1_o,
output [4:0] x_rs2_o,
output [4:0] x_rd_o,
output [4:0] x_rd_o,
output [4:0] x_shamt_o,
output reg [2:0] x_fun_o,
output [4:0] x_shamt_o,
output reg [2:0] x_fun_o,
output [4:0] x_opcode_o,
output x_shifter_sign_o,
output [4:0] x_opcode_o,
output x_shifter_sign_o,
output [31:0] x_imm_i_o,
output [31:0] x_imm_s_o,
output [31:0] x_imm_b_o,
output [31:0] x_imm_u_o,
output [31:0] x_imm_j_o
output [31:0] x_imm_i_o,
output [31:0] x_imm_s_o,
output [31:0] x_imm_b_o,
output [31:0] x_imm_u_o,
output [31:0] x_imm_j_o
);
wire [4:0] f_opcode = f_ir_i[6:2];
assign rf_rs1_o = im_data_i [19:15];
assign rf_rs2_o = im_data_i [24:20];
assign x_rs1_o = f_ir_i [19:15];
assign x_rs2_o = f_ir_i [24:20];
......@@ -94,10 +91,17 @@ module rv_predecode
assign x_imm_b_o = { {20{ f_ir_i[31] }}, f_ir_i[7], f_ir_i[30:25], f_ir_i[11:8], 1'b0 };
assign x_imm_u_o = { f_ir_i[31], f_ir_i[30:20], f_ir_i[19:12], 12'h000 };
assign x_imm_j_o = { {12{f_ir_i[31]}},
f_ir_i[19:12],
f_ir_i[20], f_ir_i[30:25], f_ir_i[24:21], 1'b0};
f_ir_i[19:12],
f_ir_i[20], f_ir_i[30:25], f_ir_i[24:21], 1'b0};
assign x_pc_o = f_pc_i;
endmodule // rv_predecode
......
......@@ -150,6 +150,12 @@ module rv_regfile
assign x_rs1_value_o = rs1_bypass ? w_bypass_rd_value_i : rs1_regfile;
assign x_rs2_value_o = rs2_bypass ? w_bypass_rd_value_i : rs2_regfile;
/* wire rs1_bypass = write && (w_rd_i == d_rs1_i);
wire rs2_bypass = write && (w_rd_i == d_rs2_i);
assign x_rs1_value_o = rs1_bypass ? w_rd_value_i : rs1_regfile;
assign x_rs2_value_o = rs2_bypass ? w_rd_value_i : rs2_regfile;*/
endmodule // rv_regfile
......
......@@ -35,7 +35,7 @@ module rv_writeback
input x_load_i,
input x_store_i,
input x_load_hazard_i,
input [31:0] x_dm_addr_i,
input [4:0] x_rd_i,
input [31:0] x_rd_value_i,
......
......@@ -3,6 +3,8 @@ quietly WaveActivateNextPane {} 0
add wave -noupdate /main/DUT/clk_i
add wave -noupdate /main/DUT/rst_i
add wave -noupdate -expand -group cpu /main/DUT/clk_i
add wave -noupdate -expand -group cpu /main/DUT/rst_i
add wave -noupdate -expand -group cpu /main/DUT/im_addr_o
add wave -noupdate -expand -group cpu /main/DUT/im_data_i
add wave -noupdate -expand -group cpu /main/DUT/im_valid_i
add wave -noupdate -expand -group cpu /main/DUT/dm_addr_o
......@@ -14,16 +16,24 @@ add wave -noupdate -expand -group cpu /main/DUT/dm_store_o
add wave -noupdate -expand -group cpu /main/DUT/dm_load_o
add wave -noupdate -expand -group cpu /main/DUT/dm_load_done_i
add wave -noupdate -expand -group cpu /main/DUT/dm_store_done_i
add wave -noupdate -expand -group cpu /main/DUT/rst_i
add wave -noupdate -expand -group cpu /main/DUT/f_stall
add wave -noupdate -expand -group cpu /main/DUT/w_stall
add wave -noupdate -expand -group cpu /main/DUT/x_stall
add wave -noupdate -expand -group cpu /main/DUT/x_kill
add wave -noupdate -expand -group cpu /main/DUT/f_kill
add wave -noupdate -expand -group cpu /main/DUT/f2d_pc
add wave -noupdate -expand -group cpu /main/DUT/f2d_pc_plus_4
add wave -noupdate -expand -group cpu /main/DUT/f2d_ir
add wave -noupdate -expand -group cpu /main/DUT/f2d_ir_valid
add wave -noupdate -expand -group cpu /main/DUT/x2f_pc_bra
add wave -noupdate -expand -group cpu /main/DUT/x2f_bra
add wave -noupdate -expand -group cpu /main/DUT/f2d_valid
add wave -noupdate -expand -group cpu /main/DUT/f_stall_req
add wave -noupdate -expand -group cpu /main/DUT/d2x_pc
add wave -noupdate -expand -group cpu /main/DUT/rf_rs2
add wave -noupdate -expand -group cpu /main/DUT/rf_rs1
add wave -noupdate -expand -group cpu /main/DUT/d2x_rs1
add wave -noupdate -expand -group cpu /main/DUT/rf_rs2
add wave -noupdate -expand -group cpu /main/DUT/d2x_rs2
add wave -noupdate -expand -group cpu /main/DUT/d2x_rd
add wave -noupdate -expand -group cpu /main/DUT/d2x_shamt
add wave -noupdate -expand -group cpu /main/DUT/d2x_fun
......@@ -31,26 +41,53 @@ add wave -noupdate -expand -group cpu /main/DUT/d2x_opcode
add wave -noupdate -expand -group cpu /main/DUT/d2x_shifter_sign
add wave -noupdate -expand -group cpu /main/DUT/d2x_imm_i
add wave -noupdate -expand -group cpu /main/DUT/d2x_imm_s
add wave -noupdate -expand -group cpu /main/DUT/d2x_imm_b
add wave -noupdate -expand -group cpu /main/DUT/d2x_imm_u
add wave -noupdate -expand -group cpu /main/DUT/d2x_imm_b
add wave -noupdate -expand -group cpu /main/DUT/d2x_imm_j
add wave -noupdate /main/DUT/interlock_load
add wave -noupdate -expand -group cpu /main/DUT/f_load_hazard
add wave -noupdate -expand -group cpu /main/DUT/x2w_rd
add wave -noupdate -expand -group cpu /main/DUT/x2w_rd_value
add wave -noupdate -expand -group cpu /main/DUT/x2w_dm_addr
add wave -noupdate -expand -group cpu /main/DUT/x2w_rd_write
add wave -noupdate -expand -group cpu /main/DUT/x2w_fun
add wave -noupdate -expand -group cpu /main/DUT/x2w_store
add wave -noupdate -expand -group cpu /main/DUT/x2w_load
add wave -noupdate -expand -group cpu /main/DUT/x_rs2_value
add wave -noupdate -expand -group cpu /main/DUT/x_rs1_value
add wave -noupdate -expand -group cpu /main/DUT/rf_rd
add wave -noupdate -expand -group cpu /main/DUT/rf_rd_value
add wave -noupdate -expand -group cpu /main/DUT/rf_rd_write
add wave -noupdate -expand -group cpu /main/DUT/rf_bypass_rd_value
add wave -noupdate -expand -group cpu /main/DUT/rf_bypass_rd_write
add wave -noupdate -expand -group cpu /main/DUT/x_load_comb
add wave -noupdate -expand -group cpu /main/DUT/x_stall_req
add wave -noupdate -expand -group cpu /main/DUT/w_stall_req
add wave -noupdate -expand -group cpu /main/DUT/x2f_bra_d0
add wave -noupdate -expand -group cpu /main/DUT/interlock_load
add wave -noupdate -expand -group cpu /main/DUT/interlock_load_d0
add wave -noupdate -expand -group cpu /main/DUT/stall_tmp
add wave -noupdate -expand -group fetch /main/DUT/fetch/clk_i
add wave -noupdate -expand -group fetch /main/DUT/fetch/rst_i
add wave -noupdate -expand -group fetch /main/DUT/fetch/im_addr_o
add wave -noupdate -expand -group fetch /main/DUT/fetch/im_data_i
add wave -noupdate -expand -group fetch /main/DUT/fetch/im_valid_i
add wave -noupdate -expand -group fetch /main/DUT/fetch/im_valid_d0
add wave -noupdate -expand -group fetch /main/DUT/fetch/f_stall_i
add wave -noupdate -expand -group fetch /main/DUT/fetch/f_kill_i
add wave -noupdate -expand -group fetch /main/DUT/fetch/rf_rs1_o
add wave -noupdate -expand -group fetch /main/DUT/fetch/rf_rs2_o
add wave -noupdate -expand -group fetch /main/DUT/fetch/f_load_hazard_o
add wave -noupdate -expand -group fetch /main/DUT/fetch/f_ir_o
add wave -noupdate -expand -group fetch /main/DUT/fetch/f_pc_o
add wave -noupdate -expand -group fetch /main/DUT/fetch/f_pc_plus_4_o
add wave -noupdate -expand -group fetch /main/DUT/fetch/f_valid_o
add wave -noupdate -expand -group fetch /main/DUT/fetch/x_pc_bra_i
add wave -noupdate -expand -group fetch /main/DUT/fetch/x_bra_i
add wave -noupdate -expand -group fetch /main/DUT/fetch/pc
add wave -noupdate -expand -group fetch /main/DUT/fetch/ir
add wave -noupdate -expand -group fetch /main/DUT/fetch/rst_d
add wave -noupdate -expand -group fetch /main/DUT/fetch/rs1_mem
add wave -noupdate -expand -group fetch /main/DUT/fetch/rs2_mem
add wave -noupdate -expand -group fetch /main/DUT/fetch/rd
add wave -noupdate -expand -group fetch /main/DUT/fetch/pc_next
add wave -noupdate -group decode /main/DUT/decode/clk_i
add wave -noupdate -group decode /main/DUT/decode/rst_i
......@@ -185,7 +222,7 @@ add wave -noupdate -expand -group writeback /main/DUT/writeback/rf_rd_o
add wave -noupdate -expand -group writeback /main/DUT/writeback/rf_rd_write_o
add wave -noupdate -expand -group writeback /main/DUT/writeback/load_value
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {13948780 ps} 0}
WaveRestoreCursors {{Cursor 1} {140034 ps} 0}
configure wave -namecolwidth 250
configure wave -valuecolwidth 100
configure wave -justifyvalue left
......@@ -200,4 +237,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {13882681 ps} {14027319 ps}
WaveRestoreZoom {0 ps} {289276 ps}
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