diff --git a/doc/tdc.tex b/doc/tdc.tex
index d6c69be9e4dca73eb63242c9a143f51b8620fc6e..682eb0a0599c894446237e28c0a60601c2443525 100644
--- a/doc/tdc.tex
+++ b/doc/tdc.tex
@@ -229,6 +229,11 @@ The delay line must be placed in a way that minimizes the delay from the input s
 To be most effective, the ring oscillator must be placed close to the delay line of the same channel.
 
 \section{Host interface module}
+The optional host interface module connects the TDC core to a Wishbone bus. It is a separate top-level entity named \verb!tdc_hostif! that instantiates \verb!tdc!. It implements a Wishbone slave interface, which is automatically generated with \verb!wbgen2!.
+
+It supports a maximum of 8 channels. The debug interface of the TDC core is also exposed through the Wishbone interface. Interrupts are generated at the end of the startup calibration, on a coarse counter overflow, and after each transition of the input signals.
+
+Generics and ports should be self-explanatory. Refer to the documentation generated by \verb!wbgen2! for a description of the registers and interrupts. Run the \verb!genwb.py! script to generate the \verb!wb! file for \verb!wbgen2!.
 
 \begin{thebibliography}{99}
 \bibitem{s6hdl} Xilinx, \textsl{Spartan-6 Libraries Guide for HDL Designs}, \url{http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_3/spartan6_hdl.pdf}