From 291fce0ad7513ed072201ea6239c15fea5a18ad5 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Sat, 27 Aug 2011 17:31:48 +0200
Subject: [PATCH] hostif: reduce max channels to 8
---
hostif/genconn.py | 2 +-
hostif/genwb.py | 2 +-
hostif/tdc_hostif.vhd | 139 +--
hostif/tdc_hostif_package.vhd | 249 +----
hostif/tdc_wb.vhd | 1596 ++++-----------------------------
5 files changed, 181 insertions(+), 1807 deletions(-)
diff --git a/hostif/genconn.py b/hostif/genconn.py
index dc2b998..a8669de 100755
--- a/hostif/genconn.py
+++ b/hostif/genconn.py
@@ -1,6 +1,6 @@
#!/usr/bin/python
-nchan = 30
+nchan = 8
for i in range(0,nchan):
print "tdc_desh%d_o => wbg_des(%d downto %d)," % (i, i*64+63, i*64+32)
diff --git a/hostif/genwb.py b/hostif/genwb.py
index 5d6c8c0..bb41748 100755
--- a/hostif/genwb.py
+++ b/hostif/genwb.py
@@ -1,6 +1,6 @@
#!/usr/bin/python
-nchan = 30
+nchan = 8
print "peripheral {"
print " name = \"TDC\";"
diff --git a/hostif/tdc_hostif.vhd b/hostif/tdc_hostif.vhd
index 1670d03..22f24f8 100644
--- a/hostif/tdc_hostif.vhd
+++ b/hostif/tdc_hostif.vhd
@@ -12,6 +12,7 @@
--
-------------------------------------------------------------------------------
-- last changes:
+-- 2011-08-27 SB Reduced supported channel count to 8
-- 2011-08-26 SB Created file
-------------------------------------------------------------------------------
@@ -39,7 +40,7 @@ entity tdc_hostif is
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
- wb_addr_i : in std_logic_vector(7 downto 0);
+ wb_addr_i : in std_logic_vector(5 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
@@ -87,7 +88,7 @@ signal wbg_fcr : std_logic_vector(31 downto 0);
signal wbg_fcsr : std_logic_vector(31 downto 0);
-- maximum number of channels the host interface can support
-constant c_NCHAN: positive := 30;
+constant c_NCHAN: positive := 8;
signal wbg_des : std_logic_vector(c_NCHAN*64-1 downto 0);
signal wbg_pol : std_logic_vector(c_NCHAN-1 downto 0);
@@ -187,50 +188,6 @@ begin
tdc_desl6_o => wbg_des(415 downto 384),
tdc_desh7_o => wbg_des(511 downto 480),
tdc_desl7_o => wbg_des(479 downto 448),
- tdc_desh8_o => wbg_des(575 downto 544),
- tdc_desl8_o => wbg_des(543 downto 512),
- tdc_desh9_o => wbg_des(639 downto 608),
- tdc_desl9_o => wbg_des(607 downto 576),
- tdc_desh10_o => wbg_des(703 downto 672),
- tdc_desl10_o => wbg_des(671 downto 640),
- tdc_desh11_o => wbg_des(767 downto 736),
- tdc_desl11_o => wbg_des(735 downto 704),
- tdc_desh12_o => wbg_des(831 downto 800),
- tdc_desl12_o => wbg_des(799 downto 768),
- tdc_desh13_o => wbg_des(895 downto 864),
- tdc_desl13_o => wbg_des(863 downto 832),
- tdc_desh14_o => wbg_des(959 downto 928),
- tdc_desl14_o => wbg_des(927 downto 896),
- tdc_desh15_o => wbg_des(1023 downto 992),
- tdc_desl15_o => wbg_des(991 downto 960),
- tdc_desh16_o => wbg_des(1087 downto 1056),
- tdc_desl16_o => wbg_des(1055 downto 1024),
- tdc_desh17_o => wbg_des(1151 downto 1120),
- tdc_desl17_o => wbg_des(1119 downto 1088),
- tdc_desh18_o => wbg_des(1215 downto 1184),
- tdc_desl18_o => wbg_des(1183 downto 1152),
- tdc_desh19_o => wbg_des(1279 downto 1248),
- tdc_desl19_o => wbg_des(1247 downto 1216),
- tdc_desh20_o => wbg_des(1343 downto 1312),
- tdc_desl20_o => wbg_des(1311 downto 1280),
- tdc_desh21_o => wbg_des(1407 downto 1376),
- tdc_desl21_o => wbg_des(1375 downto 1344),
- tdc_desh22_o => wbg_des(1471 downto 1440),
- tdc_desl22_o => wbg_des(1439 downto 1408),
- tdc_desh23_o => wbg_des(1535 downto 1504),
- tdc_desl23_o => wbg_des(1503 downto 1472),
- tdc_desh24_o => wbg_des(1599 downto 1568),
- tdc_desl24_o => wbg_des(1567 downto 1536),
- tdc_desh25_o => wbg_des(1663 downto 1632),
- tdc_desl25_o => wbg_des(1631 downto 1600),
- tdc_desh26_o => wbg_des(1727 downto 1696),
- tdc_desl26_o => wbg_des(1695 downto 1664),
- tdc_desh27_o => wbg_des(1791 downto 1760),
- tdc_desl27_o => wbg_des(1759 downto 1728),
- tdc_desh28_o => wbg_des(1855 downto 1824),
- tdc_desl28_o => wbg_des(1823 downto 1792),
- tdc_desh29_o => wbg_des(1919 downto 1888),
- tdc_desl29_o => wbg_des(1887 downto 1856),
tdc_raw0_i => wbg_raw(31 downto 0),
tdc_mesh0_i => wbg_mes(63 downto 32),
tdc_mesl0_i => wbg_mes(31 downto 0),
@@ -255,72 +212,6 @@ begin
tdc_raw7_i => wbg_raw(255 downto 224),
tdc_mesh7_i => wbg_mes(511 downto 480),
tdc_mesl7_i => wbg_mes(479 downto 448),
- tdc_raw8_i => wbg_raw(287 downto 256),
- tdc_mesh8_i => wbg_mes(575 downto 544),
- tdc_mesl8_i => wbg_mes(543 downto 512),
- tdc_raw9_i => wbg_raw(319 downto 288),
- tdc_mesh9_i => wbg_mes(639 downto 608),
- tdc_mesl9_i => wbg_mes(607 downto 576),
- tdc_raw10_i => wbg_raw(351 downto 320),
- tdc_mesh10_i => wbg_mes(703 downto 672),
- tdc_mesl10_i => wbg_mes(671 downto 640),
- tdc_raw11_i => wbg_raw(383 downto 352),
- tdc_mesh11_i => wbg_mes(767 downto 736),
- tdc_mesl11_i => wbg_mes(735 downto 704),
- tdc_raw12_i => wbg_raw(415 downto 384),
- tdc_mesh12_i => wbg_mes(831 downto 800),
- tdc_mesl12_i => wbg_mes(799 downto 768),
- tdc_raw13_i => wbg_raw(447 downto 416),
- tdc_mesh13_i => wbg_mes(895 downto 864),
- tdc_mesl13_i => wbg_mes(863 downto 832),
- tdc_raw14_i => wbg_raw(479 downto 448),
- tdc_mesh14_i => wbg_mes(959 downto 928),
- tdc_mesl14_i => wbg_mes(927 downto 896),
- tdc_raw15_i => wbg_raw(511 downto 480),
- tdc_mesh15_i => wbg_mes(1023 downto 992),
- tdc_mesl15_i => wbg_mes(991 downto 960),
- tdc_raw16_i => wbg_raw(543 downto 512),
- tdc_mesh16_i => wbg_mes(1087 downto 1056),
- tdc_mesl16_i => wbg_mes(1055 downto 1024),
- tdc_raw17_i => wbg_raw(575 downto 544),
- tdc_mesh17_i => wbg_mes(1151 downto 1120),
- tdc_mesl17_i => wbg_mes(1119 downto 1088),
- tdc_raw18_i => wbg_raw(607 downto 576),
- tdc_mesh18_i => wbg_mes(1215 downto 1184),
- tdc_mesl18_i => wbg_mes(1183 downto 1152),
- tdc_raw19_i => wbg_raw(639 downto 608),
- tdc_mesh19_i => wbg_mes(1279 downto 1248),
- tdc_mesl19_i => wbg_mes(1247 downto 1216),
- tdc_raw20_i => wbg_raw(671 downto 640),
- tdc_mesh20_i => wbg_mes(1343 downto 1312),
- tdc_mesl20_i => wbg_mes(1311 downto 1280),
- tdc_raw21_i => wbg_raw(703 downto 672),
- tdc_mesh21_i => wbg_mes(1407 downto 1376),
- tdc_mesl21_i => wbg_mes(1375 downto 1344),
- tdc_raw22_i => wbg_raw(735 downto 704),
- tdc_mesh22_i => wbg_mes(1471 downto 1440),
- tdc_mesl22_i => wbg_mes(1439 downto 1408),
- tdc_raw23_i => wbg_raw(767 downto 736),
- tdc_mesh23_i => wbg_mes(1535 downto 1504),
- tdc_mesl23_i => wbg_mes(1503 downto 1472),
- tdc_raw24_i => wbg_raw(799 downto 768),
- tdc_mesh24_i => wbg_mes(1599 downto 1568),
- tdc_mesl24_i => wbg_mes(1567 downto 1536),
- tdc_raw25_i => wbg_raw(831 downto 800),
- tdc_mesh25_i => wbg_mes(1663 downto 1632),
- tdc_mesl25_i => wbg_mes(1631 downto 1600),
- tdc_raw26_i => wbg_raw(863 downto 832),
- tdc_mesh26_i => wbg_mes(1727 downto 1696),
- tdc_mesl26_i => wbg_mes(1695 downto 1664),
- tdc_raw27_i => wbg_raw(895 downto 864),
- tdc_mesh27_i => wbg_mes(1791 downto 1760),
- tdc_mesl27_i => wbg_mes(1759 downto 1728),
- tdc_raw28_i => wbg_raw(927 downto 896),
- tdc_mesh28_i => wbg_mes(1855 downto 1824),
- tdc_mesl28_i => wbg_mes(1823 downto 1792),
- tdc_raw29_i => wbg_raw(959 downto 928),
- tdc_mesh29_i => wbg_mes(1919 downto 1888),
- tdc_mesl29_i => wbg_mes(1887 downto 1856),
irq_ie0_i => wbg_ie(0),
irq_ie1_i => wbg_ie(1),
irq_ie2_i => wbg_ie(2),
@@ -328,29 +219,7 @@ begin
irq_ie4_i => wbg_ie(4),
irq_ie5_i => wbg_ie(5),
irq_ie6_i => wbg_ie(6),
- irq_ie7_i => wbg_ie(7),
- irq_ie8_i => wbg_ie(8),
- irq_ie9_i => wbg_ie(9),
- irq_ie10_i => wbg_ie(10),
- irq_ie11_i => wbg_ie(11),
- irq_ie12_i => wbg_ie(12),
- irq_ie13_i => wbg_ie(13),
- irq_ie14_i => wbg_ie(14),
- irq_ie15_i => wbg_ie(15),
- irq_ie16_i => wbg_ie(16),
- irq_ie17_i => wbg_ie(17),
- irq_ie18_i => wbg_ie(18),
- irq_ie19_i => wbg_ie(19),
- irq_ie20_i => wbg_ie(20),
- irq_ie21_i => wbg_ie(21),
- irq_ie22_i => wbg_ie(22),
- irq_ie23_i => wbg_ie(23),
- irq_ie24_i => wbg_ie(24),
- irq_ie25_i => wbg_ie(25),
- irq_ie26_i => wbg_ie(26),
- irq_ie27_i => wbg_ie(27),
- irq_ie28_i => wbg_ie(28),
- irq_ie29_i => wbg_ie(29)
+ irq_ie7_i => wbg_ie(7)
-- end autogenerated connections
);
diff --git a/hostif/tdc_hostif_package.vhd b/hostif/tdc_hostif_package.vhd
index cd10c0b..37b8b9f 100644
--- a/hostif/tdc_hostif_package.vhd
+++ b/hostif/tdc_hostif_package.vhd
@@ -12,6 +12,7 @@
--
-------------------------------------------------------------------------------
-- last changes:
+-- 2011-08-27 SB Reduced supported channel count to 8
-- 2011-08-25 SB Created file
-------------------------------------------------------------------------------
@@ -37,7 +38,7 @@ component tdc_hostif is
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
- wb_addr_i : in std_logic_vector(7 downto 0);
+ wb_addr_i : in std_logic_vector(5 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
@@ -58,7 +59,7 @@ component tdc_wb is
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
- wb_addr_i : in std_logic_vector(7 downto 0);
+ wb_addr_i : in std_logic_vector(5 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
@@ -103,96 +104,8 @@ component tdc_wb is
tdc_desh7_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 7 (low word)'
tdc_desl7_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 8 (high word)'
- tdc_desh8_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 8 (low word)'
- tdc_desl8_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 9 (high word)'
- tdc_desh9_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 9 (low word)'
- tdc_desl9_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 10 (high word)'
- tdc_desh10_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 10 (low word)'
- tdc_desl10_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 11 (high word)'
- tdc_desh11_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 11 (low word)'
- tdc_desl11_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 12 (high word)'
- tdc_desh12_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 12 (low word)'
- tdc_desl12_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 13 (high word)'
- tdc_desh13_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 13 (low word)'
- tdc_desl13_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 14 (high word)'
- tdc_desh14_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 14 (low word)'
- tdc_desl14_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 15 (high word)'
- tdc_desh15_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 15 (low word)'
- tdc_desl15_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 16 (high word)'
- tdc_desh16_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 16 (low word)'
- tdc_desl16_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 17 (high word)'
- tdc_desh17_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 17 (low word)'
- tdc_desl17_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 18 (high word)'
- tdc_desh18_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 18 (low word)'
- tdc_desl18_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 19 (high word)'
- tdc_desh19_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 19 (low word)'
- tdc_desl19_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 20 (high word)'
- tdc_desh20_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 20 (low word)'
- tdc_desl20_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 21 (high word)'
- tdc_desh21_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 21 (low word)'
- tdc_desl21_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 22 (high word)'
- tdc_desh22_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 22 (low word)'
- tdc_desl22_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 23 (high word)'
- tdc_desh23_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 23 (low word)'
- tdc_desl23_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 24 (high word)'
- tdc_desh24_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 24 (low word)'
- tdc_desl24_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 25 (high word)'
- tdc_desh25_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 25 (low word)'
- tdc_desl25_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 26 (high word)'
- tdc_desh26_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 26 (low word)'
- tdc_desl26_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 27 (high word)'
- tdc_desh27_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 27 (low word)'
- tdc_desl27_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 28 (high word)'
- tdc_desh28_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 28 (low word)'
- tdc_desl28_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 29 (high word)'
- tdc_desh29_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 29 (low word)'
- tdc_desl29_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Value' in reg: 'Detected polarities'
- tdc_pol_i : in std_logic_vector(29 downto 0);
+ tdc_pol_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 0'
tdc_raw0_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 0 (high word)'
@@ -241,138 +154,6 @@ component tdc_wb is
tdc_mesh7_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 7 (low word)'
tdc_mesl7_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 8'
- tdc_raw8_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 8 (high word)'
- tdc_mesh8_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 8 (low word)'
- tdc_mesl8_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 9'
- tdc_raw9_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 9 (high word)'
- tdc_mesh9_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 9 (low word)'
- tdc_mesl9_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 10'
- tdc_raw10_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 10 (high word)'
- tdc_mesh10_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 10 (low word)'
- tdc_mesl10_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 11'
- tdc_raw11_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 11 (high word)'
- tdc_mesh11_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 11 (low word)'
- tdc_mesl11_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 12'
- tdc_raw12_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 12 (high word)'
- tdc_mesh12_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 12 (low word)'
- tdc_mesl12_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 13'
- tdc_raw13_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 13 (high word)'
- tdc_mesh13_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 13 (low word)'
- tdc_mesl13_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 14'
- tdc_raw14_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 14 (high word)'
- tdc_mesh14_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 14 (low word)'
- tdc_mesl14_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 15'
- tdc_raw15_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 15 (high word)'
- tdc_mesh15_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 15 (low word)'
- tdc_mesl15_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 16'
- tdc_raw16_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 16 (high word)'
- tdc_mesh16_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 16 (low word)'
- tdc_mesl16_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 17'
- tdc_raw17_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 17 (high word)'
- tdc_mesh17_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 17 (low word)'
- tdc_mesl17_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 18'
- tdc_raw18_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 18 (high word)'
- tdc_mesh18_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 18 (low word)'
- tdc_mesl18_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 19'
- tdc_raw19_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 19 (high word)'
- tdc_mesh19_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 19 (low word)'
- tdc_mesl19_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 20'
- tdc_raw20_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 20 (high word)'
- tdc_mesh20_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 20 (low word)'
- tdc_mesl20_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 21'
- tdc_raw21_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 21 (high word)'
- tdc_mesh21_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 21 (low word)'
- tdc_mesl21_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 22'
- tdc_raw22_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 22 (high word)'
- tdc_mesh22_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 22 (low word)'
- tdc_mesl22_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 23'
- tdc_raw23_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 23 (high word)'
- tdc_mesh23_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 23 (low word)'
- tdc_mesl23_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 24'
- tdc_raw24_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 24 (high word)'
- tdc_mesh24_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 24 (low word)'
- tdc_mesl24_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 25'
- tdc_raw25_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 25 (high word)'
- tdc_mesh25_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 25 (low word)'
- tdc_mesl25_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 26'
- tdc_raw26_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 26 (high word)'
- tdc_mesh26_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 26 (low word)'
- tdc_mesl26_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 27'
- tdc_raw27_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 27 (high word)'
- tdc_mesh27_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 27 (low word)'
- tdc_mesl27_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 28'
- tdc_raw28_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 28 (high word)'
- tdc_mesh28_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 28 (low word)'
- tdc_mesl28_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 29'
- tdc_raw29_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 29 (high word)'
- tdc_mesh29_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 29 (low word)'
- tdc_mesl29_i : in std_logic_vector(31 downto 0);
irq_ie0_i : in std_logic;
irq_ie1_i : in std_logic;
irq_ie2_i : in std_logic;
@@ -381,28 +162,6 @@ component tdc_wb is
irq_ie5_i : in std_logic;
irq_ie6_i : in std_logic;
irq_ie7_i : in std_logic;
- irq_ie8_i : in std_logic;
- irq_ie9_i : in std_logic;
- irq_ie10_i : in std_logic;
- irq_ie11_i : in std_logic;
- irq_ie12_i : in std_logic;
- irq_ie13_i : in std_logic;
- irq_ie14_i : in std_logic;
- irq_ie15_i : in std_logic;
- irq_ie16_i : in std_logic;
- irq_ie17_i : in std_logic;
- irq_ie18_i : in std_logic;
- irq_ie19_i : in std_logic;
- irq_ie20_i : in std_logic;
- irq_ie21_i : in std_logic;
- irq_ie22_i : in std_logic;
- irq_ie23_i : in std_logic;
- irq_ie24_i : in std_logic;
- irq_ie25_i : in std_logic;
- irq_ie26_i : in std_logic;
- irq_ie27_i : in std_logic;
- irq_ie28_i : in std_logic;
- irq_ie29_i : in std_logic;
irq_isc_i : in std_logic;
irq_icc_i : in std_logic;
-- Port for BIT field: 'Freeze request' in reg: 'Debug control'
diff --git a/hostif/tdc_wb.vhd b/hostif/tdc_wb.vhd
index 6cc48b8..9fe9fd1 100644
--- a/hostif/tdc_wb.vhd
+++ b/hostif/tdc_wb.vhd
@@ -2,11 +2,11 @@
-- Title : Wishbone slave core for TDC
---------------------------------------------------------------------------------------
-- File : tdc_wb.vhd
--- Author : auto-generated by wbgen2 from tdc.wb
--- Created : Thu Aug 25 22:28:17 2011
+-- Author : auto-generated by wbgen2 from tdc_wb.wb
+-- Created : Sat Aug 27 17:26:44 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
--- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE tdc.wb
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE tdc_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
@@ -19,7 +19,7 @@ entity tdc_wb is
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
- wb_addr_i : in std_logic_vector(7 downto 0);
+ wb_addr_i : in std_logic_vector(5 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
@@ -64,96 +64,8 @@ entity tdc_wb is
tdc_desh7_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 7 (low word)'
tdc_desl7_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 8 (high word)'
- tdc_desh8_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 8 (low word)'
- tdc_desl8_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 9 (high word)'
- tdc_desh9_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 9 (low word)'
- tdc_desl9_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 10 (high word)'
- tdc_desh10_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 10 (low word)'
- tdc_desl10_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 11 (high word)'
- tdc_desh11_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 11 (low word)'
- tdc_desl11_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 12 (high word)'
- tdc_desh12_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 12 (low word)'
- tdc_desl12_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 13 (high word)'
- tdc_desh13_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 13 (low word)'
- tdc_desl13_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 14 (high word)'
- tdc_desh14_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 14 (low word)'
- tdc_desl14_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 15 (high word)'
- tdc_desh15_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 15 (low word)'
- tdc_desl15_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 16 (high word)'
- tdc_desh16_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 16 (low word)'
- tdc_desl16_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 17 (high word)'
- tdc_desh17_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 17 (low word)'
- tdc_desl17_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 18 (high word)'
- tdc_desh18_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 18 (low word)'
- tdc_desl18_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 19 (high word)'
- tdc_desh19_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 19 (low word)'
- tdc_desl19_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 20 (high word)'
- tdc_desh20_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 20 (low word)'
- tdc_desl20_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 21 (high word)'
- tdc_desh21_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 21 (low word)'
- tdc_desl21_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 22 (high word)'
- tdc_desh22_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 22 (low word)'
- tdc_desl22_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 23 (high word)'
- tdc_desh23_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 23 (low word)'
- tdc_desl23_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 24 (high word)'
- tdc_desh24_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 24 (low word)'
- tdc_desl24_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 25 (high word)'
- tdc_desh25_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 25 (low word)'
- tdc_desl25_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 26 (high word)'
- tdc_desh26_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 26 (low word)'
- tdc_desl26_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 27 (high word)'
- tdc_desh27_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 27 (low word)'
- tdc_desl27_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 28 (high word)'
- tdc_desh28_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 28 (low word)'
- tdc_desl28_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Deskew value for channel 29 (high word)'
- tdc_desh29_o : out std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Deskew value for channel 29 (low word)'
- tdc_desl29_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Value' in reg: 'Detected polarities'
- tdc_pol_i : in std_logic_vector(29 downto 0);
+ tdc_pol_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 0'
tdc_raw0_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 0 (high word)'
@@ -202,138 +114,6 @@ entity tdc_wb is
tdc_mesh7_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 7 (low word)'
tdc_mesl7_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 8'
- tdc_raw8_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 8 (high word)'
- tdc_mesh8_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 8 (low word)'
- tdc_mesl8_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 9'
- tdc_raw9_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 9 (high word)'
- tdc_mesh9_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 9 (low word)'
- tdc_mesl9_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 10'
- tdc_raw10_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 10 (high word)'
- tdc_mesh10_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 10 (low word)'
- tdc_mesl10_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 11'
- tdc_raw11_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 11 (high word)'
- tdc_mesh11_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 11 (low word)'
- tdc_mesl11_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 12'
- tdc_raw12_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 12 (high word)'
- tdc_mesh12_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 12 (low word)'
- tdc_mesl12_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 13'
- tdc_raw13_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 13 (high word)'
- tdc_mesh13_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 13 (low word)'
- tdc_mesl13_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 14'
- tdc_raw14_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 14 (high word)'
- tdc_mesh14_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 14 (low word)'
- tdc_mesl14_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 15'
- tdc_raw15_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 15 (high word)'
- tdc_mesh15_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 15 (low word)'
- tdc_mesl15_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 16'
- tdc_raw16_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 16 (high word)'
- tdc_mesh16_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 16 (low word)'
- tdc_mesl16_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 17'
- tdc_raw17_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 17 (high word)'
- tdc_mesh17_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 17 (low word)'
- tdc_mesl17_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 18'
- tdc_raw18_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 18 (high word)'
- tdc_mesh18_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 18 (low word)'
- tdc_mesl18_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 19'
- tdc_raw19_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 19 (high word)'
- tdc_mesh19_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 19 (low word)'
- tdc_mesl19_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 20'
- tdc_raw20_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 20 (high word)'
- tdc_mesh20_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 20 (low word)'
- tdc_mesl20_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 21'
- tdc_raw21_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 21 (high word)'
- tdc_mesh21_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 21 (low word)'
- tdc_mesl21_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 22'
- tdc_raw22_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 22 (high word)'
- tdc_mesh22_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 22 (low word)'
- tdc_mesl22_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 23'
- tdc_raw23_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 23 (high word)'
- tdc_mesh23_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 23 (low word)'
- tdc_mesl23_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 24'
- tdc_raw24_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 24 (high word)'
- tdc_mesh24_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 24 (low word)'
- tdc_mesl24_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 25'
- tdc_raw25_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 25 (high word)'
- tdc_mesh25_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 25 (low word)'
- tdc_mesl25_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 26'
- tdc_raw26_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 26 (high word)'
- tdc_mesh26_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 26 (low word)'
- tdc_mesl26_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 27'
- tdc_raw27_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 27 (high word)'
- tdc_mesh27_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 27 (low word)'
- tdc_mesl27_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 28'
- tdc_raw28_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 28 (high word)'
- tdc_mesh28_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 28 (low word)'
- tdc_mesl28_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Value' in reg: 'Raw measured value for channel 29'
- tdc_raw29_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'High word value' in reg: 'Fixed point measurement for channel 29 (high word)'
- tdc_mesh29_i : in std_logic_vector(31 downto 0);
--- Port for std_logic_vector field: 'Low word value' in reg: 'Fixed point measurement for channel 29 (low word)'
- tdc_mesl29_i : in std_logic_vector(31 downto 0);
irq_ie0_i : in std_logic;
irq_ie1_i : in std_logic;
irq_ie2_i : in std_logic;
@@ -342,28 +122,6 @@ entity tdc_wb is
irq_ie5_i : in std_logic;
irq_ie6_i : in std_logic;
irq_ie7_i : in std_logic;
- irq_ie8_i : in std_logic;
- irq_ie9_i : in std_logic;
- irq_ie10_i : in std_logic;
- irq_ie11_i : in std_logic;
- irq_ie12_i : in std_logic;
- irq_ie13_i : in std_logic;
- irq_ie14_i : in std_logic;
- irq_ie15_i : in std_logic;
- irq_ie16_i : in std_logic;
- irq_ie17_i : in std_logic;
- irq_ie18_i : in std_logic;
- irq_ie19_i : in std_logic;
- irq_ie20_i : in std_logic;
- irq_ie21_i : in std_logic;
- irq_ie22_i : in std_logic;
- irq_ie23_i : in std_logic;
- irq_ie24_i : in std_logic;
- irq_ie25_i : in std_logic;
- irq_ie26_i : in std_logic;
- irq_ie27_i : in std_logic;
- irq_ie28_i : in std_logic;
- irq_ie29_i : in std_logic;
irq_isc_i : in std_logic;
irq_icc_i : in std_logic;
-- Port for BIT field: 'Freeze request' in reg: 'Debug control'
@@ -415,50 +173,6 @@ signal tdc_desh6_int : std_logic_vector(31 downto 0);
signal tdc_desl6_int : std_logic_vector(31 downto 0);
signal tdc_desh7_int : std_logic_vector(31 downto 0);
signal tdc_desl7_int : std_logic_vector(31 downto 0);
-signal tdc_desh8_int : std_logic_vector(31 downto 0);
-signal tdc_desl8_int : std_logic_vector(31 downto 0);
-signal tdc_desh9_int : std_logic_vector(31 downto 0);
-signal tdc_desl9_int : std_logic_vector(31 downto 0);
-signal tdc_desh10_int : std_logic_vector(31 downto 0);
-signal tdc_desl10_int : std_logic_vector(31 downto 0);
-signal tdc_desh11_int : std_logic_vector(31 downto 0);
-signal tdc_desl11_int : std_logic_vector(31 downto 0);
-signal tdc_desh12_int : std_logic_vector(31 downto 0);
-signal tdc_desl12_int : std_logic_vector(31 downto 0);
-signal tdc_desh13_int : std_logic_vector(31 downto 0);
-signal tdc_desl13_int : std_logic_vector(31 downto 0);
-signal tdc_desh14_int : std_logic_vector(31 downto 0);
-signal tdc_desl14_int : std_logic_vector(31 downto 0);
-signal tdc_desh15_int : std_logic_vector(31 downto 0);
-signal tdc_desl15_int : std_logic_vector(31 downto 0);
-signal tdc_desh16_int : std_logic_vector(31 downto 0);
-signal tdc_desl16_int : std_logic_vector(31 downto 0);
-signal tdc_desh17_int : std_logic_vector(31 downto 0);
-signal tdc_desl17_int : std_logic_vector(31 downto 0);
-signal tdc_desh18_int : std_logic_vector(31 downto 0);
-signal tdc_desl18_int : std_logic_vector(31 downto 0);
-signal tdc_desh19_int : std_logic_vector(31 downto 0);
-signal tdc_desl19_int : std_logic_vector(31 downto 0);
-signal tdc_desh20_int : std_logic_vector(31 downto 0);
-signal tdc_desl20_int : std_logic_vector(31 downto 0);
-signal tdc_desh21_int : std_logic_vector(31 downto 0);
-signal tdc_desl21_int : std_logic_vector(31 downto 0);
-signal tdc_desh22_int : std_logic_vector(31 downto 0);
-signal tdc_desl22_int : std_logic_vector(31 downto 0);
-signal tdc_desh23_int : std_logic_vector(31 downto 0);
-signal tdc_desl23_int : std_logic_vector(31 downto 0);
-signal tdc_desh24_int : std_logic_vector(31 downto 0);
-signal tdc_desl24_int : std_logic_vector(31 downto 0);
-signal tdc_desh25_int : std_logic_vector(31 downto 0);
-signal tdc_desl25_int : std_logic_vector(31 downto 0);
-signal tdc_desh26_int : std_logic_vector(31 downto 0);
-signal tdc_desl26_int : std_logic_vector(31 downto 0);
-signal tdc_desh27_int : std_logic_vector(31 downto 0);
-signal tdc_desl27_int : std_logic_vector(31 downto 0);
-signal tdc_desh28_int : std_logic_vector(31 downto 0);
-signal tdc_desl28_int : std_logic_vector(31 downto 0);
-signal tdc_desh29_int : std_logic_vector(31 downto 0);
-signal tdc_desl29_int : std_logic_vector(31 downto 0);
signal tdc_dctl_req_int : std_logic ;
signal tdc_csel_next_dly0 : std_logic ;
signal tdc_csel_next_int : std_logic ;
@@ -467,21 +181,21 @@ signal tdc_luta_int : std_logic_vector(15 downto 0);
signal tdc_hisa_int : std_logic_vector(15 downto 0);
signal tdc_fcc_st_dly0 : std_logic ;
signal tdc_fcc_st_int : std_logic ;
-signal eic_idr_int : std_logic_vector(31 downto 0);
+signal eic_idr_int : std_logic_vector(9 downto 0);
signal eic_idr_write_int : std_logic ;
-signal eic_ier_int : std_logic_vector(31 downto 0);
+signal eic_ier_int : std_logic_vector(9 downto 0);
signal eic_ier_write_int : std_logic ;
-signal eic_imr_int : std_logic_vector(31 downto 0);
-signal eic_isr_clear_int : std_logic_vector(31 downto 0);
-signal eic_isr_status_int : std_logic_vector(31 downto 0);
-signal eic_irq_ack_int : std_logic_vector(31 downto 0);
+signal eic_imr_int : std_logic_vector(9 downto 0);
+signal eic_isr_clear_int : std_logic_vector(9 downto 0);
+signal eic_isr_status_int : std_logic_vector(9 downto 0);
+signal eic_irq_ack_int : std_logic_vector(9 downto 0);
signal eic_isr_write_int : std_logic ;
-signal irq_inputs_vector_int : std_logic_vector(31 downto 0);
+signal irq_inputs_vector_int : std_logic_vector(9 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
-signal rwaddr_reg : std_logic_vector(7 downto 0);
+signal rwaddr_reg : std_logic_vector(5 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
@@ -523,50 +237,6 @@ begin
tdc_desl6_int <= "00000000000000000000000000000000";
tdc_desh7_int <= "00000000000000000000000000000000";
tdc_desl7_int <= "00000000000000000000000000000000";
- tdc_desh8_int <= "00000000000000000000000000000000";
- tdc_desl8_int <= "00000000000000000000000000000000";
- tdc_desh9_int <= "00000000000000000000000000000000";
- tdc_desl9_int <= "00000000000000000000000000000000";
- tdc_desh10_int <= "00000000000000000000000000000000";
- tdc_desl10_int <= "00000000000000000000000000000000";
- tdc_desh11_int <= "00000000000000000000000000000000";
- tdc_desl11_int <= "00000000000000000000000000000000";
- tdc_desh12_int <= "00000000000000000000000000000000";
- tdc_desl12_int <= "00000000000000000000000000000000";
- tdc_desh13_int <= "00000000000000000000000000000000";
- tdc_desl13_int <= "00000000000000000000000000000000";
- tdc_desh14_int <= "00000000000000000000000000000000";
- tdc_desl14_int <= "00000000000000000000000000000000";
- tdc_desh15_int <= "00000000000000000000000000000000";
- tdc_desl15_int <= "00000000000000000000000000000000";
- tdc_desh16_int <= "00000000000000000000000000000000";
- tdc_desl16_int <= "00000000000000000000000000000000";
- tdc_desh17_int <= "00000000000000000000000000000000";
- tdc_desl17_int <= "00000000000000000000000000000000";
- tdc_desh18_int <= "00000000000000000000000000000000";
- tdc_desl18_int <= "00000000000000000000000000000000";
- tdc_desh19_int <= "00000000000000000000000000000000";
- tdc_desl19_int <= "00000000000000000000000000000000";
- tdc_desh20_int <= "00000000000000000000000000000000";
- tdc_desl20_int <= "00000000000000000000000000000000";
- tdc_desh21_int <= "00000000000000000000000000000000";
- tdc_desl21_int <= "00000000000000000000000000000000";
- tdc_desh22_int <= "00000000000000000000000000000000";
- tdc_desl22_int <= "00000000000000000000000000000000";
- tdc_desh23_int <= "00000000000000000000000000000000";
- tdc_desl23_int <= "00000000000000000000000000000000";
- tdc_desh24_int <= "00000000000000000000000000000000";
- tdc_desl24_int <= "00000000000000000000000000000000";
- tdc_desh25_int <= "00000000000000000000000000000000";
- tdc_desl25_int <= "00000000000000000000000000000000";
- tdc_desh26_int <= "00000000000000000000000000000000";
- tdc_desl26_int <= "00000000000000000000000000000000";
- tdc_desh27_int <= "00000000000000000000000000000000";
- tdc_desl27_int <= "00000000000000000000000000000000";
- tdc_desh28_int <= "00000000000000000000000000000000";
- tdc_desl28_int <= "00000000000000000000000000000000";
- tdc_desh29_int <= "00000000000000000000000000000000";
- tdc_desl29_int <= "00000000000000000000000000000000";
tdc_dctl_req_int <= '0';
tdc_csel_next_int <= '0';
tdc_cal_int <= '0';
@@ -593,8 +263,8 @@ begin
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
- case rwaddr_reg(7 downto 0) is
- when "00000000" =>
+ case rwaddr_reg(5 downto 0) is
+ when "000000" =>
if (wb_we_i = '1') then
tdc_cs_rst_int <= wrdata_reg(0);
else
@@ -632,7 +302,7 @@ begin
end if;
ack_sreg(2) <= '1';
ack_in_progress <= '1';
- when "00000001" =>
+ when "000001" =>
if (wb_we_i = '1') then
tdc_desh0_int <= wrdata_reg(31 downto 0);
else
@@ -640,7 +310,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "00000010" =>
+ when "000010" =>
if (wb_we_i = '1') then
tdc_desl0_int <= wrdata_reg(31 downto 0);
else
@@ -648,7 +318,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "00000011" =>
+ when "000011" =>
if (wb_we_i = '1') then
tdc_desh1_int <= wrdata_reg(31 downto 0);
else
@@ -656,7 +326,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "00000100" =>
+ when "000100" =>
if (wb_we_i = '1') then
tdc_desl1_int <= wrdata_reg(31 downto 0);
else
@@ -664,7 +334,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "00000101" =>
+ when "000101" =>
if (wb_we_i = '1') then
tdc_desh2_int <= wrdata_reg(31 downto 0);
else
@@ -672,7 +342,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "00000110" =>
+ when "000110" =>
if (wb_we_i = '1') then
tdc_desl2_int <= wrdata_reg(31 downto 0);
else
@@ -680,7 +350,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "00000111" =>
+ when "000111" =>
if (wb_we_i = '1') then
tdc_desh3_int <= wrdata_reg(31 downto 0);
else
@@ -688,7 +358,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "00001000" =>
+ when "001000" =>
if (wb_we_i = '1') then
tdc_desl3_int <= wrdata_reg(31 downto 0);
else
@@ -696,7 +366,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "00001001" =>
+ when "001001" =>
if (wb_we_i = '1') then
tdc_desh4_int <= wrdata_reg(31 downto 0);
else
@@ -704,7 +374,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "00001010" =>
+ when "001010" =>
if (wb_we_i = '1') then
tdc_desl4_int <= wrdata_reg(31 downto 0);
else
@@ -712,7 +382,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "00001011" =>
+ when "001011" =>
if (wb_we_i = '1') then
tdc_desh5_int <= wrdata_reg(31 downto 0);
else
@@ -720,7 +390,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "00001100" =>
+ when "001100" =>
if (wb_we_i = '1') then
tdc_desl5_int <= wrdata_reg(31 downto 0);
else
@@ -728,7 +398,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "00001101" =>
+ when "001101" =>
if (wb_we_i = '1') then
tdc_desh6_int <= wrdata_reg(31 downto 0);
else
@@ -736,7 +406,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "00001110" =>
+ when "001110" =>
if (wb_we_i = '1') then
tdc_desl6_int <= wrdata_reg(31 downto 0);
else
@@ -744,7 +414,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "00001111" =>
+ when "001111" =>
if (wb_we_i = '1') then
tdc_desh7_int <= wrdata_reg(31 downto 0);
else
@@ -752,7 +422,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "00010000" =>
+ when "010000" =>
if (wb_we_i = '1') then
tdc_desl7_int <= wrdata_reg(31 downto 0);
else
@@ -760,998 +430,206 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "00010001" =>
+ when "010001" =>
if (wb_we_i = '1') then
- tdc_desh8_int <= wrdata_reg(31 downto 0);
else
- rddata_reg(31 downto 0) <= tdc_desh8_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00010010" =>
- if (wb_we_i = '1') then
- tdc_desl8_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desl8_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00010011" =>
- if (wb_we_i = '1') then
- tdc_desh9_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desh9_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00010100" =>
- if (wb_we_i = '1') then
- tdc_desl9_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desl9_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00010101" =>
- if (wb_we_i = '1') then
- tdc_desh10_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desh10_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00010110" =>
- if (wb_we_i = '1') then
- tdc_desl10_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desl10_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00010111" =>
- if (wb_we_i = '1') then
- tdc_desh11_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desh11_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00011000" =>
- if (wb_we_i = '1') then
- tdc_desl11_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desl11_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00011001" =>
- if (wb_we_i = '1') then
- tdc_desh12_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desh12_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00011010" =>
- if (wb_we_i = '1') then
- tdc_desl12_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desl12_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00011011" =>
- if (wb_we_i = '1') then
- tdc_desh13_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desh13_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00011100" =>
- if (wb_we_i = '1') then
- tdc_desl13_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desl13_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00011101" =>
- if (wb_we_i = '1') then
- tdc_desh14_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desh14_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00011110" =>
- if (wb_we_i = '1') then
- tdc_desl14_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desl14_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00011111" =>
- if (wb_we_i = '1') then
- tdc_desh15_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desh15_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00100000" =>
- if (wb_we_i = '1') then
- tdc_desl15_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desl15_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00100001" =>
- if (wb_we_i = '1') then
- tdc_desh16_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desh16_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00100010" =>
- if (wb_we_i = '1') then
- tdc_desl16_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desl16_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00100011" =>
- if (wb_we_i = '1') then
- tdc_desh17_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desh17_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00100100" =>
- if (wb_we_i = '1') then
- tdc_desl17_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desl17_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00100101" =>
- if (wb_we_i = '1') then
- tdc_desh18_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desh18_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00100110" =>
- if (wb_we_i = '1') then
- tdc_desl18_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desl18_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00100111" =>
- if (wb_we_i = '1') then
- tdc_desh19_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desh19_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00101000" =>
- if (wb_we_i = '1') then
- tdc_desl19_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desl19_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00101001" =>
- if (wb_we_i = '1') then
- tdc_desh20_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desh20_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00101010" =>
- if (wb_we_i = '1') then
- tdc_desl20_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desl20_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00101011" =>
- if (wb_we_i = '1') then
- tdc_desh21_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desh21_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00101100" =>
- if (wb_we_i = '1') then
- tdc_desl21_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desl21_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00101101" =>
- if (wb_we_i = '1') then
- tdc_desh22_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desh22_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00101110" =>
- if (wb_we_i = '1') then
- tdc_desl22_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desl22_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00101111" =>
- if (wb_we_i = '1') then
- tdc_desh23_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desh23_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00110000" =>
- if (wb_we_i = '1') then
- tdc_desl23_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desl23_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00110001" =>
- if (wb_we_i = '1') then
- tdc_desh24_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desh24_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00110010" =>
- if (wb_we_i = '1') then
- tdc_desl24_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desl24_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00110011" =>
- if (wb_we_i = '1') then
- tdc_desh25_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desh25_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00110100" =>
- if (wb_we_i = '1') then
- tdc_desl25_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desl25_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00110101" =>
- if (wb_we_i = '1') then
- tdc_desh26_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desh26_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00110110" =>
- if (wb_we_i = '1') then
- tdc_desl26_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desl26_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00110111" =>
- if (wb_we_i = '1') then
- tdc_desh27_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desh27_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00111000" =>
- if (wb_we_i = '1') then
- tdc_desl27_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desl27_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00111001" =>
- if (wb_we_i = '1') then
- tdc_desh28_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desh28_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00111010" =>
- if (wb_we_i = '1') then
- tdc_desl28_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desl28_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00111011" =>
- if (wb_we_i = '1') then
- tdc_desh29_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desh29_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00111100" =>
- if (wb_we_i = '1') then
- tdc_desl29_int <= wrdata_reg(31 downto 0);
- else
- rddata_reg(31 downto 0) <= tdc_desl29_int;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00111101" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(29 downto 0) <= tdc_pol_i;
- rddata_reg(30) <= 'X';
- rddata_reg(31) <= 'X';
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00111110" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_raw0_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "00111111" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesh0_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01000000" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesl0_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01000001" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_raw1_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01000010" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesh1_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01000011" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesl1_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01000100" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_raw2_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01000101" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesh2_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01000110" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesl2_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01000111" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_raw3_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01001000" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesh3_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01001001" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesl3_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01001010" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_raw4_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01001011" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesh4_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01001100" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesl4_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01001101" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_raw5_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01001110" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesh5_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01001111" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesl5_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01010000" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_raw6_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01010001" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesh6_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01010010" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesl6_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01010011" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_raw7_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01010100" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesh7_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01010101" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesl7_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01010110" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_raw8_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01010111" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesh8_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01011000" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesl8_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01011001" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_raw9_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01011010" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesh9_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01011011" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesl9_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01011100" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_raw10_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01011101" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesh10_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01011110" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesl10_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01011111" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_raw11_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01100000" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesh11_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01100001" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesl11_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01100010" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_raw12_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01100011" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesh12_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01100100" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesl12_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01100101" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_raw13_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01100110" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesh13_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01100111" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesl13_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01101000" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_raw14_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01101001" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesh14_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01101010" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesl14_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01101011" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_raw15_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01101100" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesh15_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01101101" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesl15_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01101110" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_raw16_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01101111" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesh16_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01110000" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesl16_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01110001" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_raw17_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01110010" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesh17_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01110011" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesl17_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01110100" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_raw18_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01110101" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesh18_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01110110" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesl18_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01110111" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_raw19_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01111000" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesh19_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01111001" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesl19_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01111010" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_raw20_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01111011" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesh20_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01111100" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesl20_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01111101" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_raw21_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01111110" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesh21_i;
- end if;
- ack_sreg(0) <= '1';
- ack_in_progress <= '1';
- when "01111111" =>
- if (wb_we_i = '1') then
- else
- rddata_reg(31 downto 0) <= tdc_mesl21_i;
+ rddata_reg(7 downto 0) <= tdc_pol_i;
+ rddata_reg(8) <= 'X';
+ rddata_reg(9) <= 'X';
+ rddata_reg(10) <= 'X';
+ rddata_reg(11) <= 'X';
+ rddata_reg(12) <= 'X';
+ rddata_reg(13) <= 'X';
+ rddata_reg(14) <= 'X';
+ rddata_reg(15) <= 'X';
+ rddata_reg(16) <= 'X';
+ rddata_reg(17) <= 'X';
+ rddata_reg(18) <= 'X';
+ rddata_reg(19) <= 'X';
+ rddata_reg(20) <= 'X';
+ rddata_reg(21) <= 'X';
+ rddata_reg(22) <= 'X';
+ rddata_reg(23) <= 'X';
+ rddata_reg(24) <= 'X';
+ rddata_reg(25) <= 'X';
+ rddata_reg(26) <= 'X';
+ rddata_reg(27) <= 'X';
+ rddata_reg(28) <= 'X';
+ rddata_reg(29) <= 'X';
+ rddata_reg(30) <= 'X';
+ rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10000000" =>
+ when "010010" =>
if (wb_we_i = '1') then
else
- rddata_reg(31 downto 0) <= tdc_raw22_i;
+ rddata_reg(31 downto 0) <= tdc_raw0_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10000001" =>
+ when "010011" =>
if (wb_we_i = '1') then
else
- rddata_reg(31 downto 0) <= tdc_mesh22_i;
+ rddata_reg(31 downto 0) <= tdc_mesh0_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10000010" =>
+ when "010100" =>
if (wb_we_i = '1') then
else
- rddata_reg(31 downto 0) <= tdc_mesl22_i;
+ rddata_reg(31 downto 0) <= tdc_mesl0_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10000011" =>
+ when "010101" =>
if (wb_we_i = '1') then
else
- rddata_reg(31 downto 0) <= tdc_raw23_i;
+ rddata_reg(31 downto 0) <= tdc_raw1_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10000100" =>
+ when "010110" =>
if (wb_we_i = '1') then
else
- rddata_reg(31 downto 0) <= tdc_mesh23_i;
+ rddata_reg(31 downto 0) <= tdc_mesh1_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10000101" =>
+ when "010111" =>
if (wb_we_i = '1') then
else
- rddata_reg(31 downto 0) <= tdc_mesl23_i;
+ rddata_reg(31 downto 0) <= tdc_mesl1_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10000110" =>
+ when "011000" =>
if (wb_we_i = '1') then
else
- rddata_reg(31 downto 0) <= tdc_raw24_i;
+ rddata_reg(31 downto 0) <= tdc_raw2_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10000111" =>
+ when "011001" =>
if (wb_we_i = '1') then
else
- rddata_reg(31 downto 0) <= tdc_mesh24_i;
+ rddata_reg(31 downto 0) <= tdc_mesh2_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10001000" =>
+ when "011010" =>
if (wb_we_i = '1') then
else
- rddata_reg(31 downto 0) <= tdc_mesl24_i;
+ rddata_reg(31 downto 0) <= tdc_mesl2_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10001001" =>
+ when "011011" =>
if (wb_we_i = '1') then
else
- rddata_reg(31 downto 0) <= tdc_raw25_i;
+ rddata_reg(31 downto 0) <= tdc_raw3_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10001010" =>
+ when "011100" =>
if (wb_we_i = '1') then
else
- rddata_reg(31 downto 0) <= tdc_mesh25_i;
+ rddata_reg(31 downto 0) <= tdc_mesh3_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10001011" =>
+ when "011101" =>
if (wb_we_i = '1') then
else
- rddata_reg(31 downto 0) <= tdc_mesl25_i;
+ rddata_reg(31 downto 0) <= tdc_mesl3_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10001100" =>
+ when "011110" =>
if (wb_we_i = '1') then
else
- rddata_reg(31 downto 0) <= tdc_raw26_i;
+ rddata_reg(31 downto 0) <= tdc_raw4_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10001101" =>
+ when "011111" =>
if (wb_we_i = '1') then
else
- rddata_reg(31 downto 0) <= tdc_mesh26_i;
+ rddata_reg(31 downto 0) <= tdc_mesh4_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10001110" =>
+ when "100000" =>
if (wb_we_i = '1') then
else
- rddata_reg(31 downto 0) <= tdc_mesl26_i;
+ rddata_reg(31 downto 0) <= tdc_mesl4_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10001111" =>
+ when "100001" =>
if (wb_we_i = '1') then
else
- rddata_reg(31 downto 0) <= tdc_raw27_i;
+ rddata_reg(31 downto 0) <= tdc_raw5_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10010000" =>
+ when "100010" =>
if (wb_we_i = '1') then
else
- rddata_reg(31 downto 0) <= tdc_mesh27_i;
+ rddata_reg(31 downto 0) <= tdc_mesh5_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10010001" =>
+ when "100011" =>
if (wb_we_i = '1') then
else
- rddata_reg(31 downto 0) <= tdc_mesl27_i;
+ rddata_reg(31 downto 0) <= tdc_mesl5_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10010010" =>
+ when "100100" =>
if (wb_we_i = '1') then
else
- rddata_reg(31 downto 0) <= tdc_raw28_i;
+ rddata_reg(31 downto 0) <= tdc_raw6_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10010011" =>
+ when "100101" =>
if (wb_we_i = '1') then
else
- rddata_reg(31 downto 0) <= tdc_mesh28_i;
+ rddata_reg(31 downto 0) <= tdc_mesh6_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10010100" =>
+ when "100110" =>
if (wb_we_i = '1') then
else
- rddata_reg(31 downto 0) <= tdc_mesl28_i;
+ rddata_reg(31 downto 0) <= tdc_mesl6_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10010101" =>
+ when "100111" =>
if (wb_we_i = '1') then
else
- rddata_reg(31 downto 0) <= tdc_raw29_i;
+ rddata_reg(31 downto 0) <= tdc_raw7_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10010110" =>
+ when "101000" =>
if (wb_we_i = '1') then
else
- rddata_reg(31 downto 0) <= tdc_mesh29_i;
+ rddata_reg(31 downto 0) <= tdc_mesh7_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10010111" =>
+ when "101001" =>
if (wb_we_i = '1') then
else
- rddata_reg(31 downto 0) <= tdc_mesl29_i;
+ rddata_reg(31 downto 0) <= tdc_mesl7_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10011000" =>
+ when "101010" =>
if (wb_we_i = '1') then
tdc_dctl_req_int <= wrdata_reg(0);
else
@@ -1790,7 +668,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10011001" =>
+ when "101011" =>
if (wb_we_i = '1') then
tdc_csel_next_int <= wrdata_reg(0);
else
@@ -1828,7 +706,7 @@ begin
end if;
ack_sreg(2) <= '1';
ack_in_progress <= '1';
- when "10011010" =>
+ when "101100" =>
if (wb_we_i = '1') then
tdc_cal_int <= wrdata_reg(0);
else
@@ -1867,7 +745,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10011011" =>
+ when "101101" =>
if (wb_we_i = '1') then
tdc_luta_int <= wrdata_reg(15 downto 0);
else
@@ -1891,14 +769,14 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10011100" =>
+ when "101110" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= tdc_lutd_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10011101" =>
+ when "101111" =>
if (wb_we_i = '1') then
tdc_hisa_int <= wrdata_reg(15 downto 0);
else
@@ -1922,14 +800,14 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10011110" =>
+ when "110000" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= tdc_hisd_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10011111" =>
+ when "110001" =>
if (wb_we_i = '1') then
tdc_fcc_st_int <= wrdata_reg(0);
else
@@ -1967,21 +845,21 @@ begin
end if;
ack_sreg(2) <= '1';
ack_in_progress <= '1';
- when "10100000" =>
+ when "110010" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= tdc_fcr_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10100001" =>
+ when "110011" =>
if (wb_we_i = '1') then
else
rddata_reg(31 downto 0) <= tdc_fcsr_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10101000" =>
+ when "111000" =>
if (wb_we_i = '1') then
eic_idr_write_int <= '1';
else
@@ -2020,7 +898,7 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10101001" =>
+ when "111001" =>
if (wb_we_i = '1') then
eic_ier_write_int <= '1';
else
@@ -2059,18 +937,62 @@ begin
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10101010" =>
+ when "111010" =>
if (wb_we_i = '1') then
else
- rddata_reg(31 downto 0) <= eic_imr_int(31 downto 0);
+ rddata_reg(9 downto 0) <= eic_imr_int(9 downto 0);
+ rddata_reg(10) <= 'X';
+ rddata_reg(11) <= 'X';
+ rddata_reg(12) <= 'X';
+ rddata_reg(13) <= 'X';
+ rddata_reg(14) <= 'X';
+ rddata_reg(15) <= 'X';
+ rddata_reg(16) <= 'X';
+ rddata_reg(17) <= 'X';
+ rddata_reg(18) <= 'X';
+ rddata_reg(19) <= 'X';
+ rddata_reg(20) <= 'X';
+ rddata_reg(21) <= 'X';
+ rddata_reg(22) <= 'X';
+ rddata_reg(23) <= 'X';
+ rddata_reg(24) <= 'X';
+ rddata_reg(25) <= 'X';
+ rddata_reg(26) <= 'X';
+ rddata_reg(27) <= 'X';
+ rddata_reg(28) <= 'X';
+ rddata_reg(29) <= 'X';
+ rddata_reg(30) <= 'X';
+ rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
- when "10101011" =>
+ when "111011" =>
if (wb_we_i = '1') then
eic_isr_write_int <= '1';
else
- rddata_reg(31 downto 0) <= eic_isr_status_int(31 downto 0);
+ rddata_reg(9 downto 0) <= eic_isr_status_int(9 downto 0);
+ rddata_reg(10) <= 'X';
+ rddata_reg(11) <= 'X';
+ rddata_reg(12) <= 'X';
+ rddata_reg(13) <= 'X';
+ rddata_reg(14) <= 'X';
+ rddata_reg(15) <= 'X';
+ rddata_reg(16) <= 'X';
+ rddata_reg(17) <= 'X';
+ rddata_reg(18) <= 'X';
+ rddata_reg(19) <= 'X';
+ rddata_reg(20) <= 'X';
+ rddata_reg(21) <= 'X';
+ rddata_reg(22) <= 'X';
+ rddata_reg(23) <= 'X';
+ rddata_reg(24) <= 'X';
+ rddata_reg(25) <= 'X';
+ rddata_reg(26) <= 'X';
+ rddata_reg(27) <= 'X';
+ rddata_reg(28) <= 'X';
+ rddata_reg(29) <= 'X';
+ rddata_reg(30) <= 'X';
+ rddata_reg(31) <= 'X';
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
@@ -2133,161 +1055,7 @@ begin
tdc_desh7_o <= tdc_desh7_int;
-- Low word value
tdc_desl7_o <= tdc_desl7_int;
--- High word value
- tdc_desh8_o <= tdc_desh8_int;
--- Low word value
- tdc_desl8_o <= tdc_desl8_int;
--- High word value
- tdc_desh9_o <= tdc_desh9_int;
--- Low word value
- tdc_desl9_o <= tdc_desl9_int;
--- High word value
- tdc_desh10_o <= tdc_desh10_int;
--- Low word value
- tdc_desl10_o <= tdc_desl10_int;
--- High word value
- tdc_desh11_o <= tdc_desh11_int;
--- Low word value
- tdc_desl11_o <= tdc_desl11_int;
--- High word value
- tdc_desh12_o <= tdc_desh12_int;
--- Low word value
- tdc_desl12_o <= tdc_desl12_int;
--- High word value
- tdc_desh13_o <= tdc_desh13_int;
--- Low word value
- tdc_desl13_o <= tdc_desl13_int;
--- High word value
- tdc_desh14_o <= tdc_desh14_int;
--- Low word value
- tdc_desl14_o <= tdc_desl14_int;
--- High word value
- tdc_desh15_o <= tdc_desh15_int;
--- Low word value
- tdc_desl15_o <= tdc_desl15_int;
--- High word value
- tdc_desh16_o <= tdc_desh16_int;
--- Low word value
- tdc_desl16_o <= tdc_desl16_int;
--- High word value
- tdc_desh17_o <= tdc_desh17_int;
--- Low word value
- tdc_desl17_o <= tdc_desl17_int;
--- High word value
- tdc_desh18_o <= tdc_desh18_int;
--- Low word value
- tdc_desl18_o <= tdc_desl18_int;
--- High word value
- tdc_desh19_o <= tdc_desh19_int;
--- Low word value
- tdc_desl19_o <= tdc_desl19_int;
--- High word value
- tdc_desh20_o <= tdc_desh20_int;
--- Low word value
- tdc_desl20_o <= tdc_desl20_int;
--- High word value
- tdc_desh21_o <= tdc_desh21_int;
--- Low word value
- tdc_desl21_o <= tdc_desl21_int;
--- High word value
- tdc_desh22_o <= tdc_desh22_int;
--- Low word value
- tdc_desl22_o <= tdc_desl22_int;
--- High word value
- tdc_desh23_o <= tdc_desh23_int;
--- Low word value
- tdc_desl23_o <= tdc_desl23_int;
--- High word value
- tdc_desh24_o <= tdc_desh24_int;
--- Low word value
- tdc_desl24_o <= tdc_desl24_int;
--- High word value
- tdc_desh25_o <= tdc_desh25_int;
--- Low word value
- tdc_desl25_o <= tdc_desl25_int;
--- High word value
- tdc_desh26_o <= tdc_desh26_int;
--- Low word value
- tdc_desl26_o <= tdc_desl26_int;
--- High word value
- tdc_desh27_o <= tdc_desh27_int;
--- Low word value
- tdc_desl27_o <= tdc_desl27_int;
--- High word value
- tdc_desh28_o <= tdc_desh28_int;
--- Low word value
- tdc_desl28_o <= tdc_desl28_int;
--- High word value
- tdc_desh29_o <= tdc_desh29_int;
--- Low word value
- tdc_desl29_o <= tdc_desl29_int;
--- Value
--- Value
--- High word value
--- Low word value
--- Value
--- High word value
--- Low word value
--- Value
--- High word value
--- Low word value
--- Value
--- High word value
--- Low word value
--- Value
--- High word value
--- Low word value
--- Value
--- High word value
--- Low word value
--- Value
--- High word value
--- Low word value
--- Value
--- High word value
--- Low word value
--- Value
--- High word value
--- Low word value
--- Value
--- High word value
--- Low word value
--- Value
--- High word value
--- Low word value
-- Value
--- High word value
--- Low word value
--- Value
--- High word value
--- Low word value
--- Value
--- High word value
--- Low word value
--- Value
--- High word value
--- Low word value
--- Value
--- High word value
--- Low word value
--- Value
--- High word value
--- Low word value
--- Value
--- High word value
--- Low word value
--- Value
--- High word value
--- Low word value
--- Value
--- High word value
--- Low word value
--- Value
--- High word value
--- Low word value
--- Value
--- High word value
--- Low word value
-- Value
-- High word value
-- Low word value
@@ -2354,15 +1122,15 @@ begin
-- Result
-- Result
-- extra code for reg/fifo/mem: Interrupt disable register
- eic_idr_int(31 downto 0) <= wrdata_reg(31 downto 0);
+ eic_idr_int(9 downto 0) <= wrdata_reg(9 downto 0);
-- extra code for reg/fifo/mem: Interrupt enable register
- eic_ier_int(31 downto 0) <= wrdata_reg(31 downto 0);
+ eic_ier_int(9 downto 0) <= wrdata_reg(9 downto 0);
-- extra code for reg/fifo/mem: Interrupt status register
- eic_isr_clear_int(31 downto 0) <= wrdata_reg(31 downto 0);
+ eic_isr_clear_int(9 downto 0) <= wrdata_reg(9 downto 0);
-- extra code for reg/fifo/mem: IRQ_CONTROLLER
eic_irq_controller_inst : wbgen2_eic
generic map (
- g_num_interrupts => 32,
+ g_num_interrupts => 10,
g_irq00_mode => 0,
g_irq01_mode => 0,
g_irq02_mode => 0,
@@ -2420,30 +1188,8 @@ begin
irq_inputs_vector_int(5) <= irq_ie5_i;
irq_inputs_vector_int(6) <= irq_ie6_i;
irq_inputs_vector_int(7) <= irq_ie7_i;
- irq_inputs_vector_int(8) <= irq_ie8_i;
- irq_inputs_vector_int(9) <= irq_ie9_i;
- irq_inputs_vector_int(10) <= irq_ie10_i;
- irq_inputs_vector_int(11) <= irq_ie11_i;
- irq_inputs_vector_int(12) <= irq_ie12_i;
- irq_inputs_vector_int(13) <= irq_ie13_i;
- irq_inputs_vector_int(14) <= irq_ie14_i;
- irq_inputs_vector_int(15) <= irq_ie15_i;
- irq_inputs_vector_int(16) <= irq_ie16_i;
- irq_inputs_vector_int(17) <= irq_ie17_i;
- irq_inputs_vector_int(18) <= irq_ie18_i;
- irq_inputs_vector_int(19) <= irq_ie19_i;
- irq_inputs_vector_int(20) <= irq_ie20_i;
- irq_inputs_vector_int(21) <= irq_ie21_i;
- irq_inputs_vector_int(22) <= irq_ie22_i;
- irq_inputs_vector_int(23) <= irq_ie23_i;
- irq_inputs_vector_int(24) <= irq_ie24_i;
- irq_inputs_vector_int(25) <= irq_ie25_i;
- irq_inputs_vector_int(26) <= irq_ie26_i;
- irq_inputs_vector_int(27) <= irq_ie27_i;
- irq_inputs_vector_int(28) <= irq_ie28_i;
- irq_inputs_vector_int(29) <= irq_ie29_i;
- irq_inputs_vector_int(30) <= irq_isc_i;
- irq_inputs_vector_int(31) <= irq_icc_i;
+ irq_inputs_vector_int(8) <= irq_isc_i;
+ irq_inputs_vector_int(9) <= irq_icc_i;
rwaddr_reg <= wb_addr_i;
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
--
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