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Commit cb51a9d7 authored by Dusan Slavinec's avatar Dusan Slavinec
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kernel module for testing PMC prototype V1

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src/hdl/dpram/aria_dpram.cmp deleted 100644 → 0
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--Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
component aria_dpram
PORT
(
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock_a : IN STD_LOGIC := '1';
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (39 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (39 DOWNTO 0);
rden_a : IN STD_LOGIC := '1';
rden_b : IN STD_LOGIC := '1';
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (39 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (39 DOWNTO 0)
);
end component;
src/hdl/dpram/aria_dpram.inc deleted 100644 → 0
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--Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
FUNCTION aria_dpram
(
address_a[7..0],
address_b[7..0],
clock_a,
clock_b,
data_a[39..0],
data_b[39..0],
rden_a,
rden_b,
wren_a,
wren_b
)
RETURNS (
q_a[39..0],
q_b[39..0]
);
src/hdl/dpram/aria_dpram.qip deleted 100644 → 0
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set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "aria_dpram.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "aria_dpram_inst.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "aria_dpram_bb.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "aria_dpram.inc"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "aria_dpram.cmp"]
src/hdl/dpram/aria_dpram.v deleted 100644 → 0
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src/hdl/dpram/aria_dpram_bb.v deleted 100644 → 0
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// megafunction wizard: %RAM: 2-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: aria_dpram.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module aria_dpram (
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
rden_a,
rden_b,
wren_a,
wren_b,
q_a,
q_b);
input [7:0] address_a;
input [7:0] address_b;
input clock_a;
input clock_b;
input [39:0] data_a;
input [39:0] data_b;
input rden_a;
input rden_b;
input wren_a;
input wren_b;
output [39:0] q_a;
output [39:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock_a;
tri1 rden_a;
tri1 rden_b;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "5"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "10240"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "40"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "40"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "40"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "40"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria V"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "40"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "40"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: USED_PORT: address_a 0 0 8 0 INPUT NODEFVAL "address_a[7..0]"
// Retrieval info: USED_PORT: address_b 0 0 8 0 INPUT NODEFVAL "address_b[7..0]"
// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
// Retrieval info: USED_PORT: data_a 0 0 40 0 INPUT NODEFVAL "data_a[39..0]"
// Retrieval info: USED_PORT: data_b 0 0 40 0 INPUT NODEFVAL "data_b[39..0]"
// Retrieval info: USED_PORT: q_a 0 0 40 0 OUTPUT NODEFVAL "q_a[39..0]"
// Retrieval info: USED_PORT: q_b 0 0 40 0 OUTPUT NODEFVAL "q_b[39..0]"
// Retrieval info: USED_PORT: rden_a 0 0 0 0 INPUT VCC "rden_a"
// Retrieval info: USED_PORT: rden_b 0 0 0 0 INPUT VCC "rden_b"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
// Retrieval info: CONNECT: @address_a 0 0 8 0 address_a 0 0 8 0
// Retrieval info: CONNECT: @address_b 0 0 8 0 address_b 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 40 0 data_a 0 0 40 0
// Retrieval info: CONNECT: @data_b 0 0 40 0 data_b 0 0 40 0
// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden_a 0 0 0 0
// Retrieval info: CONNECT: @rden_b 0 0 0 0 rden_b 0 0 0 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 40 0 @q_a 0 0 40 0
// Retrieval info: CONNECT: q_b 0 0 40 0 @q_b 0 0 40 0
// Retrieval info: GEN_FILE: TYPE_NORMAL aria_dpram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL aria_dpram.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL aria_dpram.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL aria_dpram.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL aria_dpram_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL aria_dpram_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
src/hdl/dpram/aria_dpram_inst.v deleted 100644 → 0
View file @ a7e44180
aria_dpram aria_dpram_inst (
.address_a ( address_a_sig ),
.address_b ( address_b_sig ),
.clock_a ( clock_a_sig ),
.clock_b ( clock_b_sig ),
.data_a ( data_a_sig ),
.data_b ( data_b_sig ),
.rden_a ( rden_a_sig ),
.rden_b ( rden_b_sig ),
.wren_a ( wren_a_sig ),
.wren_b ( wren_b_sig ),
.q_a ( q_a_sig ),
.q_b ( q_b_sig )
);
src/hdl/dpram/greybox_tmp/cbx_args.txt deleted 100644 → 0
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ADDRESS_REG_B=CLOCK1
CLOCK_ENABLE_INPUT_A=BYPASS
CLOCK_ENABLE_INPUT_B=BYPASS
CLOCK_ENABLE_OUTPUT_A=BYPASS
CLOCK_ENABLE_OUTPUT_B=BYPASS
INDATA_REG_B=CLOCK1
INTENDED_DEVICE_FAMILY="Arria V"
LPM_TYPE=altsyncram
NUMWORDS_A=256
NUMWORDS_B=256
OPERATION_MODE=BIDIR_DUAL_PORT
OUTDATA_ACLR_A=NONE
OUTDATA_ACLR_B=NONE
OUTDATA_REG_A=CLOCK0
OUTDATA_REG_B=CLOCK1
POWER_UP_UNINITIALIZED=FALSE
READ_DURING_WRITE_MODE_PORT_A=NEW_DATA_NO_NBE_READ
READ_DURING_WRITE_MODE_PORT_B=NEW_DATA_NO_NBE_READ
WIDTHAD_A=8
WIDTHAD_B=8
WIDTH_A=40
WIDTH_B=40
WIDTH_BYTEENA_A=1
WIDTH_BYTEENA_B=1
WRCONTROL_WRADDRESS_REG_B=CLOCK1
DEVICE_FAMILY="Arria V"
address_a
address_b
clock0
clock1
data_a
data_b
rden_a
rden_b
wren_a
wren_b
q_a
q_b
src/pmc-wb/95-pmc-wb.rules 0 → 100755
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SUBSYSTEM=="wbm", GROUP="wishbone", MODE="0660"
SUBSYSTEM=="wbs", GROUP="wishbone", MODE="0660"
SUBSYSTEM=="tty", SUBSYSTEMS=="usb-serial", DRIVERS=="wishbone_serial", GROUP="wishbone", MODE="0660"
src/pmc-wb/Makefile 0 → 100755
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ifneq ($(KERNELRELEASE),)
# When Makefile is invoked from kernel build system, define objects
ccflags-y += -DGIT_REVISION="$(shell git --git-dir=$(src)/../.git log -n1 --pretty='format:%h (%ci)')"
obj-m += pmc_wb.o wishbone.o
else
# When the Makefile is run directly, invoke the kernel build system
KERNELVER ?= `uname -r`
KERNELDIR ?= /lib/modules/$(KERNELVER)/build
PWD := $(shell pwd)
all:
$(MAKE) -C $(KERNELDIR) M=$(PWD)
install:
$(MAKE) -C $(KERNELDIR) M=$(PWD) INSTALL_MOD_PATH=$(STAGING) modules_install
mkdir -p $(STAGING)/etc/udev/rules.d
cp 95-pmc-wb.rules $(STAGING)/etc/udev/rules.d
[ $$(id -u) -ne 0 ] || depmod -a
[ $$(id -u) -ne 0 ] || groupadd wishbone || true
clean:
$(MAKE) -C $(KERNELDIR) M=$(PWD) clean
endif
src/pmc-wb/pmc_wb.c 0 → 100755
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src/pmc-wb/pmc_wb.h 0 → 100755
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#ifndef PMC_WB_DRIVER_H
#define PMC_WB_DRIVER_H
#include "wishbone.h"
#define PMC_WB "pmc_wb"
#define PMC_WB_VERSION "0.1"
#define PMC_WB_VENDOR_ID 0x10dc
#define PMC_WB_DEVICE_ID 0xc570
#define CONTROL_REGISTER_HIGH 0
#define CONTROL_REGISTER_LOW 4
#define ERROR_FLAG_HIGH 8
#define ERROR_FLAG_LOW 12
#define WINDOW_OFFSET_HIGH 16
#define WINDOW_OFFSET_LOW 20
#define SDWB_ADDRESS_HIGH 24
#define SDWB_ADDRESS_LOW 28
#define MASTER_CTL_HIGH 64
#define MASTER_CTL_LOW 68
#define MASTER_ADR_HIGH 72
#define MASTER_ADR_LOW 76
#define MASTER_DAT_HIGH 80
#define MASTER_DAT_LOW 84
#define WINDOW_HIGH 0xFFFF0000UL
#define WINDOW_LOW 0x0000FFFCUL
/* PCI core control and status registers in BAR0 */
#define PCI_CONF_IRQ 0x3C
#define WB_CONF_INT_ACK_REG 0x1E8 /* PCI core WB interrupt Acknowledge register */
#define WB_CONF_ICR_REG 0x1EC /* PCI core WB interrupt Control register */
#define WB_CONF_ISR_REG 0x1F0 /* PCI core WB interrupt Status register */
/* One per BAR */
struct pmc_wb_resource {
unsigned long start; /* start addr of BAR */
unsigned long end; /* end addr of BAR */
unsigned long size; /* size of BAR */
void *addr; /* remapped addr */
};
/* One per physical card */
struct pmc_wb_dev {
struct pci_dev* pci_dev;
struct pmc_wb_resource pci_res[3];
int msi;
struct wishbone wb;
struct mutex mutex; /* only one user can open a cycle at a time */
unsigned int window_offset;
unsigned int low_addr, width, shift;
};
#endif
src/pmc-wb/wishbone.c 0 → 100755
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src/pmc-wb/wishbone.h 0 → 100755
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#ifndef WISHBONE_H
#define WISHBONE_H
#include <linux/types.h>
#include <linux/list.h>
#include <linux/cdev.h>
#define WISHBONE_VERSION "0.1"
#define WISHONE_MAX_DEVICES 32 /* default only */
#define ETHERBONE_BCA 0x80
#define ETHERBONE_RCA 0x40
#define ETHERBONE_RFF 0x20
#define ETHERBONE_CYC 0x08
#define ETHERBONE_WCA 0x04
#define ETHERBONE_WFF 0x02
#define WBA_DATA 0x8000
#define WBA_ERR 0x8004
/* Implementation assumes these have the same size: */
typedef unsigned int wb_addr_t;
typedef unsigned int wb_data_t;
struct wishbone;
struct etherbone_master_context;
struct etherbone_slave_context;
struct wishbone_request
{
int write; /* 1=write, 0=read */
wb_addr_t addr;
wb_data_t data;
unsigned char mask; /* byte-enable for write */
};
struct wishbone_operations
{
/* owning module */
struct module *owner;
/* master operations */
void (*cycle)(struct wishbone *wb, int on);
void (*byteenable)(struct wishbone *wb, unsigned char mask);
void (*write)(struct wishbone *wb, wb_addr_t addr, wb_data_t);
wb_data_t (*read)(struct wishbone *wb, wb_addr_t addr);
wb_data_t (*read_cfg)(struct wishbone *wb, wb_addr_t addr);
/* slave operations */
int (*request)(struct wishbone *wb, struct wishbone_request*); /* 1=record filled, 0=none pending. re-enable non-MSI interrupts. */
void (*reply)(struct wishbone *wb, int err, wb_data_t dat);
};
/* One per wishbone backend hardware */
struct wishbone
{
const struct wishbone_operations* wops;
struct device *parent;
/* internal (guarded by global mutex--register/unregister): */
struct list_head list;
dev_t master_dev, slave_dev;
struct cdev master_cdev, slave_cdev;
struct device *master_device, *slave_device;
/* wake-q for blocking slave io */
wait_queue_head_t waitq;
struct fasync_struct *fasync;
struct mutex mutex; /* guards slave below */
struct etherbone_slave_context *slave;
};
#define RING_SIZE 8192
#define RING_INDEX(x) ((x) & (RING_SIZE-1))
#define RING_POS(x) ((x) & (RING_SIZE*2-1))
/* One per open of character device */
struct etherbone_master_context
{
struct wishbone* wishbone;
struct fasync_struct *fasync;
struct mutex mutex;
wait_queue_head_t waitq;
enum { header, idle, cycle } state;
unsigned int sent, processed, received; /* sent <= processed <= received */
unsigned char buf[RING_SIZE]; /* Ring buffer */
};
struct etherbone_slave_context
{
struct wishbone* wishbone;
struct mutex mutex;
unsigned int pending_err; /* unanswered operations */
int negotiated;
wb_data_t data;
unsigned int rbuf_done; /* data remaining to be read: [rbuf_done, rbuf_end) */
unsigned int rbuf_end;
unsigned char rbuf[sizeof(wb_data_t)*6];
unsigned int wbuf_fill; /* data remaining to be processed: [0, wbuf_full) */
unsigned char wbuf[sizeof(wb_data_t)*(255*2+3)];
};
#define RING_READ_LEN(ctx) RING_POS((ctx)->processed - (ctx)->sent)
#define RING_PROC_LEN(ctx) RING_POS((ctx)->received - (ctx)->processed)
#define RING_WRITE_LEN(ctx) RING_POS((ctx)->sent + RING_SIZE - (ctx)->received)
#define RING_POINTER(ctx, idx) (&(ctx)->buf[RING_INDEX((ctx)->idx)])
int wishbone_register(struct wishbone* wb);
int wishbone_unregister(struct wishbone* wb);
/* call when device has data pending. disable non-MSI interrupt generation before calling. */
void wishbone_slave_ready(struct wishbone* wb);
#endif
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