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mock-turtle
Commit 84040ec9 authored by Tristan Gingold's avatar Tristan Gingold Committed by Dimitris Lampridis
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endpoint: remove unused tlv code.

parent 681cd126
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Showing with 6 additions and 91 deletions
hdl/rtl/endpoint/mt_endpoint_pkg.vhd
View file @ 84040ec9
......@@ -47,21 +47,12 @@ package mt_endpoint_pkg is
dst_ip : std_logic_vector(31 downto 0);
dst_port : std_logic_vector(15 downto 0);
ethertype : std_logic_vector(15 downto 0);
type0 : std_logic_vector(31 downto 0);
type1 : std_logic_vector(31 downto 0);
type2 : std_logic_vector(31 downto 0);
type3 : std_logic_vector(31 downto 0);
store_header : std_logic;
is_tlv : std_logic;
filter_dst_mac : std_logic;
filter_dst_ip : std_logic;
filter_dst_port : std_logic;
filter_ethertype : std_logic;
filter_udp : std_logic;
filter_type0 : std_logic;
filter_type1 : std_logic;
filter_type2 : std_logic;
filter_type3 : std_logic;
filter_raw : std_logic;
enable : std_logic; -- discard all packets if 0
end record;
......@@ -69,7 +60,6 @@ package mt_endpoint_pkg is
type t_rmq_ep_rx_header is record
is_udp : std_logic;
is_raw : std_logic;
is_tlv : std_logic;
src_mac : std_logic_vector(47 downto 0);
dst_mac : std_logic_vector(47 downto 0);
ethertype : std_logic_vector(15 downto 0);
......@@ -78,8 +68,6 @@ package mt_endpoint_pkg is
src_ip : std_logic_vector(31 downto 0);
dst_ip : std_logic_vector(31 downto 0);
udp_length : std_logic_vector(15 downto 0);
tlv_type : std_logic_vector(31 downto 0);
tlv_size : std_logic_vector(15 downto 0);
end record;
type t_rmq_ep_tx_slot_config_array is
......
hdl/rtl/endpoint/mt_rmq_endpoint_rx.vhd
View file @ 84040ec9
......@@ -58,15 +58,10 @@ architecture arch of mt_rmq_endpoint_rx is
constant c_addr_ethertype : integer := 3;
constant c_addr_dst_ip : integer := 4;
constant c_addr_dst_port : integer := 5;
constant c_addr_dst_type0 : integer := 6;
constant c_addr_dst_type1 : integer := 7;
constant c_addr_dst_type2 : integer := 8;
constant c_addr_dst_type3 : integer := 9;
signal config : t_rmq_ep_rx_config;
signal match_dst_mac, match_dst_ip, match_udp, match_ethertype : std_logic;
signal match_type0, match_type1, match_type2, match_type3 : std_logic;
signal match_dst_port, match_raw, match : std_logic;
signal drop : std_logic;
......@@ -84,16 +79,11 @@ begin -- arch
case to_integer(unsigned(snk_config_i.adr(9 downto 2))) is
when c_addr_config =>
config.filter_udp <= snk_config_i.dat(0);
-- config.filter_tlv <= snk_config_i.dat(1);
config.filter_raw <= snk_config_i.dat(2);
config.filter_dst_mac <= snk_config_i.dat(3);
config.filter_ethertype <= snk_config_i.dat(4);
config.filter_dst_port <= snk_config_i.dat(5);
config.filter_dst_ip <= snk_config_i.dat(6);
config.filter_type0 <= snk_config_i.dat(7);
config.filter_type1 <= snk_config_i.dat(8);
config.filter_type2 <= snk_config_i.dat(9);
config.filter_type3 <= snk_config_i.dat(10);
config.store_header <= snk_config_i.dat(11);
config.enable <= snk_config_i.dat(31);
when c_addr_dst_mac_hi =>
......@@ -106,14 +96,6 @@ begin -- arch
config.dst_port <= snk_config_i.dat(15 downto 0);
when c_addr_ethertype =>
config.ethertype <= snk_config_i.dat(15 downto 0);
when c_addr_dst_type0 =>
config.type0 <= snk_config_i.dat(31 downto 0);
when c_addr_dst_type1 =>
config.type1 <= snk_config_i.dat(31 downto 0);
when c_addr_dst_type2 =>
config.type2 <= snk_config_i.dat(31 downto 0);
when c_addr_dst_type3 =>
config.type3 <= snk_config_i.dat(31 downto 0);
when others => null;
end case;
end if;
......@@ -133,10 +115,6 @@ begin -- arch
snk_config_o.dat(4) <= config.filter_ethertype;
snk_config_o.dat(5) <= config.filter_dst_port;
snk_config_o.dat(6) <= config.filter_dst_ip;
snk_config_o.dat(7) <= config.filter_type0;
snk_config_o.dat(8) <= config.filter_type1;
snk_config_o.dat(9) <= config.filter_type2;
snk_config_o.dat(10) <= config.filter_type3;
snk_config_o.dat(11) <= config.store_header;
snk_config_o.dat(30 downto 12) <= (others => '0');
snk_config_o.dat(31) <= config.enable;
......@@ -153,14 +131,6 @@ begin -- arch
when c_addr_ethertype =>
snk_config_o.dat(15 downto 0) <= config.ethertype;
snk_config_o.dat(31 downto 16) <= (others => '0');
when c_addr_dst_type0 =>
snk_config_o.dat <= config.type0;
when c_addr_dst_type1 =>
snk_config_o.dat <= config.type1;
when c_addr_dst_type2 =>
snk_config_o.dat <= config.type2;
when c_addr_dst_type3 =>
snk_config_o.dat <= config.type3;
when others => null;
end case;
end process p_read_config_regs;
......@@ -178,12 +148,6 @@ begin -- arch
match_udp <= '1';
match_raw <= '1';
match_type0 <= '1';
match_type1 <= '1';
match_type2 <= '1';
match_type3 <= '1';
if(config.filter_udp = '1') then
match_udp <= header_i.is_udp;
......@@ -203,35 +167,10 @@ begin -- arch
match_dst_ip <= '0';
end if;
end if;
--if (config.filter_type0 = '1') then
-- if (config.type0 /= header_i.tlv_type) then
-- match_type0 <= '0';
-- end if;
--end if;
--if (config.filter_type1 = '1') then
-- if (config.type1 /= header_i.tlv_type) then
-- match_type1 <= '0';
-- end if;
--end if;
--if (config.filter_type2 = '1') then
-- if (config.type2 /= header_i.tlv_type) then
-- match_type2 <= '0';
-- end if;
--end if;
--if (config.filter_type3 = '1') then
-- if (config.type3 /= header_i.tlv_type) then
-- match_type3 <= '0';
-- end if;
--end if;
end if;
if(config.filter_raw = '1') then
if (config.filter_raw = '1') then
match_raw <= header_i.is_raw;
......@@ -247,8 +186,7 @@ begin -- arch
end if;
match <= match_type0 and match_type1 and match_type2 and match_type3 and
match_dst_mac and match_dst_ip and match_ethertype and
match <= match_dst_mac and match_dst_ip and match_ethertype and
match_dst_port and match_udp and match_raw and config.enable;
......
hdl/rtl/endpoint/mt_rmq_rx_deframer.vhd
View file @ 84040ec9
......@@ -40,7 +40,6 @@ entity mt_rmq_rx_deframer is
p_header_valid_o : out std_logic;
p_is_udp_o : out std_logic;
p_is_raw_o : out std_logic;
p_is_tlv_o : out std_logic;
p_src_mac_o : out std_logic_vector(47 downto 0);
p_dst_mac_o : out std_logic_vector(47 downto 0);
p_ethertype_o : out std_logic_vector(15 downto 0);
......@@ -48,9 +47,7 @@ entity mt_rmq_rx_deframer is
p_dst_port_o : out std_logic_vector(15 downto 0);
p_src_ip_o : out std_logic_vector(31 downto 0);
p_dst_ip_o : out std_logic_vector(31 downto 0);
p_udp_length_o : out std_logic_vector(15 downto 0);
p_tlv_type_o : out std_logic_vector(31 downto 0);
p_tlv_size_o : out std_logic_vector(15 downto 0));
p_udp_length_o : out std_logic_vector(15 downto 0));
end mt_rmq_rx_deframer;
architecture arch of mt_rmq_rx_deframer is
......@@ -83,7 +80,7 @@ architecture arch of mt_rmq_rx_deframer is
return if_false;
end if;
end f_pick;
signal dummy : std_logic_vector(15 downto 0);
signal state : t_state;
......@@ -208,9 +205,5 @@ begin
end if;
end if;
end process p_fsm;
p_is_tlv_o <= '0';
end arch;
hdl/rtl/endpoint/mt_rmq_rx_path.vhd
View file @ 84040ec9
......@@ -63,7 +63,6 @@ begin
p_header_valid_o => p_header_valid_o,
p_is_udp_o => p_header_o.is_udp,
p_is_raw_o => p_header_o.is_raw,
p_is_tlv_o => p_header_o.is_tlv,
p_src_mac_o => p_header_o.src_mac,
p_dst_mac_o => p_header_o.dst_mac,
p_ethertype_o => p_header_o.ethertype,
......@@ -71,9 +70,7 @@ begin
p_dst_port_o => p_header_o.dst_port,
p_src_ip_o => p_header_o.src_ip,
p_dst_ip_o => p_header_o.dst_ip,
p_udp_length_o => p_header_o.udp_length,
p_tlv_type_o => p_header_o.tlv_type,
p_tlv_size_o => p_header_o.tlv_size);
p_udp_length_o => p_header_o.udp_length);
U_stream_register : entity work.mt_rmq_stream_register
port map (
......
hdl/rtl/mqueue/mt_rmq_rx.vhd
View file @ 84040ec9
......@@ -94,8 +94,7 @@ begin
addr => unsigned(c_mqueue_addr_header) + 8,
is_even => '1',
payload_size => (others => '0'),
is_hdr_d => 'X'
);
is_hdr_d => 'X');
else
-- Wait until a slot is ready.
snk_o <= (pkt_ready => '0',
......
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