hdl: add missing signal to sensitivity list

71f76b73 · Dimitris Lampridis · 32333315 · 71f76b73
Commit 71f76b73 authored Aug 02, 2018 by Dimitris Lampridis
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mt_rmq_endpoint_tx.vhd hdl/rtl/endpoint/mt_rmq_endpoint_tx.vhd +1 -1

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--- a/hdl/rtl/endpoint/mt_rmq_endpoint_tx.vhd
+++ b/hdl/rtl/endpoint/mt_rmq_endpoint_tx.vhd
@@ -89,7 +89,7 @@ begin  -- arch
    end if;
  end process p_write_config_regs;

-  p_read_config_regs : process(snk_config_i)
+  p_read_config_regs : process(config, snk_config_i)
  begin
    case to_integer(unsigned(snk_config_i.adr(9 downto 2))) is
      when c_ADDR_CONFIG =>