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V5.0 gateware release
| Project | Open issues | State | Due date |
|---|---|---|---|
| FMC ADC 100M 14b 4cha - Gateware | 3 | Open | expired on Sep 30, 2019 |
Unstarted Issues (open and unassigned)
0
Ongoing Issues (open and assigned)
3
- FMC ADC 100M 14b 4cha - Gateware · Account for trigger sample in post-trigger samples
- FMC ADC 100M 14b 4cha - Gateware · Cannot use last DPRAM sample
- FMC ADC 100M 14b 4cha - Gateware · Expose more info in the status and/or interrupt registers
Completed Issues (closed)
18
- FMC ADC 100M 14b 4cha - Gateware · hdl - Replace glitch filter with dual threshold FSM
- FMC ADC 100M 14b 4cha - Gateware · hdl - Review and sanitize reset logic
- FMC ADC 100M 14b 4cha - Gateware · hdl - Trim unused clock signals
- FMC ADC 100M 14b 4cha - Gateware · Add White Rabbit support
- FMC ADC 100M 14b 4cha - Gateware · Replace "decimation" with "under-sampling"
- FMC ADC 100M 14b 4cha - Gateware · Add "trigger on time" functionality
- FMC ADC 100M 14b 4cha - Gateware · Add option to tag based on WR time
- FMC ADC 100M 14b 4cha - Gateware · Add extra trigger input from FPGA logic
- FMC ADC 100M 14b 4cha - Gateware · Implement a basic WR trigger message
- FMC ADC 100M 14b 4cha - Gateware · hdl - switch to 125MHz clock source
- FMC ADC 100M 14b 4cha - Gateware · gateware manual: wrong data format reported for channel status registers
- FMC ADC 100M 14b 4cha - Gateware · Replace hardware trigger enable logic
- FMC ADC 100M 14b 4cha - Gateware · Update testbench
- FMC ADC 100M 14b 4cha - Gateware · Update Gennum core to address critical freeze issue
- FMC ADC 100M 14b 4cha - Gateware · Misalignment of external trigger wrt data
- FMC ADC 100M 14b 4cha - Gateware · Add correct delays to all trigger sources
- FMC ADC 100M 14b 4cha - Gateware · Wrong sampling clock freqency in the Xilinx constraints
- FMC ADC 100M 14b 4cha - Gateware · doc - fix formula for calculating the corrected DAC value