Ready for PCB layout review.
Project | Open issues | State | Due date |
---|---|---|---|
Simple VME FMC Carrier 7 - SVEC7 | 3 | Open |
Unstarted Issues (open and unassigned)
1
- Simple VME FMC Carrier 7 - SVEC7 · AFPGA Flash/AFPGA configuration issues
Ongoing Issues (open and assigned)
2
- Simple VME FMC Carrier 7 - SVEC7 · Perform test synthesis/P&R with the new pin assignment
- Simple VME FMC Carrier 7 - SVEC7 · Documentation-related issues
Completed Issues (closed)
20
- Simple VME FMC Carrier 7 - SVEC7 · Bypass caps in FT4232
- Simple VME FMC Carrier 7 - SVEC7 · VAdj PSU should be controlled by the AFPGA
- Simple VME FMC Carrier 7 - SVEC7 · Clocking: consider removing IC20 and SFP_CLK?
- Simple VME FMC Carrier 7 - SVEC7 · Clocking: remove PLLFMC1_CLK/PLLFMC2_CLK.
- Simple VME FMC Carrier 7 - SVEC7 · Clocking: Kintex-7 doesn't support LVPECL.
- Simple VME FMC Carrier 7 - SVEC7 · IC4C: swapped Flash_MISO and Flash_MOSI lines.
- Simple VME FMC Carrier 7 - SVEC7 · Question about I/O expander connection
- Simple VME FMC Carrier 7 - SVEC7 · Pulldowns missing on IOEXP_RCLK and IOEXP_RESET
- Simple VME FMC Carrier 7 - SVEC7 · Do we need voltage translation to Vadj_FMC for FMC JTAG and I2C?
- Simple VME FMC Carrier 7 - SVEC7 · Use CERN library components
- Simple VME FMC Carrier 7 - SVEC7 · CDCM61004 VCCVCO connection
- Simple VME FMC Carrier 7 - SVEC7 · IC8 VIN decoupling cap value
- Simple VME FMC Carrier 7 - SVEC7 · LDO Soft-start time is set to 1s, is such a long time intentional?
- Simple VME FMC Carrier 7 - SVEC7 · AFPGA_1V0: mixed-up LDO feedback dividers
- Simple VME FMC Carrier 7 - SVEC7 · DDR3 swapped
- Simple VME FMC Carrier 7 - SVEC7 · TPS74401RGWT bias
- Simple VME FMC Carrier 7 - SVEC7 · P1V0 considerations
- Simple VME FMC Carrier 7 - SVEC7 · VP_0 and VN_0
- Simple VME FMC Carrier 7 - SVEC7 · sfpga: read dtack
- Simple VME FMC Carrier 7 - SVEC7 · Add serial EEPROM that are preprogrammed with MAC address